KR100699585B1 - Output buffer circuit - Google Patents

Abstract

An output buffer circuit according to the present invention comprises: an input terminal to which a differential input voltage signal is applied to two input terminals; A class AB output stage configured to increase a current flowing through the output stage when the difference between the differential input voltage is greater than zero; A floating current source for biasing the class AB output stage; A summing circuit connected to the input terminal, the floating current source, and the class AB output terminal to sum the current supplied from the input terminal and the internal current supplied from the floating current source; A clamp circuit connected to the summing circuit and the class AB output terminal to limit a magnitude of a voltage swing generated during slewing; And a flipped voltage follower connected to the input terminal and the clamp circuit to transfer a bias current only when a slewed differential input voltage signal is applied, wherein the slewed differential input voltage is an upslewed differential input. Voltage or down-slewing differential input voltage.

Output buffer circuit, transistor, slew rate, slewing, bias current,

Description

Output buffer circuit {OUTPUT BUFFER CIRCUIT}

Figure 1a is an output buffer modeled according to the prior art

1B is a view showing an input voltage signal and an output voltage signal according to the prior art;

2 is a circuit diagram of an output buffer circuit according to the prior art.

3 is a circuit diagram of an output buffer circuit according to the present invention.

4A is a circuit diagram of an output buffer circuit operating during upslewing according to the present invention.

4B is a circuit diagram of an output buffer circuit operating during downslewing according to the present invention.

5A is an output buffer modeled according to the present invention.

5b is a view comparing waveforms of the output voltage according to the present invention and the output voltage according to the prior art;

<Description of Major Symbols in Drawing>

300: output buffer circuit 301a to 301f: input terminal

301a: first NMOS transistor 301b: second NMOS transistor 301c: first PMOS transistor 301d: second PMOS transistor 301e: third PMOS transistor 301f: third NMOS transistor 302a to 302d: floating current source 302c 4th PMOS Transistor 302d 4th NMOS Transistor 303a to 303h Summing Circuit

303c: fifth PMOS transistor 303d: sixth PMOS transistor

303g: Fifth NMOS transistor 303h: Sixth NMOS transistor

304a, 304b: Class AB output terminal 304a: Seventh PMOS transistor

304b: 7th NMOS transistor 305a-305d: clamp circuit 306a: 8th NMOS transistor 306b: 8th PMOS transistor 306c: 9th NMOS transistor 306d: 9th PMOS transistor 500: output buffer 501a: input voltage signal

501b: Output voltage waveform according to the prior art

501c: output voltage waveform according to the present invention

Iss: Input Bias Current

Ip: Class AB output bias current t: Data transfer time

The display field is evaluated as an advanced technology field that can lead the future in the electronics industry. Accordingly, a number of liquid crystal display (LCD) and plasma display panel (PDP) products are being released.

Currently, as a next generation technology, development of various display devices is actively progressed, and among them, development of SOM (Spatial Optical Moulator) devices is most actively progressed. The output resolution of SOM (Spatial Optical Modulator) driver ICs is currently 8 bits, but more than 10 bits will be put to practical use in the next few years. Therefore, high-speed, high-precision driver circuits are required for its driving.

High slewing rate is required to maintain high speed and high accuracy. Here, the slew rate means the amount of change in the output per unit time of the output change with respect to the step change of the control input signal, a driver circuit having a high slew rate is required to deliver a more accurate video signal within a predetermined data transmission time.

FIG. 1A illustrates an output buffer 100 modeled according to the prior art, and FIG. 1B illustrates an input voltage signal and an output voltage signal according to the prior art.

As shown in FIGS. 1A and 1B, the output buffer 100 according to the related art may be modeled as a large capacity capacitor Coff of 50 pF or more. Accordingly, the parasitic capacitor may be generated due to the capacitor Coff, which causes a delay in the video signal, thereby preventing the accurate video signal from being delivered within a given data transmission time t.

That is, referring to FIG. 1B, when the up-slewed input signal is applied for a predetermined data transmission time t, it can be seen that the output image signal a of a predetermined size is not transmitted. Similarly, down-slewing Even when the input signal is applied, it can be seen that the output image signal b of a predetermined size is not transmitted. Therefore, if the output voltage is increased when the up-slewed input signal is applied, and the output voltage is decreased when the down-slewed input signal is applied, the slew rate in the circuit is improved, thereby making the video signal more accurate. Will be able to deliver.

2 shows a circuit diagram of an output buffer circuit 200 according to the prior art.

The output buffer circuit 200 according to the prior art biases the input terminals 201a to 201f and the class AB output terminals 204a and 204b to which differential input voltage signals are applied to two input terminals, as shown in FIG. The current supplied from the input terminals 201a to 201f connected to the floating current sources 202a to 202d, the input terminals 201a to 201f, the floating current sources 202a to 202d, and the class AB output terminals 204a to 204b. Summing circuits 203a to 203h for summing internal currents supplied from the floating current sources 202a to 202d, and class AB output terminals 204a for outputting a voltage by increasing the current flowing through the output terminal when the difference between the differential input voltages is greater than 0; 204b) and clamp circuits 205a to 205d connected to the summing circuits 203a to 203h and the class AB output terminals 204a and 204b to limit the magnitude of the voltage swing generated during slewing. Here, the differential input voltage means a difference between the voltages applied to the two input terminals, and accordingly, the output buffer according to the prior art is irrespective of the magnitude of the voltage applied between the two input terminals and the common point. An input circuit scheme that operates only in response to a difference in voltage applied to the two input terminals is introduced.

Referring to the output buffer circuit 200 illustrated in FIG. 2, the operation of improving the slew rate is as follows.

When the bias current of the input terminals 201a to 201f is Is and the current biased to the class AB output terminal through the floating current sources 202a to 202d is Ip and the mutual conductance of the MOS transistor is g _m . When the differential input voltage applied to 201f) becomes Iss / g _m or more, that is, when the slewed differential input voltage is applied, some of the transistors of the input terminals 201a to 201f are turned on, and some are turned off. As a result, the bias current Iss flows only through some transistors.

That is, the above operation process will be described below by dividing the case where the up-slewed input voltage and the down-slewing input voltage are applied.

First, when the up-slewed input voltage is applied, that is, the gate voltages of the first NMOS transistor 201a and the first PMOS transistor 201c are the second NMOS transistor 201b and the second PMOS transistor. When Iss / g _{m is} higher than the gate voltage of 201d, only the first NMOS transistor 201a and the second PMOS transistor 201d are turned on, and the bias current Iss is the first NMOS transistor ( 201a) and the current flowing only through the second PMOS transistor 201d and biased to the class AB output terminals 204a and 204b through the floating current sources 202a to 202d are defined as Ip. The bias current Iss is supplied through the discharge of Cc. Therefore, the source voltage of the sixth PMOS transistor 203d is lowered until the bias current Iss is completely supplied through the discharge of the compensation capacitive load Cc, and the seventh PMOS transistor 204a The gate voltage is also lowered, whereby the output voltage Vout is raised, so that the slew rate in the circuit is improved.

On the other hand, when the down-slewed input voltage is applied, that is, the gate voltages of the first NMOS transistor 201a and the first PMOS transistor 201c are the second NMOS transistor 201b and the second PMOS. When the gate voltage of the transistor 201d is lower than Iss / g _m or more, only the first PMOS transistor 201c and the second NMOS transistor 201b are turned on so that the bias current Iss is the first PMOS. Only through the transistor 201c and the second NMOS transistor 201b. Since the current biased to the class AB output terminals 204a and 204b through the floating current sources 302a to 302d is set to Ip, the bias current Iss is charged to the compensation capacitive load Cc. Therefore, the source voltage of the sixth NMOS transistor 203h increases until the bias current Iss is fully charged in the compensation capacitive load Cc, and the gate voltage of the seventh NMOS transistor 204b also rises. As a result, the output voltage Vout is lowered and the slew rate in the circuit is improved.

However, in the output buffer used in the conventional driver, when the slew rate is increased for high speed and high precision characteristics, a large amount of power is consumed. This is because the slew rate is a value obtained by dividing the bias current Iss by the capacitance of the compensating capacitive load Cc (slew rate = Iss / Cc), which is proportional to the bias current Iss in the circuit. That is, since the compensatory capacitive load Cc needs to be charged and discharged in order to increase the slew rate, the bias current Iss must be increased. Accordingly, the increased bias is increased not only during slewing but also during the input voltage. Since a current flows in the circuit, a large amount of power is consumed.

Accordingly, the present invention has been made to solve the above problem, and by adding a flipped voltage follower composed of a plurality of transistors, the output voltage of a high slew rate even at a bias current similar to that of the output buffer used in the conventional driver. The present invention also provides an output buffer circuit that can prevent a large amount of power from being consumed by adding a flipped voltage follower that increases the bias current only during slewing.

According to an aspect of the present invention, an output buffer circuit includes: an input terminal to which a differential input voltage signal is applied to two input terminals; A class AB output stage configured to increase a current flowing through the output stage when the difference between the differential input voltage is greater than zero; A floating current source for biasing the class AB output stage; A summing circuit connected to the input terminal, the floating current source, and the class AB output terminal to sum the current supplied from the input terminal and the internal current supplied from the floating current source; A clamp circuit connected to the summing circuit and the class AB output terminal to limit a magnitude of a voltage swing generated during slewing; And a flipped voltage follower connected to the input terminal and the clamp circuit to deliver a bias current only when a slewed differential input voltage signal is applied, wherein the differential input voltage is an up-slewed differential input voltage. It features.

delete

The input terminal may include first and second NMOS transistors to which the up-slewed differential input voltage is applied to a gate; First and second PMOS transistors to which the up-slewed differential input voltage is applied to a gate; A third PMOS transistor for biasing the first and second NMOS transistors; And a third NMOS transistor for biasing the first and second PMOS transistors.

The flipped voltage follower may further include: an eighth NMOS transistor configured to receive the up-slewed differential input voltage at a gate thereof and to be connected to a drain of a third PMOS transistor at the input terminal; An eighth PMOS transistor, to which the up-slewed differential input voltage is applied to a gate, and connected to a drain of a third NMOS transistor of the input terminal; A ninth NMOS transistor connected to the source of the eighth NMOS transistor; And a ninth PMOS transistor connected to the source of the eighth PMOS transistor.

The first NMOS transistor and the second PMOS transistor of the input terminal may be turned on, and the first PMOS transistor and the second NMOS transistor may be turned off.

The eighth NMOS transistor and the eighth PMOS transistor of the flipped voltage follower are turned off, and the ninth NMOS transistor and the ninth PMOS transistor are turned on.

On the other hand, another output buffer circuit for achieving the above object, the input terminal to which the differential input voltage signal is applied to the two input terminals; A class AB output stage configured to increase a current flowing through the output stage when the difference between the differential input voltage is greater than zero; A floating current source for biasing the class AB output stage; A summing circuit connected to the input terminal, the floating current source, and the class AB output terminal to sum the current supplied from the input terminal and the internal current supplied from the floating current source; A clamp circuit connected to the summing circuit and the class AB output terminal to limit a magnitude of a voltage swing generated during slewing; And a flipped voltage follower connected to the input terminal and the clamp circuit to deliver a bias current only when a slewed differential input voltage signal is applied, wherein the differential input voltage is a down-slewed differential input voltage. It is characterized by.

In this case, the input terminal may include: first and second NMOS transistors to which the down-slewed differential input voltage is applied to a gate; First and second PMOS transistors to which the down-slewed differential input voltage is applied to a gate; A third PMOS transistor for biasing the first and second NMOS transistors; And a third NMOS transistor for biasing the first and second PMOS transistors.

The flipped voltage follower may include: an eighth NMOS transistor connected to the drain of the third PMOS transistor of the input terminal by applying the down-slewed differential input voltage to a gate; An eighth PMOS transistor, to which the down-slewed differential input voltage is applied to a gate, and connected to a drain of a third NMOS transistor of the input terminal; And a ninth NMOS transistor connected to a source of the eighth NMOS transistor; and a ninth PMOS transistor connected to a source of the eighth PMOS transistor.

The first PMOS transistor and the second NMOS transistor of the input terminal may be turned on, and the first NMOS transistor and the second PMOS transistor may be turned off.

The eighth NMOS transistor and the eighth PMOS transistor of the flipped voltage follower are turned off, and the ninth NMOS transistor and the ninth PMOS transistor are turned on.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 shows a circuit diagram of an output buffer circuit 300 according to the present invention. As shown in FIG. 3, the output buffer circuit 300 according to the present invention biases the input terminals 301a to 301f and the class AB output terminals 304a and 304b to which differential input voltage signals are applied to two input terminals. Connected to the floating current source 302a to 302d, the input terminals 301a to 301f, the floating current source 302a to 302d, and the class AB output terminals 304a and 304b to supply current from the input terminals 301a to 301f. And summing circuits 303a to 303h for summing the internal currents supplied from the floating current sources 302a to 302d, and class AB output terminals 304a for outputting a voltage by increasing the current flowing through the output stage when the difference between the differential input voltages is greater than zero. Is connected to the summing circuits 303a to 303h and the class AB output terminals 304a and 304b to limit the magnitude of the voltage swing generated during slewing, and the input terminal 301a. To 301f) and clamp circuits 305a to 305d If the differential input voltage signal applied to only it consists of a flip-de voltage follower (306a ~ 306d) for delivering a bias current.

The input terminals 301a to 301f include a first NMOS transistor 301a and a first PMOS transistor 301c having the same node as one terminal to which the differential input voltage Vin + is applied, and the differential input voltage ( The second NMOS transistor 301b, the second PMOS transistor 301d, and the first and second NMOS transistors 301a and 301b having the same node as the other terminal to which Vin- is applied are biased. And a third NMOS transistor 301f for biasing the first and second PMOS transistors 301c and 301d. Here, the differential input voltage means the difference between the voltage applied to the two input terminals, according to the present invention, regardless of the magnitude of the voltage applied between the two input terminals and the common point, the two inputs An input circuit scheme that operates in response only to the difference in voltage applied to a terminal is introduced.

As shown in FIG. 3, since the input terminals 301a to 301f are configured by using the NMOS transistor and the PMOS transistor, the voltages of the entire range from the ground voltage to the power supply voltage VDD can be ensured as the input / output voltage. do. As such, an input terminal capable of securing an input / output voltage of a voltage range from the ground voltage to the power supply voltage VDD is called a rail to rail input terminal, and thus, as an output buffer according to the present invention, the rail to rail It is preferable to use a folded cascode operational amplifier having an input.

The clamp circuits 305a to 305d serve to limit the magnitude of the voltage swing generated during slewing. This will be described in detail below.

During up-slewing, if the source voltage of the sixth PMOS transistor 303d falls below a predetermined voltage, the sixth PMOS transistor 303d is turned off, and the source voltage of the fifth NMOS transistor 303g is a constant voltage. In this case, the fifth NMOS transistor 303g is turned off. In addition, during down slewing, when the source voltage of the fifth PMOS transistor 303c falls below a predetermined voltage, the fifth PMOS transistor 303c is turned off, and the source voltage of the sixth NMOS transistor 303h is reduced. When the voltage rises above the predetermined voltage, the sixth NMOS transistor 303h is turned off. Therefore, in order to prevent this, by adding the clamp circuits 305a to 305d, the magnitudes of the source voltage fluctuations of the fifth and sixth PMOS transistors 303c and 303d and the fifth and sixth NMOS transistors 303g and 303h are reduced. In this case, the fifth and six PMOS transistors 303c and 303d and the fifth and sixth NMOS transistors 303g and 303h may be prevented from being turned off.

The flipped voltage followers 306a to 306d may include an eighth NMOS transistor 306a to which the differential input voltage is applied to a gate and connected to a drain of the third PMOS transistor 301e of the input terminals 301a to 301f. ), The differential input voltage is applied to a gate, and an eighth PMOS transistor 306b and an eighth NMOS transistor 306a connected to a drain of the third NMOS transistor 301f of the input terminals 301a to 301f. The NMOS transistor 306c is connected to the source of the N MOS transistor 306c, and the ninth PMOS transistor 306d is connected to the source of the eighth PMOS transistor 306b.

Meanwhile, as shown in FIG. 3, the eighth NMOS transistor 306a and the first and second NMOS transistors 301a and 301b are all designed identically, and the eighth PMOS transistor 306b and the first, Both PMOS transistors 301c and 301d are designed in the same manner, and the same voltage as the differential input voltage is applied to the gates of the eighth NMOS transistor 306a and the eighth PMOS transistor 306b. Voltages between gates and sources of the eighth NMOS transistor 306a and the eighth PMOS transistor 306b and the first and second NMOS transistors 301a and 301b and the first and second PMOS transistors 301c and 301d. These are all the same, and the magnitude of the current 2Iss, which is the sum of the current Iss biased in the third PMOS transistor 301e and the current Iss biased in the third NMOS transistor 301f, Transistors constituting the input terminals 301a to 301f Among them, the magnitudes of the currents 2Iss, the sum of the currents Iss / 2 flowing through the first and second NMOS transistors 301a and 301b and the first and second PMOS transistors 301c and 301d, respectively, are the same.

When the current biased to the class AB output terminals 304a and 304b through the floating current sources 302a to 302d is Ip, the differential input voltage equal to or greater than Iss / g _m is applied to the input terminals 301a to 301f. When applied and slewing occurs, the eighth NMOS transistor 306a and the eighth PMOS transistor 306b are turned off, and the ninth NMOS transistor 306c and the ninth PMOS transistor 306d are turned on. Thus, the magnitude of the current flowing through the first NMOS transistor 301a and the second PMOS transistor 301d or the first PMOS transistor 301c and the second NMOS transistor 301b is larger than that of the normal state. Will increase. Thus, an increased bias current of 2Iss + α flows only when slewing occurs.

Hereinafter, an exemplary embodiment of using the output buffer circuit 300 shown in FIG. 3 to improve the slew rate and to reduce power consumption for the bias current will be described in detail.

Example 1

4A shows a circuit diagram of an output buffer circuit operating during upslewing according to the present invention.

In the up-slewing operation, that is, the gate voltages of the first NMOS transistor 301a and the first PMOS transistor 301c are higher than the gate voltages of the second NMOS transistor 301b and the second PMOS transistor 301d. When Iss / g _m or more, only the first NMOS transistor 301a and the second PMOS transistor 301d are turned on, so that the bias current Ib of 2Iss + α magnitude is the first NMOS transistor 301a. ) And the second PMOS transistor 301d. Since the current biased to the class AB output terminals 304a and 304b through the floating current sources 302a to 302d is set to Ip, the bias current Ib is supplied through the discharge of the compensating capacitive load Cc. Therefore, the source voltage of the sixth PMOS transistor 303d is lowered until the bias current Ib is completely supplied through the discharge of the compensation capacitive load Cc, and the gate of the seventh PMOS transistor 304a is reduced. Since the voltage also drops, the fourth PMOS transistor 302c is turned off so that the current Ip flows only through the fourth NMOS transistor 302d. At this time, the gate voltage of the seventh PMOS transistor 304a is lowered to V _b2 -V _THN (V _THN : thermal voltage of the NMOS transistor). As a result, the output voltage Vout is increased to increase the voltage in the circuit. Lu rate is improved.

Example 2

Figure 4b shows a circuit diagram of the output buffer circuit operating in downslewing according to the present invention.

In the down slewing operation, that is, the gate voltages of the first NMOS transistor 301a and the first PMOS transistor 301c are the gate voltages of the second NMOS transistor 301b and the second PMOS transistor 301d. When Iss / g _m or more lower, only the first PMOS transistor 301c and the second NMOS transistor 301b are turned on, so that a bias current Ib of 2Iss + α size is obtained by the first PMOS transistor ( Only through 301c and the second NMOS transistor 301b. Since the current biased to the class AB output terminals 304a and 304b through the floating current sources 302a to 302d is defined as Ip, the bias current Ib is charged to the compensation capacitive load Cc. Therefore, the source voltage of the sixth NMOS transistor 303h increases until the bias current Ib is fully charged in the compensation capacitive load Cc, and the gate voltage of the seventh NMOS transistor 304b also increases. As a result, the fourth NMOS transistor 302d is turned off so that the current Ip flows only through the fourth PMOS transistor 302c. At this time, the gate voltage of the seventh NMOS transistor 304b rises to V _b1- | V _THP | (V _THP : column voltage of the PMOS transistor), and accordingly, the output voltage Vout is lowered, thereby reducing the circuit voltage. The slew rate inside is improved.

5A and 5B are diagrams showing simulation results according to the present invention.

5A is a diagram illustrating an output buffer 500 modeled according to the present invention. Simulation performed through the modeled output buffer 500 is performed under a condition of a power supply voltage VDD of 15V and a ground voltage of 0V. The capacitance of the capacitor Coff constituting the SOM device and the data line was modeled at 50pF.

Figure 5b is a view comparing the waveform of the output voltage according to the present invention and the output voltage according to the prior art.

As shown in FIG. 5B, it can be seen that for the input voltage 501a to be applied, the output voltage 501c according to the present invention has a much improved slew rate than the output voltage 501b according to the prior art. .

Table 1 is for comparing the characteristics of the output buffer circuit according to the prior art and the present invention.

 As shown in Table 1, the characteristics such as quiescent current, open loop gain, phase margin, etc. at the same power supply voltage (VDD) are almost the same as in the conventional output buffer circuit. It can be seen that the degree of slew rate is improved.

Preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and various substitutions, modifications, and changes within the scope of the technical spirit of the present invention for those skilled in the art to which the present invention pertains. Modifications may be made and such substitutions, changes and the like should be regarded as belonging to the following claims.

As described above, in the output buffer circuit according to the present invention, by adding a flipped voltage follower composed of a plurality of transistors, the output of the high slew rate even at a bias current similar to the bias current of the output buffer used in the conventional driver. The voltage can be obtained.

In addition, since only a flipped voltage follower consisting of four transistors needs to be added to the output buffer used in the conventional driver, the implementation itself is simple.

In addition, by adding a flipped voltage follower that increases the bias current only during slewing, it is possible to prevent a large amount of power from being consumed.

Claims (11)

delete An input terminal to which a differential input voltage signal is applied to two input terminals; A class AB output stage configured to increase a current flowing through the output stage when the difference between the differential input voltage is greater than zero; A floating current source for biasing the class AB output stage; A summing circuit connected to the input terminal, the floating current source, and the class AB output terminal to sum the current supplied from the input terminal and the internal current supplied from the floating current source; A clamp circuit connected to the summing circuit and the class AB output terminal to limit a magnitude of a voltage swing generated during slewing; And And a flipped voltage follower connected to the input terminal and the clamp circuit to transfer a bias current only when a slewed differential input voltage signal is applied. And said differential input voltage is an up-slewed differential input voltage. The method of claim 2, wherein the input terminal, First and second NMOS transistors to which the up-slewed differential input voltage is applied to a gate; First and second PMOS transistors to which the up-slewed differential input voltage is applied to a gate; A third PMOS transistor for biasing the first and second NMOS transistors; And And a third NMOS transistor for biasing the first and second PMOS transistors.  The method of claim 3, wherein the flipped voltage follower, An eighth NMOS transistor, wherein the up-slewed differential input voltage is applied to a gate and connected to a drain of a third PMOS transistor of the input terminal; An eighth PMOS transistor, to which the up-slewed differential input voltage is applied to a gate, and connected to a drain of a third NMOS transistor of the input terminal; A ninth NMOS transistor connected to the source of the eighth NMOS transistor; And And a ninth PMOS transistor connected to the source of the eighth PMOS transistor. The method of claim 3, The first NMOS transistor and the second PMOS transistor are turned on, and the first PMOS transistor and the second NMOS transistor are turned off. The method of claim 4, wherein The eighth NMOS transistor and the eighth PMOS transistor are turned off, and the ninth NMOS transistor and the ninth PMOS transistor are turned on. An input terminal to which a differential input voltage signal is applied to two input terminals; A class AB output stage configured to increase a current flowing through the output stage when the difference between the differential input voltage is greater than zero; A floating current source for biasing the class AB output stage; A summing circuit connected to the input terminal, the floating current source, and the class AB output terminal to sum the current supplied from the input terminal and the internal current supplied from the floating current source; A clamp circuit connected to the summing circuit and the class AB output terminal to limit a magnitude of a voltage swing generated during slewing; And And a flipped voltage follower connected to the input terminal and the clamp circuit to transfer a bias current only when a slewed differential input voltage signal is applied. And said differential input voltage is a downslewed differential input voltage. The method of claim 7, wherein the input terminal, First and second NMOS transistors to which the down-slewed differential input voltage is applied to a gate; First and second PMOS transistors to which the down-slewed differential input voltage is applied to a gate; A third PMOS transistor for biasing the first and second NMOS transistors; And And a third NMOS transistor for biasing the first and second PMOS transistors. The method of claim 8, wherein the flipped voltage follower, An eighth NMOS transistor, the downslewing differential input voltage being applied to a gate, and connected to a drain of a third PMOS transistor of the input terminal; An eighth PMOS transistor, to which the down-slewed differential input voltage is applied to a gate, and connected to a drain of a third NMOS transistor of the input terminal; A ninth NMOS transistor connected to the source of the eighth NMOS transistor; And And a ninth PMOS transistor connected to the source of the eighth PMOS transistor. The method of claim 8, The first PMOS transistor and the second NMOS transistor are turned on, and the first NMOS transistor and the second PMOS transistor are turned off. The method of claim 9, The eighth NMOS transistor and the eighth PMOS transistor are turned off, and the ninth NMOS transistor and the ninth PMOS transistor are turned on.

Images