KR100696804B1 - The Method for Driving Plasma Display Panel with Counter Type Electrode - Google Patents

Abstract

A method for driving a plasma display panel having counter electrodes is provided to effectively perform a reset discharge with a low voltage by applying a reset discharge pulse on scan and sustain electrodes. A rear substrate(10) is formed of a glass and forms a PDP(Plasma Display Panel) with a front substrate(20). Address electrodes(30) and first and second electrodes(40,50) are formed between the front and rear substrates. Barrier ribs define plural discharge cells(90) between the front and rear substrates. A fluorescent layer(80) is formed in a predetermined region of the discharge cell. A reset discharge period includes a writing discharge process, when discharges are performed between the first and address electrodes and between the second and address electrodes.

Description

{The Method for Driving Plasma Display Panel with Counter Type Electrode}

1 is a perspective view of a plasma display panel according to an embodiment of the present invention.

2 is a cross-sectional view taken along the line A-A of FIG.

3 is a sectional view taken along line B-B in FIG.

4 is a vertical cross-sectional view taken along line C-C of FIG. 2.

5 is a horizontal cross-sectional view corresponding to FIG. 2 of a plasma display panel according to another embodiment of the present invention.

6 is a driving waveform diagram according to a driving method of a plasma display panel according to an exemplary embodiment of the present invention.

7A to 7F illustrate wall charge distribution diagrams based on the driving waveform diagram of FIG. 6 according to an exemplary embodiment of the present invention.

8A is a driving waveform diagram of a plasma display panel according to another embodiment of the present invention.

FIG. 8B is a wall charge distribution diagram in the second erase discharge process of the driving waveform diagram of FIG. 8A.

9 is a driving waveform diagram of a plasma display panel according to another embodiment of the present invention.

10 is a driving waveform diagram of a plasma display panel according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10-back board 20-front board

30-address electrode 32-bus electrode

34-transparent electrode 36-front dielectric layer

40-first electrode 50-second electrode

60-dielectric layer

62-first dielectric layer 64-second dielectric layer

66-Inner Dielectric Layer 68-Protective Layer

70-Bulkhead 72-First Bulkhead

74-Second Bulkhead 76-Internal Bulkhead

80-phosphor layer 82-transmissive phosphor layer

90, 90a, 90b-discharge cell

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel. In particular, in a plasma display panel having an opposite discharge electrode, a pulse for reset discharge is applied to the scan electrode and the sustain electrode, and between the scan electrode and the address electrode and between the sustain electrode and the address electrode. The present invention relates to a method of driving a plasma display panel capable of simultaneously performing an effective reset discharge at a lower voltage.

Plasma Display Panel (Plasma Display Panel) is a visible light emitted by the phosphor excited by the ultraviolet light generated from the plasma obtained by performing a gas discharge in the state in which the discharge gas is injected into the discharge space formed between the two opposing substrates A panel for realizing an image by using means a panel used in a plasma display device which is one of flat display devices. A plasma display panel is generally formed with a scan electrode and an address electrode intersecting a discharge cell and a discharge cell partitioned by a front substrate, a rear substrate facing the front substrate, and a partition wall. The plasma display panel may be classified into a direct current type, an alternating current type, and a mixed type according to a structure and a driving principle. In addition, the plasma display panel may be classified into a surface discharge method and an opposite discharge method according to the discharge structure.

In the surface discharge method, since the distance between the scan electrode and the address electrode is large, a relatively large discharge start voltage is required, and the discharge is started in the region closest to the two electrodes, approximately at the center of the discharge cell, and then discharged. Moves to the edge region of the electrode. The discharge occurs in the center region because the discharge start voltage in this region is low. Once the discharge is initiated, the discharge is maintained under a voltage lower than the discharge start voltage due to the formation of space charge, and the voltage between the two electrodes gradually decreases with time. After the discharge starts, the intensity of the electric field decreases as ions and electrons accumulate in the central region, and the discharge disappears in this region. That is, since the voltage applied between the two electrodes decreases with time, a strong discharge occurs in the center region of the discharge cell (low light emitting efficiency), and a weak discharge occurs near the edge of the discharge cell (high light emitting efficiency). In addition, since the space between the scan electrode and the sustain electrode is relatively small, the discharge does not proceed in the inner region of the discharge cell. With this principle, the three-electrode surface discharge structure has a low ratio of heat used to heat electrons in the input energy and a low luminous efficiency.

Therefore, in recent years, in order to improve the shortcomings of the three-electrode discharge method, the development of the counter-discharge plasma display panel is in progress. In the opposite discharge method, the sustain electrode and the scan electrode are formed in the intermediate partition wall in the space between the front substrate and the rear substrate to face each other, and the address electrode is formed to cross the sustain electrode and the scan electrode. Therefore, in this counter discharge method, the distance between the scan electrode and the address electrode is shorter than that of the surface discharge method, so that the address voltage is relatively low. In addition, in the counter discharge method, since the discharge proceeds as a whole inside the discharge cell, the discharge space may be increased, thereby increasing the discharge efficiency.

In the opposite discharge method, the discharge cells may be arranged in various shapes as compared with the surface discharge method, and may include a matrix type arrangement and a delta type arrangement. In the matrix arrangement, the discharge cells are uniformly arranged in one direction and the other direction, and a phosphor layer having the same color is formed in one direction. Therefore, in the matrix type arrangement, three discharge cells arranged side by side form one pixel. The delta type arrangement is an arrangement in which three discharge cells adjacent to each other in which phosphor layers emitting different colors of visible light are formed are substantially triangular to form one pixel.

In driving the opposite discharge type plasma display panel, there is a problem in that it is difficult to directly apply the driving waveform applied to the three-electrode surface discharge method. The driving waveform applied to the conventional 3-electrode surface discharge method scans by applying a positive voltage to the scan electrode and applying a relatively low voltage to the sustain electrode and the address electrode during the writing discharge process of the reset section. After the electrons are accumulated in the electrodes and the ions are accumulated in the sustain electrode and the address electrode, wall charges suitable for addressing are removed by erasing a part of the electrons of the scan electrode and the ions of the sustain electrode during the erase discharge of the reset period. Accumulate in the electrode.

On the other hand, in the counter discharge structure, since the distance between the scan electrode and the sustain electrode is greater than the distance between the address electrode and the sustain electrode, the discharge start voltage can be relatively large. Therefore, the writing discharge process of the reset period starts with the discharge between the address electrode and the sustain electrode, and a voltage for discharge is applied between the sustain electrode and the scan electrode to initiate the discharge between the sustain electrode and the scan electrode. A voltage much higher than the discharge start voltage should be applied between the electrodes. This is because the voltage actually applied between the sustain electrode and the scan electrode is relatively decreased by the wall charges formed on the sustain electrode by the discharge between the address electrode and the sustain electrode. Therefore, when the driving waveform used in the three-electrode surface discharge type plasma display panel is applied to the structure of the opposite discharge type, a very high reset voltage is applied to the scan electrode during the writing discharge process of the reset section, which is relatively inefficient. There is a problem.

The present invention is to solve the above problems, in the plasma display panel having a counter discharge electrode by applying a pulse for the reset discharge to the scan electrode and the sustain electrode than between the scan electrode and the address electrode and between the sustain electrode and the address electrode It is an object of the present invention to provide a method of driving a plasma display panel that enables efficient reset discharge to proceed simultaneously at a low voltage.

In order to solve the above problems, the driving method of the plasma display panel of the present invention includes a first electrode and a second electrode formed to face each other between opposing front and rear substrates, and the first and second electrodes. A partition layer formed between the electrode and the rear substrate, an address electrode disposed on the lower surface of the front substrate to intersect the first electrode and the second electrode, and a phosphor layer formed on an area including an upper surface of the rear substrate and side surfaces of the partition substrates; A plasma display panel driving method comprising driving a plasma display panel including a reset discharge period, an address discharge period, and a sustain discharge period, wherein the reset discharge period is predetermined for the first electrode and the second electrode. Applying a second pulse of the voltage (Vset) at the same time between the first electrode and the address electrode and between the second electrode and the address electrode And a writing discharge process in which a transition occurs, wherein the address discharge period applies a scan pulse of a predetermined voltage Vsc having a sign opposite to the voltage applied in the reset discharge period to the first electrode, and simultaneously An address pulse having a predetermined voltage Va having the opposite sign as that of the first electrode is applied, and the second electrode is performed to apply and maintain a bias voltage Vb having the same sign as the voltage of the address pulse. It is done.

In addition, in the present invention, the first electrode and the second electrode formed to face each other between the opposing front substrate and the rear substrate, the partition wall formed between the first electrode and the second electrode and the rear substrate, the lower surface of the front substrate A plasma display panel including an address electrode disposed to intersect the first electrode and the second electrode, and a phosphor layer formed in an area including an upper surface of the rear substrate and side surfaces of the partition walls. In the method of driving a plasma display panel driven by a driving waveform including a discharge period, the reset discharge period is applied to the first electrode and the second electrode by applying a second waveform pulse 2_b1 pulse and a second_b2 pulse, respectively And a writing discharge process in which discharge occurs between an electrode and an address electrode and between a second electrode and an address electrode. Applies a sustain pulse of a predetermined voltage (Vs) having a sign opposite to the voltage applied to the writing discharge process to the first electrode, and simultaneously a predetermined voltage (signal having a sign opposite to the first electrode) to the address electrode. An address pulse of Va) may be applied, and the second electrode may be performed to apply and maintain a bias voltage Vb having the same sign as that of the address electrode.

In addition, the driving method of the plasma display panel according to the present invention is formed between a first electrode and a second electrode formed to face each other between the opposing front substrate and the rear substrate, and between the first electrode and the second electrode and the rear substrate. A plasma display panel including a partition wall formed thereon, an address electrode disposed on the bottom surface of the front substrate so as to intersect the first electrode and the second electrode, and a phosphor layer formed on an area including an upper surface of the back substrate and side surfaces of the partition walls; A driving method of a plasma display panel driven by a driving waveform including a discharge period, an address discharge period, and a sustain discharge period, wherein the reset discharge period is a ramp waveform that gradually increases to the first electrode and the second electrode. 2_c1 pulse and 2_c2 pulse are applied to discharge between the first electrode and the address electrode and between the second electrode and the address electrode, respectively. A writing discharge process occurring therein and a second erasing discharge process of applying third and third pulses having a ramp waveform gradually decreasing to the first electrode and the second electrode, respectively, wherein the address discharge period is the first electrode. A scan pulse of a predetermined voltage Vsc having the same sign as the voltage of the third_c1 pulse applied to the writing discharge process is applied to the scan electrode, and at the same time, a predetermined voltage Va having the sign opposite to the first electrode is applied to the address electrode. ), And the second electrode may be configured to maintain the bias voltage Vb having the same sign as the address electrode.

Hereinafter, a structure of a plasma display panel having a counter discharge electrode and a driving method thereof will be described in detail with reference to the accompanying drawings and embodiments.

First, the structure of the plasma display panel to which the driving method of the plasma display panel according to the embodiment of the present invention is applied will be described. Hereinafter, the driving method will be described based on the plasma display panel having the delta discharge cell structure, but it can be applied to the plasma display panel having the matrix discharge cell structure.

1 is a perspective view of a plasma display panel according to an embodiment of the present invention. 2 is a cross-sectional view taken along line A-A of FIG. 3 is a sectional view taken along line B-B in FIG. 4 is a vertical cross-sectional view taken along line C-C of FIG. 2.

1 to 4, a plasma display panel according to an exemplary embodiment of the present invention may include a back substrate 10, a front substrate 20, address electrodes 30, first electrodes 40, and a second substrate. The electrode 50 may be formed to include the dielectric layer 60, the partition walls 70, and the phosphor layer 80. Hereinafter, the plane of the component facing the front substrate 20 direction (+ Z direction in FIG. 1) is the upper surface, and the plane of the component facing the rear substrate 10 direction (-Z direction in FIG. 1) is divided into the lower surface. Will be explained.

The back substrate 10 is formed of a material such as glass and forms a plasma display panel together with the front substrate 20. The front substrate 20 is formed of a transparent material such as soda glass and is formed to face the rear substrate 10 at a predetermined interval. In addition, an address electrode 30, first electrodes 40, second electrodes 50, and barrier ribs 70 are formed in a space between the rear substrate 10 and the front substrate 20. In addition, a plurality of discharge cells 90 are partitioned by partition walls 70 between the rear substrate 10 and the front substrate 20, and a phosphor layer 80 is formed in a predetermined region inside the discharge cell 90. And a discharge gas for generating vacuum ultraviolet rays by plasma discharge.

The address electrodes 30 are formed to include the bus electrodes 32 and the transparent electrodes 34. The first electrodes 30 may be formed by address discharge voltages applied to the transparent electrodes 34 through the bus electrodes 32. 40, or address discharge occurs with the second electrodes 50.

The bus electrodes 32 extend in one direction (for example, the y direction in FIG. 1) on the lower surface 20a of the front substrate 20, and are disposed to be parallel to each other in the x-axis direction. The bus electrodes 32 are preferably arranged at intervals corresponding to half of the length of the discharge cell 90 in the x-axis direction. Accordingly, when the bus electrodes 32 penetrate the discharge cells 90 that are alternately arranged at the left and right about the first electrode 40 (or the second electrode 50) along the y-axis direction, the first One side of the electrode 40 penetrates into the center region of the discharge cell 90a, and the other side penetrates into the region between the discharge cells 90b.

The bus electrodes 32 are formed of metal electrodes to have a small width and a small electrical resistance in order to minimize blocking of visible light transmitted to the front substrate 20. The bus electrodes 32 are preferably formed of a metal material having excellent conductivity and low resistance, such as Ag, Al, or Cu.

The transparent electrode 34 is made of a transparent material such as indium tin oxide (ITO), has a predetermined width and length, and is preferably formed such that the planar shape has a rectangular shape. However, the transparent electrode 34 may also be formed in a shape such as an oval or a circle, and the shape is not limited thereto. The transparent electrode 34 is electrically coupled to the lower surface or the upper surface of the bus electrode 32, and is preferably formed symmetrically about the bus electrode 32. Accordingly, the transparent electrode 34 is disposed substantially in the center region of the discharge cell 90 and causes an address discharge with the first electrode 40.

The front dielectric layer 36 may be formed on the bottom surface of the front substrate 20 so as to cover the address electrode 30 as a whole. The front dielectric layer 36 electrically insulates the address electrode 30 and prevents the address electrode 30 from being damaged during the discharge process. In addition, a front protective layer 37 such as an MgO protective layer may be formed on the bottom surface of the front dielectric layer 36 to protect the address electrode 30 and the front dielectric layer 36. The front protective layer 37 is formed of MgO material used to protect the dielectric in the plasma display panel, and prevents the electrodes from being damaged during the discharge process, and serves to lower the discharge voltage by emitting secondary electrons. The front passivation layer 37 is mainly formed of a thin film by a sputtering method or an E-beam evaporation method.

The first electrodes 40 and the second electrodes 50 extend in a direction intersecting with the address electrode 30 (the x-axis direction in FIG. 1) and are alternately disposed, and adjacent discharge cells 90 are disposed. Each is shared. Accordingly, the first electrodes 40 and the second electrodes 50 face each other with respect to the discharge cell 90 to perform a pair of discharges. In addition, the first electrodes 40 and the second electrodes 50 are preferably formed such that the width in the horizontal direction is smaller than the height in the vertical direction when cut perpendicularly to the longitudinal direction. Accordingly, the first and second electrodes 40 and 50 allow the opposite discharge to proceed in a larger area. In addition, the first electrode 40 (hereinafter, the first electrode is set as the address electrode and the scan electrode for generating the address discharge) causes the address discharge to be generated in the opposite manner with the address electrode 30 in a larger area. The discharge can proceed efficiently. Here, although the first electrode 40 is set as the scan electrode and the second electrode 50 is set as the sustain electrode, the reverse direction may be set.

Since the first electrodes 40 and the second electrodes 50 are positioned above the partitions 70 and do not require transparency, the first electrodes 40 and the second electrodes 50 may be formed of metal electrodes of a general conductive metal. The first electrodes 40 and the second electrodes 50 are preferably formed of a metal material having excellent conductivity such as Ag, Al, or Cu, and having low resistance, and have a fast response speed due to discharge, and a signal is distorted. It is possible to reduce the power consumption required for sustain discharge, and there are various advantages. However, the material of the first electrodes 40 and the second electrodes 50 is not limited thereto, and various metals having excellent conductivity and low resistance may be used.

The dielectric layer 60 includes a first dielectric layer 62 and a second dielectric layer 64. In addition, the dielectric layer 60 may further include an internal dielectric layer 66 formed in a region where the first dielectric layer 62 and the second dielectric layer 64 cross each other. Therefore, the internal dielectric layer 66 may not be formed depending on the design of the plasma display panel.

The first dielectric layer 62 is formed to a predetermined thickness on the outer surfaces of the first electrodes 40 and the second electrodes 50. The first dielectric layer 62 prevents the electrodes from being damaged by the collision of charged particles accelerated during the discharge process. The first dielectric layer 62 is formed of a glass component including elements such as Pb, B, Si, Al and O, and fillers such as ZrO ₂ , TiO ₂ , Al ₂ O ₃ , Cr, Cu, Pigments such as Co, Fe and the like may be included and formed. However, the components of the first dielectric layer 62 are not limited thereto, but may be formed of various dielectric materials.

The second dielectric layer 64 intersects with the first dielectric layer 62 between the first dielectric layers 62 adjacent to each other, and is staggered from left to right around the first electrode 40 (or the second electrode 50). Arranged and formed. More specifically, the second dielectric layer 64 includes a second dielectric layer 64a formed on one side of the first electrode 40 and a second dielectric layer 64b formed on the other side of the second dielectric layer 64 in the x-axis direction. It is formed by moving by a length (l) corresponding to approximately half of the length of the (90). In addition, the second dielectric layer 64 has a predetermined width, and since the same electrode as the first electrode 40 and the second electrode 50 is not formed therein, the second dielectric layer 64 has a width smaller than that of the first dielectric layer 62. Can be formed. The second dielectric layer 64 may be formed of the same material as the first dielectric layer 62, but the material of the second dielectric layer 64 is not limited thereto and may be formed of various dielectric materials. .

The internal dielectric layer 66 is formed in a predetermined shape so as to face the inside of the discharge cell 90 in a region where the first dielectric layer 62 and the second dielectric layer 64 cross each other. In more detail, the internal dielectric layer 66 is formed in a predetermined shape at a vertex portion of the discharge cell 90 where the first dielectric layer 62 and the second dielectric layer 64 intersect to form a shape on the discharge cell 90. Is changed to octagonal shape, not square shape. The internal dielectric layer 66 is formed in a substantially triangular shape based on a planar shape, and is formed in contact with the first dielectric layer 62 and the second dielectric layer 64 so that the triangular diagonal lines face the discharge cell 90.

The internal dielectric layer 66 may be symmetrically formed with respect to the address electrode 30 (or the second dielectric layer 64) formed thereon. In this case, the inner dielectric layer 66 is spaced apart from each other so that the separation distance d between the address electrode 30 is at least the width w ₁ of the bus electrode 32 constituting the address electrode 30. Preferably it is formed so as to be spaced apart at least by the width w ₂ of the transparent electrode 34. Here, the separation distance d is a distance formed by vertices at positions close to the address electrode 30 in one discharge cell 90 in the x-axis direction when the internal dielectric layer 66 is formed in a triangular shape. it means. Therefore, since the width of the first dielectric layer 62 formed on the outer surface of the region where the address electrode 30 penetrates is not affected by the internal dielectric layer 66, the address voltage is increased. Will be minimized.

The internal dielectric layer 66 may be formed integrally with the first dielectric layer 62 or the second dielectric layer 64. Preferably, the first electrode 40 and the second electrode 50 in which sustain discharge proceeds. It is formed integrally with the first dielectric layer 62 formed on the outer surface. When an interface is formed between the first dielectric layer 62 and the internal dielectric layer 66, the first electrodes 40 and the second electrodes 50 may be affected by the interface in the sustain discharge process.

In addition, the internal dielectric layer 66 is preferably formed at the same height as the first dielectric layer 62. Accordingly, the internal dielectric layer 66 forms a uniform discharge space in the height direction in the discharge cell 90.

In addition, the dielectric layer 60 may have a protective layer 68 formed in a region including a side surface of the first dielectric layer 62 exposed inside the discharge cell. In addition, the protective layer 68 may be formed on the side surfaces of the second dielectric layer 64 and the internal dielectric layer 66 in addition to the first dielectric layer 62. The protective layer 68 is formed of an MgO protective layer made of a material including MgO used to protect a dielectric in a plasma display panel, and prevents electrodes from being damaged during the discharge process and emits secondary electrons to discharge the discharge voltage. It acts to lower.

The partition walls 70 are formed to include first partition walls 72 and second partition walls 74. In addition, the partitions 70 may further include inner partitions 76. The barrier ribs 70 partition the discharge cell 90 between the front substrate 20 and the rear substrate 10. The barrier ribs 70 may be formed of a glass component including elements such as Pb, B, Si, Al, and O, and the like, and the barrier ribs 70 are not limited to components of the barrier ribs 70. The barrier ribs 70 are preferably formed to have a width greater than the width of the dielectric layer layer 60 formed thereon to prevent the phosphor layer formed on the side surfaces of the barrier ribs 70 from being covered by the dielectric layer 60. Done.

The first partition walls 72 extend in one direction (the x direction in FIG. 1) on the top surface of the rear substrate 10 and are disposed under the first electrode 40 and the second electrode 50. The first electrode 40 and the second electrode 50 are disposed in parallel with each other at the same interval as the 40 and the second electrode 50.

The first partition walls 72 are formed on the upper surface of the first electrode 40 and the second electrode 50 with a width larger than the width of the phosphor layer 80 formed on the side of the first partition walls 72 It is minimized that the first electrode 40 and the second electrode 50 are covered. In addition, the first partitions 72 are preferably formed such that an upper surface thereof has a width greater than the width of the first dielectric layer 62 formed on the outer surfaces of the first electrodes 40 and the second electrodes 50. The phosphor layer formed on the side surfaces of the first barrier ribs 72 is prevented from being blocked by the first dielectric layer 62. In addition, the first partitions 72 are formed such that the width of the lower surface is larger than the width of the upper surface, and the ultraviolet rays formed by the sustain discharge which is carried out between the first electrode 40 and the second electrode 50 on the upper side are formed. One to allow more collision with the phosphor layer formed on the side of the partitions (72). In addition, the first partitions 72 are formed to have a width greater than the width of the second partitions 74 such that the first dielectric layer 62 has a width larger than that of the second dielectric layer 64.

The second partitions 74 are formed in a direction intersecting the first partitions 72 between the first partitions 72, and the first partitions 72 are disposed at both sides of the first partitions 72. Discharge cells 90 partitioned together are formed to be staggered from each other. The second partitions 74 are formed to have the same arrangement as the second dielectric layer 64 under the second dielectric layer 64. Accordingly, as described above, the discharge cells 90 formed by the first partition walls 72 and the second partition walls 74 may be discharge cells 90 at both sides of the first partition wall 72. ) Is formed by moving in the longitudinal direction of the first partition wall 72 (ie, the x-axis direction in FIG. 1) by a length corresponding to half of the length in the direction of the first partition wall 72.

The second partitions 74 are preferably formed such that an upper surface thereof has a width larger than that of the second dielectric layer 64 such that a phosphor layer formed on the side surfaces of the second partitions 74 is formed by the second dielectric layer 64. To prevent it from being obscured. In addition, the second partitions 74 are formed such that the width of the lower surface is larger than the width of the upper surface, and the ultraviolet rays formed by the sustain discharge which is carried out between the first electrode 40 and the second electrode 50 on the upper side are formed. More collisions to the phosphor layer formed on the sides of the two partitions (74).

The inner partitions 76 are formed in a predetermined shape to face the inside of the discharge cell 90 in a region where the first partitions 72 and the second partitions 74 intersect. The inner partitions 76 are preferably formed in a plane shape substantially the same as the inner dielectric layer 66. For example, the inner partitions 76 may have a triangular shape when the inner dielectric layer 66 is formed in a triangular shape. Accordingly, the inner partition wall 76 is formed in a predetermined shape at a vertex portion of the discharge cell 90 where the first partition 72 and the second partition 74 intersect to form a planar shape of the discharge cell 90 in a rectangular shape. It should be in octagon shape.

The inner partitions 76 are preferably formed such that a side surface facing the inside of the discharge cell 90 forms a plane substantially the same as the side surface of the inner dielectric layer 66 or protrudes a predetermined distance into the discharge cell 90. Therefore, the inner partitions 76 prevent the phosphor layer formed on the side surface from being blocked by the inner dielectric layer 66.

The phosphor layer 80 may be formed in a region including at least an upper surface of the rear substrate 10 in the discharge cell 90. In addition, the phosphor layer 80 may be formed on side surfaces of the partition walls 70 in the discharge cell 90. In this case, the partitions 70 may include at least one of the first partitions 72, the second partitions 74, and the inner partitions 76. The phosphor layers 80 may be formed in the direction of the rear substrate 10 based on the discharge space in the discharge cell 90, and thus may be formed as reflective phosphor layers.

The phosphor layer 80 has a component for generating visible light by receiving ultraviolet rays. The red phosphor layer formed in the red light emitting cell includes phosphors such as Y (V, P) O4: Eu, and the green light emitting cell The green phosphor layer formed at includes a phosphor such as Zn 2 SiO 4: Mn, and the blue phosphor layer formed at the blue light emitting discharge cell may include a phosphor such as BAM: Eu. The phosphor layer 80 is divided into red, green, and blue light emitting phosphor layers, and is formed in each of the adjacent discharge cells 90, and the red, green, and blue light emitting phosphor layers are adjacent to each other. The cells 90 are combined to form unit pixels for implementing a color image.

The discharge cells 90 are defined by the back substrate 10, the partition walls 70, and the front substrate 20. As mentioned above, the discharge cells 90 have a discharge cell 90a formed on one side of the first partition wall 72 and a discharge cell 90b formed on the other side of the first partition wall 72. Are staggered from each other by a length corresponding to half of the length of the discharge cell 90 in the direction. Thus, the discharge cell 90 has a delta structure as a whole, and three adjacent discharge cells form a triangle and form one pixel. In addition, since the discharge cells 90 formed on one side and the other side of the discharge cell 90 are alternately formed with respect to the first electrode 40, the address electrode 30 and the first electrode penetrating the discharge cell 90a are formed. When the address discharge is performed between the electrodes 40, the address discharge occurs in the discharge cell 90a on one side but no address discharge occurs in the discharge cell 90b on the other side. Therefore, in the plasma display panel according to the present invention, there is no need to use an alis driving method or an e-alis driving method generally applied to the counter discharge method. Therefore, in the plasma display panel of the present invention, the reset period is long during the discharging process, and thus the gray level expression that appears as the number of times in the sustain discharge period is relatively small becomes difficult.

 The discharge cell 90 is filled with a discharge gas (for example, a mixed gas including xenon (Xe), neon (Ne), etc.) to cause plasma discharge. Therefore, the discharge cells 90 are discharged in the interior to generate ultraviolet rays, and the generated ultraviolet rays collide with the phosphor layer 80 to emit visible light.

Next, a structure of a plasma display panel according to another embodiment of the present invention will be described. 5 is a partial horizontal cross-sectional view of a plasma display panel according to another embodiment of the present invention. Plasma display panel according to another embodiment of the present invention is the same or similar to some of the components of the embodiment of Figures 1 to 4, the following will be a portion different from the components of the embodiment of Figures 1 to 4. The explanation is centered. Accordingly, the same components as those of the embodiment of FIGS. 1 to 4 use the same reference numerals, and a detailed description thereof will be omitted.

Referring to FIG. 5, a plasma display panel according to another exemplary embodiment of the present invention includes a dielectric layer 160 including a first dielectric layer 62, a second dielectric layer 64, and an internal dielectric layer 166. . The internal dielectric layer 166 has an approximately triangular shape with respect to a planar shape, and has an arc shape having a predetermined curvature in the inclined surface. In addition, the internal dielectric layer 166 is preferably formed such that the inclined surface forms a convex arc with respect to the center of the discharge cell 190. Therefore, the internal dielectric layer is formed in a curved surface having a predetermined curvature and the discharge cells 190 can form a wider discharge space region.

Next, a method of driving a plasma display panel according to an exemplary embodiment of the present invention will be described. 6 illustrates a driving waveform diagram according to a method of driving a plasma display panel according to an exemplary embodiment of the present invention, and FIGS. 7A to 7F illustrate a wall charge distribution diagram based on the driving waveform diagram of FIG. 6 according to an exemplary embodiment of the present invention. .

In the driving waveform of the method of driving the plasma display panel according to the embodiment of the present invention, referring to FIG. 6, a subfield including a reset discharge period (I), an address discharge period (II), and a sustain discharge period (III) is repeated. It is done. In the driving of the plasma display panel, reset discharge, address discharge, and sustain discharge are repeatedly performed.

The reset discharge cycle (I) again includes a first erase discharge process (1), a writing discharge process (2) and a second erase discharge process (3). The reset discharge period (I) is a period of erasing wall charges formed on each electrode by the previous sustain discharge and forming wall charges necessary for stabilizing the next address discharge. Here, wall charges refer to charges that are formed on the walls (eg, dielectric layers) of discharge cells close to each electrode and accumulate in the electrodes. These wall charges are not actually in contact with the electrodes themselves, but here the wall charges are described as "stacked", "accumulated", "formed" on the electrodes.

The first erase discharge process 1 is a process of erasing wall charges formed in the sustain discharge cycle of the subfield previously performed. In this embodiment, assuming that the last sustain pulse of the sustain discharge cycle is applied to the first electrode, negative wall charges are accumulated on the first electrode and positive wall charges are accumulated on the second electrode. Therefore, in the first erase discharge process 1, a first pulse of a predetermined voltage Ve1 having a positive value is applied to the second electrode. In this case, the first electrode and the address electrode maintain a reference voltage (or ground voltage) state. The voltage Ve1 of the first pulse is set to a value substantially equal to the voltage Vs of the sustain pulse, and the application time of the first pulse is set relatively shorter than that of the sustain pulse. When the first pulse is applied to the second electrode in the first erasing discharge process 1, as shown in FIG. 7A, wall charges of the first electrode and the second electrode are erased.

The writing and discharging process (2) is a process of making a predetermined wall charge on the first electrode, the second electrode and the address electrode to make the wall charge state of each discharge cell of the plasma display panel uniform. In the writing and discharging process 2, a second pulse of a predetermined voltage Vset is simultaneously applied to the first electrode and the second electrode, and the address electrode is maintained at the reference voltage V ₀ . Therefore, in the writing discharge process 2, discharge occurs simultaneously between the first electrode and the address electrode, and between the second electrode and the address electrode. The voltage Vset of the second pulse is set to a positive voltage greater than the voltage Ve1 of the first pulse, and is set to a predetermined voltage at which a writing discharge can occur in each discharge cell formed in the plasma display panel. . In addition, the application time of the second pulse is relatively longer than the first pulse. In the lighting discharge process (2), discharge occurs simultaneously between the first electrode and the address electrode, and between the second electrode and the address electrode. As shown in FIG. 7B, a negative wall charge is applied to the first electrode and the second electrode. Are accumulated, and positive charges are accumulated on the address electrode. On the other hand, since the discharge voltage between the first electrode and the address electrode and between the second electrode and the address electrode is lower than the discharge start voltage between the first electrode and the address electrode in the conventional surface discharge method, discharge occurs at a lower voltage. do.

The second erase discharge process 3 is a process of erasing part of wall charges formed on the first electrode and the second electrode. In the second erase discharge process 3, a third pulse of a predetermined voltage Ve2 is simultaneously applied to the first electrode and the second electrode, and the address electrode is maintained at a reference voltage state. The voltage Ve2 of the third pulse is set to a negative voltage whose absolute value is smaller than the voltage Vset of the second pulse, and the application time of the third pulse is shorter than that of the second pulse. In the second erasing discharge process (3), a weak erase discharge occurs simultaneously between the first electrode and the address electrode and between the second electrode and the address electrode. As shown in FIG. 7C, the first electrode and the second electrode Part of the negative wall charges accumulated on the substrate and part of the negative wall charges accumulated on the address electrode are erased.

The address discharge period (II) specifies a discharge cell through which sustain discharge is performed by adjusting wall charges accumulated on the first electrode, the second electrode, and the address electrode. In the address discharge period II, a scan pulse having a predetermined voltage Vsc having a sign opposite to the voltage Vset of the second pulse is applied to the first electrode, and at the same time, a sign opposite to the scan pulse is applied to the address electrode. That is, an address pulse of a predetermined voltage Va having the same sign as the voltage Vset of the second pulse is applied. The second electrode maintains the bias state by applying a bias voltage Vb having the same sign as the address pulse. The voltage Vsc of the scan pulse has a smaller absolute value than the voltage Vset of the second pulse and has a smaller absolute value than the voltage Ve2 of the third pulse. Further, the bias voltage Vb is set larger than the voltage Vsc of the scan pulse. In the address discharge period (II), a weak discharge occurs between the first electrode and the address electrode, and between the first electrode and the second electrode. As shown in FIG. 7D, a positive wall is formed on the first electrode and the address electrode. Charges accumulate and negative wall charges accumulate on the second electrode.

The sustain discharge period III is a period for displaying an input image. In the sustain discharge period III, a sustain pulse of a predetermined voltage Vs is applied to the first electrode or the second electrode, and the first electrode or the second electrode and the address electrode to which the sustain pulse is not applied have a reference voltage state. Will be maintained. The voltage Vs of the sustain pulse is set to a voltage having a positive sign which is the same as the voltage Vset of the second pulse. In the sustain discharge period (III), a sustain pulse is preferably applied to the first electrode first, and then a sustain discharge proceeds. As shown in FIG. 7E, negative wall charges are accumulated on the first electrode, and a second discharge occurs. Positive wall charges build up on the electrodes. Next, a sustain pulse is applied to the second electrode to sustain discharge. As shown in FIG. 7F, positive wall charges are accumulated on the first electrode and negative wall charges are accumulated on the second electrode.

Meanwhile, in the driving waveform diagram according to the embodiment of the present invention, the plasma display panel can be driven even if the pulses applied to the first electrode and the second electrode are changed according to the circuit configuration. In addition, the driving waveform diagram enables the plasma display panel to be driven even if the signs of the pulses applied to the first electrode, the second electrode and the address electrode are changed.

Next, a method of driving a plasma display panel according to another embodiment of the present invention will be described. 8A illustrates a driving waveform diagram according to a method of driving a plasma display panel according to an exemplary embodiment of the present invention, and FIG. 8B illustrates a wall charge distribution diagram in a second erase discharge process. The driving waveform diagram according to another embodiment of the present invention is the same as the driving waveform diagram according to the embodiment of FIG. 6 except for the second erase discharge process, and thus, detailed description of the same portion will be omitted.

Referring to FIG. 8A, a driving waveform diagram of a method of driving a plasma display panel according to another embodiment of the present invention includes a reset discharge period Ia, an address discharge period II, and a sustain discharge period III.

The reset discharge cycle Ia further includes a first erase discharge process 1, a writing discharge process 2, and a second erase discharge process 3a.

The second erase discharge process 3a is a process of erasing a part of the wall charges formed on the first electrode and the second electrode. In the second erase discharge process 3a, a third pulse of a predetermined voltage Ve2 is simultaneously applied to the second electrode, and the first electrode and the address electrode are maintained at a reference voltage state. The voltage Ve2 of the third pulse is set to a negative voltage whose absolute value is smaller than the voltage Vset of the second pulse, and the application time of the third pulse is shorter than that of the second pulse. In the second erase discharge process 3a, a weak erase discharge occurs simultaneously between the second electrode and the address electrode. As shown in FIG. 8B, a part of the negative wall charge and the address electrode accumulated on the second electrode are shown. Part of the positive wall charges accumulated on the wall is erased.

Next, a method of driving a plasma display panel according to another embodiment of the present invention will be described. 9 illustrates a driving waveform diagram according to a method of driving a plasma display panel according to another embodiment of the present invention. The driving waveform diagram of the driving method according to another exemplary embodiment of the present invention is identical to the driving waveform diagram according to the exemplary embodiment of FIG. 6 except for the reset discharge period, and thus, detailed descriptions of the same components will be omitted.

Referring to FIG. 9, a driving waveform diagram of a method for driving a plasma display panel according to an embodiment of the present invention is shown in FIG. 9, which is a subfield including a reset discharge period Ib, an address discharge period II, and a sustain discharge period III. Is repeated.

The reset discharge cycle Ib further includes a first erase discharge process 1b, a writing discharge process 2b, and a second erase discharge process 3b.

The first erasing discharge process 1b gradually increases from the reference voltage V0 to a predetermined voltage Ve1_b, and applies a first waveform pulse of 1_b falling back to the reference voltage V0 to the second electrode. . At this time, the first electrode and the address electrode maintain the reference voltage (V0) state. The voltage Ve1_b of the first_b pulse is set to a value substantially equal to the voltage Vs of the sustain pulse. When the first_b pulse is applied to the second electrode in the first erase discharge process 1b, the wall charges of the first electrode and the second electrode are erased.

The writing discharge process 2b rises from the reference voltage V0 to the first voltage V1_b, gradually increases from the first voltage V1_b to the second voltage V2_b, and falls to the reference voltage V ₀ . The second_b1 pulse of the ramp waveform is applied to the first electrode. In addition, the writing and discharging process 2b increases from the reference voltage V0 to the first voltage V1_b, gradually increases from the first voltage V1_b to the second voltage V2_b, and the second voltage V2_b. Is applied to the second electrode of the second waveform of the ramp waveform falling to the third voltage (V3_b) at the same time. The first voltage V1_b is set to a positive voltage and is set to approximately the same value as the voltage Vs of the sustain pulse. In addition, the second voltage V2_b of the second b_1 pulse is set to a positive voltage greater than the voltage Ve1_b of the first pulse or the voltage Vs of the sustain pulse, and is generally used in each discharge cell formed in the plasma display panel. It is set to a predetermined voltage at which writing discharge can occur. The third voltage V3_b is set to a negative voltage having an absolute value smaller than that of the second voltage V2_b and having the opposite sign. At this time, the address electrode is maintained at the reference voltage (V0) state. Accordingly, in the writing and discharging process 2b, since discharge occurs simultaneously between the first electrode and the address electrode, between the second electrode and the address electrode, negative wall charges are accumulated on the first electrode and the second electrode, and the address electrode Positive charges accumulate in the.

The second erase discharge process 3b gradually decreases from the third voltage V3_b to the fourth voltage V4_b, and ramps the third waveform pulse of the ramp waveform from the fourth voltage V4_b to the reference voltage V0. Is applied to the second electrode. In this case, the first electrode and the address electrode maintain a reference voltage state. The fourth voltage V4_b of the third_b pulse is set to a negative voltage having an absolute value smaller than the second voltage V2_b of the second_b1 pulse. In the second erase discharge process 3b, a weak erase discharge occurs simultaneously between the first electrode and the address electrode and between the second electrode and the address electrode, and the negative wall charges accumulated on the first electrode and the second electrode are generated. Part of and part of the positive wall charge accumulated on the address electrode are erased.

Meanwhile, in the driving waveform diagram according to another embodiment of the present invention, the plasma display panel can be driven even if the pulses applied to the first electrode and the second electrode are changed according to the configuration of the circuit. In addition, the driving waveform diagram enables the plasma display panel to be driven even if the signs of the pulses applied to the first electrode, the second electrode and the address electrode are changed.

Next, a method of driving a plasma display panel according to another embodiment of the present invention will be described. 10 is a driving waveform diagram according to a method of driving a plasma display panel according to another embodiment of the present invention. The driving waveform diagram of the driving method according to another exemplary embodiment of the present invention is identical to the driving waveform diagram according to the exemplary embodiment of FIG. 6 except for the reset discharge period, and thus, detailed descriptions of the same components will be omitted.

Referring to FIG. 10, a driving waveform diagram of a method of driving a plasma display panel according to an embodiment of the present invention is shown in FIG. 10, which is a subfield including a reset discharge period Ic, an address discharge period II, and a sustain discharge period III. Is repeated.

The reset discharge cycle Ic further includes a first erase discharge process 1c, a writing discharge process 2c, and a second erase discharge process 3c.

The first erasing discharge process 1c gradually increases from the reference voltage V0 to a predetermined voltage Ve1_c, and applies a first pulse of a ramp waveform, which falls back to the reference voltage V0, to the second electrode. . At this time, the first electrode and the address electrode maintain the reference voltage (V0) state. The voltage Ve1_c of the first pulse is set to a value substantially equal to the voltage Vs of the sustain pulse. When the first_c pulse is applied to the second electrode in the first erase discharge process 1c, the wall charges accumulated in the sustain discharge process on the first electrode and the second electrode are erased.

The writing and discharging process 2c increases the second_c1 pulse of the ramp waveform that rises from the reference voltage V0 to the first voltage V1_c and gradually increases from the first voltage V1_c to the second voltage V2_c. It is applied to one electrode. In addition, the writing and discharging process 2c increases from the reference voltage V0 to the first voltage V1_c and gradually increases from the first voltage V1_c to the second voltage V2_c. Is simultaneously applied to the second electrode. In this case, the second_c2 pulse is preferably set to a ramp waveform that is approximately the same as the second_c1 pulse. The first voltage V1_c is set to a positive voltage, and is set to approximately the same value as the voltage Vs of the sustain pulse. In addition, the second voltage V2_c is set to a positive voltage greater than the first voltage V1_c or the voltage Vs of the sustain pulse, and a writing discharge may occur in each discharge cell formed in the plasma display panel. It is set to a predetermined voltage. At this time, the address electrode is maintained at the reference voltage (V0) state. Therefore, in the writing discharge process 2c, since discharge occurs simultaneously between the first electrode and the address electrode, between the second electrode and the address electrode, negative wall charges are accumulated on the first electrode and the second electrode, and the address electrode Positive charges accumulate in the.

The second erase discharge process 3c gradually decreases from the second voltage V2_c to the third voltage V3_c1, and ramps up to the reference voltage V0 from the third voltage V3_c1. Is applied to the first electrode. In addition, the second erasing discharge process 3c gradually decreases from the second voltage V2_c to the third voltage V3_c2, and ramp-up of the ramp waveform rising from the third voltage V3_c2 to the reference voltage V0. 3_c2 pulse is applied to the second electrode. At this time, the address electrode maintains a reference voltage state. The third voltage V3_c1 of the third_c1 pulse is set to a negative voltage having an absolute value smaller than the second voltage V2_c of the second_c1 pulse, and preferably a negative voltage smaller than the first voltage V1_c of the second_c1 pulse. It is set to the voltage of. The third voltage V3_c2 of the third_c2 pulse is set to a negative voltage whose absolute value is smaller than the second voltage V2_c of the second_c2 pulse, and is a negative voltage greater than the first voltage V1_c of the second_c1 pulse. Is set. In addition, the third voltage V3_c1 of the third_c1 pulse is set to a negative voltage having an absolute value smaller than the third voltage V3_c2 of the third_c2 pulse. Therefore, the slope of the third_c1 pulse is smaller than the slope of the third_c2 pulse. In the second erasing discharge process 3c, a weak erase discharge is simultaneously generated between the first electrode and the address electrode and between the second electrode and the address electrode, and the negative wall charges accumulated on the first electrode and the second electrode are simultaneously generated. Part of and part of the positive wall charge accumulated on the address electrode are erased. In addition, since the third voltage V3_c1 applied to the first electrode is set to be smaller than the third voltage V3_c2 applied to the second electrode, the degree to which the charge is erased in the first electrode is relatively small. . Therefore, in the address discharge period II, an address discharge is generated stably between the first electrode and the address electrode.

Meanwhile, in the driving waveform diagram according to another embodiment of the present invention, the plasma display panel can be driven even if the pulses applied to the first electrode and the second electrode are changed according to the configuration of the circuit. In addition, the driving waveform diagram enables the plasma display panel to be driven even if the signs of the pulses applied to the first electrode, the second electrode and the address electrode are changed.

As described above, the present invention is not limited to the specific preferred embodiments described above, and any person having ordinary skill in the art to which the present invention pertains without departing from the gist of the present invention claimed in the claims. Various modifications are possible, of course, and such changes are within the scope of the claims.

According to a driving method of a plasma display panel according to the present invention, a reset discharge pulse is applied to a scan electrode and a sustain electrode in a plasma display panel having an opposite discharge electrode to reset between the scan electrode and the address electrode and between the sustain electrode and the address electrode. By allowing the discharge to proceed, there is an effect that the efficient reset discharge can proceed to a lower voltage.

Claims (29)

A first electrode and a second electrode formed to face each other between the opposing front substrate and the rear substrate, a partition wall formed between the first electrode and the second electrode and the rear substrate, and a first electrode on the lower surface of the front substrate; A plasma display panel including an address electrode disposed to intersect a second electrode, and a phosphor layer formed on an area including an upper surface of the rear substrate and side surfaces of the barrier ribs includes a reset discharge period, an address discharge period, and a sustain discharge period. In a driving method of a plasma display panel driven by a driving waveform, The reset discharge cycle is a writing discharge process in which a second pulse of a predetermined voltage (Vset) is simultaneously applied to the first electrode and the second electrode, and a discharge occurs between the first electrode and the address electrode and between the second electrode and the address electrode. Include, The address discharge period applies a scan pulse of a predetermined voltage Vsc having a sign opposite to the voltage applied to the reset discharge period to the first electrode, and simultaneously applies a sign opposite to the first electrode to the address electrode. And applying an address pulse having a predetermined voltage Va, wherein the second electrode is applied to maintain a bias voltage Vb having the same sign as the voltage of the address pulse. The method of claim 1, The reset discharge period may further include a second erase discharge process of applying a third pulse of a predetermined voltage Ve2 having a sign opposite to the voltage Vset of the second pulse to the second electrode after the writing discharge process. A method of driving a plasma display panel. The method of claim 2, The second erasing and discharging process is a method of driving a plasma display panel, characterized in that to simultaneously apply a third pulse applied to the second electrode to the first electrode. The method of claim 2 or 3, The reset discharge period may further include a first erase discharge process of applying a first pulse of a predetermined voltage Ve1 having the same sign as the voltage Vset of the second pulse to the second electrode before the writing discharge process. A method of driving a plasma display panel. The method according to claim 2 or 3, And the voltage Vset of the second pulse is set to have a positive voltage, and the voltage Ve2 of the third pulse is set to have a negative voltage. The method of claim 5, The voltage Vset of the second pulse has a voltage higher than the voltage Ve2 of the third pulse and is applied for a longer time than the third pulse. The method of claim 4, wherein And the voltage Ve1 of the first pulse is set to a voltage smaller than the voltage Vset of the second pulse. The method of claim 1, And the voltage Vsc of the scan pulse of the address discharge period is set to have a negative voltage, and the voltage Va of the address pulse is set to have a positive voltage. The method of claim 8, And the second electrode is maintained at a bias voltage (Vb) higher than the voltage (Va) of the address pulse in the address discharge period. The method of claim 5, The sustain discharge cycle is characterized in that the sustain pulse of a predetermined voltage (Vs) is applied to the first electrode and the second electrode alternately. The method of claim 10, The sustain discharge cycle is a driving method of the plasma display panel, characterized in that the sustain pulse is first applied to the first electrode. A first electrode and a second electrode formed to face each other between the opposing front substrate and the rear substrate, a partition wall formed between the first electrode and the second electrode and the rear substrate, and a first electrode on the lower surface of the front substrate; A plasma display panel including an address electrode disposed to intersect a second electrode, and a phosphor layer formed on an area including an upper surface of the rear substrate and side surfaces of the barrier ribs includes a reset discharge period, an address discharge period, and a sustain discharge period. In a driving method of a plasma display panel driven by a driving waveform, The reset discharge cycle is a writing discharge process in which discharge is generated between the first electrode and the address electrode and between the second electrode and the address electrode by applying the second waveform pulses of the second wave and the second wave of the ramp waveform to the first electrode and the second electrode, respectively. Including; The address discharge period applies a sustain pulse of a predetermined voltage (Vs) having a sign opposite to the voltage applied to the writing discharge process to the first electrode, and simultaneously applies a sign opposite to the first electrode to the address electrode. And applying an address pulse having a predetermined voltage (Va), wherein the second electrode is maintained at a bias voltage (Vb) having the same sign as the address electrode. The method of claim 12, The reset discharge period may further include a second erase discharge process of applying a third pulse of a predetermined ramp waveform having a sign opposite to that of the ramp waveform applied to the writing discharge process after the writing discharge process. A method of driving a plasma display panel. The method of claim 13, The reset discharge cycle may further include a first erasing discharge process of applying a first pulse of a ramp waveform having the same sign as the ramp waveform applied to the writing discharge process to the second electrode before the writing discharge process. How to drive the display panel. The method according to claim 13 or 14, The second_b1 pulse rises from the reference voltage V0 to the first voltage V1_b, gradually increases from the first voltage V1_b to the second voltage V2_b, and from the second voltage V2_b to the reference voltage Is set to descend to V0), The second_b2 pulse rises from the reference voltage V0 to the first voltage V1_b, and gradually increases from the first voltage V1_b to the second voltage V2_b, and from the second voltage V2_b to the second voltage. And a third voltage (V3_b) whose sign is opposite to the voltage (V2_b). The method of claim 15, The third_b pulse is gradually reduced from the third voltage (V3_b) to the fourth voltage (V4_b), and is set to rise from the fourth voltage (V4_b) to the reference voltage (V0). Driving method. The method of claim 16, And the first voltage (V1_b) is set to the same value as the voltage (Vs) of the sustain pulse. The method of claim 16, And the second voltage (V2_b) is set to a value greater than the voltage (Vs) of the sustain pulse. The method of claim 16, And the third voltage (V3_b) is set to a negative voltage whose absolute value is smaller than the second voltage (V2_b) and whose sign is opposite. The method of claim 19, And the absolute value of the third voltage (V3_b) is set to approximately the same value as the first voltage (V1_b). The method of claim 16, And the fourth voltage (V4_b) is set to have an absolute value smaller than the second voltage (V2_b). The method of claim 14, And the voltage Ve_b of the first_b pulse is set to a voltage substantially equal to the voltage Vs of the sustain pulse. A first electrode and a second electrode formed to face each other between the opposing front substrate and the rear substrate, a partition wall formed between the first electrode and the second electrode and the rear substrate, and a first electrode on the lower surface of the front substrate; A plasma display panel including an address electrode disposed to intersect a second electrode, and a phosphor layer formed on an area including an upper surface of the rear substrate and side surfaces of the barrier ribs includes a reset discharge period, an address discharge period, and a sustain discharge period. In a driving method of a plasma display panel driven by a driving waveform, The reset discharge period is applied to the second and second electrodes of the ramp waveform gradually increasing to the first electrode and the second electrode, respectively, the discharge between the first electrode and the address electrode and between the second electrode and the address electrode A writing and discharging process, and a second erasing and discharging process of applying 3_c1 pulses and 3_c2 pulses of ramp waveforms gradually decreasing to the first electrode and the second electrode, respectively. The address discharge period applies a scan pulse of a predetermined voltage Vsc having the same sign as the voltage of the third_c1 pulse applied to the writing discharge process to the first electrode, and simultaneously with the first electrode to the address electrode. An address pulse having a predetermined voltage Va having an opposite sign is applied, and the second electrode is maintained at a bias voltage Vb having the same sign as the address electrode. The method of claim 23, wherein The reset discharge cycle may further include a first erase discharge process of applying a first waveform of the ramp waveform having the same sign as the voltage of the second_c2 pulse to the second electrode before the writing discharge process. Driving method. The method of claim 23, wherein The second_c1 pulse and the second_c2 pulse gradually increase from the first voltage V1_c higher than the reference voltage to the second voltage V2_c, and are applied to maintain the second voltage V2_c for a predetermined time. How to drive the display panel. The method of claim 23, wherein The 3-c1 pulse is gradually reduced from the second voltage V2_c to the third voltage V3_c1 which is a negative voltage and is applied to rise to a reference voltage, and the third_c2 pulse is negative from the second voltage V2_c. And a voltage is gradually reduced to a third voltage (V3_c2) which is a voltage and is applied to rise to a reference voltage. The method of claim 26, The third voltage V3_c1 of the third-c1 pulse is set to a voltage having an absolute value smaller than the third voltage V3_c2 of the third_c2 pulse, and the slope of the third_c1 pulse is set smaller than the slope of the third_c2 pulse. A method of driving a plasma display panel. The method of claim 26, The third voltage V3_c1 of the third-c1 pulse and the third voltage V3_c2 of the third_c2 pulse are set to a voltage having an absolute value smaller than the second voltage V2_c of the second_c1 pulse. How to drive the display panel. The method according to any one of claims 1 to 12 or 23, The first electrode is formed of a scan electrode, the second electrode is a driving method of the plasma display panel, characterized in that formed.

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