KR100692680B1 - Timing controller of lcd - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing controller of a liquid crystal display that generates internal clocks having a phase difference from each other and outputs signals in synchronization with an internal clock in groups so as to dissipate power. R, G, and B A data control unit configured to input / latch data; a timing controller configured to output a driving control signal using a clock signal, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a data enable signal DE; n A sub clock signal generator including n delay buffer means and generating n clocks CLK_1, CLK_2,... CLK_n each having a predetermined magnitude difference based on the main clock CLK; N data processing units for processing and outputting the latched R, G, and B data; grouping output data of each data processing unit and synchronizing to clocks having a phase difference from each other N output data latches configured to output the latches; and an output buffer means for outputting gate control signals and data control signals under the control of the timing controller.

LCD, Timing Controller, ASIC

Description

Timing controller of liquid crystal display device {TIMING CONTROLLER OF LCD}

1 is a configuration diagram of a controller of a conventional liquid crystal display device

2 is an operation clock timing diagram of an output port block of the related art.

3 is a block diagram of a controller of a liquid crystal display according to the present invention.

4 is a detailed configuration diagram of the output phase adjustment device according to the present invention

5 is an operation clock timing diagram of an output port block according to the present invention.

Explanation of symbols for the main parts of the drawings

31. First input buffer 32. Input data latch section

33a.33b.33c. First, second, and third data processing units 34. Second input buffer

35. Timing Controls

36a.36b.36c. 1, 2, 3 output data latch unit

37. First Output Buffer 38. Second Output Buffer

39. Sub clock signal generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a timing controller of a liquid crystal display that generates internal clocks having phase differences from each other and outputs signals in synchronism with an internal clock in groups so as to dissipate power consumption. It is about.

Recently, flat panel display devices have been developed to have high frequency and high resolution in order to realize a more satisfactory screen of a product.

As a flat panel display device, a liquid crystal display device may be described as a typical case, and a liquid crystal display device has limitations in implementation of high resolution due to EMI problem, noise problem through transmission medium, and limitation of data transmission number in SXGA class or higher module. There is this.

In general, a liquid crystal display device transmits data in a TTL signal having a high frequency. In such an environment, an EMI problem occurs because an image signal is affected by the TTL signal and a voltage level is changed at a corresponding frequency.

In addition, the method of transmitting data or clock signals by the TTL signal described above requires a large number of transmission lines, and thus requires a large number of cables and connectors of the liquid crystal display.

In such an environment, data or clock signals are directly or indirectly affected by noise. When normal data and clock signals are affected by noise, a problem arises in that an abnormal screen is formed.

In addition, the number of data transmission bits supported by a graphics controller that is commonly used to achieve full color high resolution is limited. In the following, there is an attempt to introduce 'LVDS' technology.

LVDS technology was defined in IEEE 'IEEE P1596.3' in 1996 by the IEEE, and LVDS technology is designed to realize data transmission at low voltage, and has a high transmission speed.

Hereinafter, a controller of a liquid crystal display according to the related art will be described with reference to the accompanying drawings.

1 is a configuration diagram of a controller of a liquid crystal display of the prior art, and FIG. 2 is an operation clock timing diagram of an output port block of the prior art.

The controller of the liquid crystal display is configured with a graphics card inside the computer main body which is a signal source, and the graphics card applies R, G, B signals and control signals, which are TTL level color signals, to the first and second LVDS chips.

Due to the physical characteristics of the liquid crystal, each of the R, G, and B signals applied to have different polarities are divided and applied to the first and second LVDS chips in order to express colors by line inversion or dot inversion.

In addition, control signals such as a horizontal synchronization signal, a vertical synchronization signal, and a data enable signal are applied to the second LVDS chip.

Each signal applied to the first and second LVDS chips is converted into LVDS signals of a predetermined number of channels through a timing controller and transmitted to a source / gate driver of a liquid crystal display configured for display.

Two 85MHz LVDS chips are used to implement LCD modules with SXGA resolution because the main clock is 108MHz.

At this time, the data from LVDS receiver is odd or even 18 or 24, respectively, and it comes out through 4mA buffer.

Along with this data, control signals (DE, CLOCK, horizontal sync signal: HSYNC, vertical sync signal: VSYNC) are received from the timing controller 1 to generate the necessary sync signal, and the data is latchgn back out through the 4mA buffer.

Referring to a detailed configuration of the timing controller and the LVDS chip, as shown in FIG. 1, a first input buffer 1 for receiving R, G, and B data, and R, G, and B data of the first input buffer 1 may be used. An input data latch unit 2 for latching and outputting a clock signal, a clock signal, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a data enable signal DE to be output to the timing controller 5. A data processor 3 that processes and outputs data by the second input buffer 4, the clock signal CLK of the second input buffer 4, and the clock signal of the second input buffer 4. An output data latch unit 6 for latching data output from the data processor 3 by CLK, and a first output buffer 7 for buffering and outputting latch output data of the output data latch unit 6. And outputting gate control signals and data control signals under the control of the timing controller 5. It consists of a second output buffer (8).

Where (a) is an output port block.

However, the timing controller of the liquid crystal display of the prior art has the following problems.

Conventionally, the LCD timing controller operates in synchronization with a clock to which all signals and output signals inside the ASIC are input, as shown in FIG. 2.

At this time, when the pulses of the output pins of the LCD timing controller simultaneously transition to rising or falling pulses, heat is generated in the chip as the output buffers operate simultaneously.

This may cause a malfunction of the liquid crystal display.

In addition, as the power consumption increases momentarily, a potential change occurs at the power supply voltage pin, and the changed value of the power / groud pins affects the output signals, causing distortion of the signals.

In this case, a malfunction occurs in the operation of the IC that receives the output signals as an input. In addition, EMI characteristics are degraded by the distorted output signals.

The present invention is to solve the problem of the controller of the liquid crystal display of the prior art, the input clock is delayed by using a buffer or a gate in the chip to make an internal clock having n phase difference and then output signals It is an object of the present invention to provide a timing controller of a liquid crystal display device which divides into n groups and outputs them in synchronization with a clock having a phase difference, so as to dissipate power and improve chip heat generation and EMI.

The timing controller of the liquid crystal display according to the present invention for achieving the above object comprises: data input means for inputting / latching R, G, B data; A timing controller outputting a driving control signal using a clock signal, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a data enable signal DE; a sub clock signal generator including n delay buffer means and generating n sub clock signals CLK_1, CLK_2, ... CLK_n having a phase difference of a predetermined magnitude based on the clock signal; N data processing units for processing and outputting R, G, and B data output from the data input means in synchronization with the clock signal; N output data latch units for grouping the output data of the respective data processing units and latching them in synchronization with the sub-clock signals, respectively; And an output buffer means for buffering and outputting the output data of the output data latch unit.

Hereinafter, a timing controller and an output phase adjusting device of a liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a configuration diagram of the controller of the liquid crystal display device according to the present invention, and FIG. 4 is a detailed configuration diagram of the output phase adjustment device according to the present invention.

5 is an operation clock timing diagram of an output port block according to the present invention.

According to the present invention, a clock having a plurality of phase differences is made, and then a signal outputted using the clock has a phase difference so as to dissipate excessive power consumption caused by the output signals simultaneously shifting.

The present invention preferentially applies to the ASIC for LCD timing control, but is not limited thereto, and it can be applied to all ASIC-related products.

3, the first input buffer 31 for receiving the R, G, and B data and the input data latch unit for latching and outputting the R, G, and B data of the first input buffer 31 are illustrated in FIG. 32 and a second input buffer 34 which receives a clock signal, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a data enable signal DE, and outputs them to the timing controller 35. And first, second and third data processing units 33a, 33b and 33c for processing and outputting R, G and B data by the main clock signal CLK of the second input buffer 34, respectively. A first output data latch section 36a for latching the R data output from the first data processing section 33a by the data processor 33, the main clock signal CLK of the second input buffer 34, A second output data latch unit 36b for latching G data output from the second data processing unit 33b by a first sub clock signal having a phase difference from the main clock signal; And a third output data latch unit 36c for latching B data output from the third data processing unit 33c by a second sub clock signal having a phase difference from the first sub clock signal. A first output buffer 37 which buffers and outputs the latch output data of the output data latch units 36a, 36b and 36c, and gate control signals and data control signals under the control of the timing controller 35; And a sub clock signal generator 39 for delaying the main clock signal and outputting sub clock signals having a phase difference, respectively.

Of course, the sub-clock signal generator 30 may generate up to n sub-clock signals as necessary. Where (b) is an output port block.

In the present invention, the clock input as shown in FIG. 4 is delayed using a buffer or a gate in the chip to make an internal clock having n phase differences, and then the output signals are divided into n groups to synchronize with a clock having a phase difference. Output dissipates power consumption, improving chip heat generation and EMI.

The block diagram inside the LCD timing controller in the case of applying the contents of the present invention as shown in FIG.

Using two delay buffers, three incoming clocks with different phases are created, and the R / G / B data blocks are divided into three R / G / B data groups to synchronize three different clocks with time differences. Output R / G / B data.

Referring to the operation waveform of the output port block (output port block) in FIG. 5, as the output data are output with a time difference, it is possible to improve a problem caused by instantaneous consumption of current.

Such a timing controller and an output phase adjusting device of the liquid crystal display according to the present invention have the following effects.

First, it suppresses the simultaneous transition of the ASIC's output buffers and outputs with time difference, thereby suppressing heat generation due to excessive current change.

Second, the timing margin may be improved by stabilizing the output signal by distributing power consumption to solve the distortion of the output signal due to the instability of the power supply.

Third, EMI characteristics can be improved by suppressing noise components introduced into an output signal.

Claims (3)

Data input means for inputting / latching R, G, and B data; A timing controller outputting a driving control signal using a clock signal, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a data enable signal DE; a sub clock signal generator including n delay buffer means and generating n sub clock signals CLK_1, CLK_2, ... CLK_n having a phase difference of a predetermined magnitude based on the clock signal; N data processing units for processing and outputting R, G, and B data output from the data input means in synchronization with the clock signal; N output data latch units for grouping the output data of the respective data processing units and latching them in synchronization with the sub-clock signals, respectively; And an output buffer means for buffering and outputting the output data of the output data latch unit. The timing controller of claim 1, wherein the data processing unit comprises first, second, and third data processing units which process R, G, and B data, respectively. 2. The output data latching unit according to claim 1, wherein the output data latch unit is grouped into R data, G data, and B data, respectively, and synchronized with the first, second, and third clock signals CLK_1, CLK_2, and CLK_3 each having a predetermined phase difference. And a first, second, and third output data latching unit for outputting the timing controller.

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