KR100559222B1 - Controler of lcd - Google Patents

Abstract

The present invention relates to a controller of a liquid crystal display device capable of reducing hardware and power consumption by outputting a buffer output of an LVDS receiver to a source driver IC without passing through a timing controller. LVDS output buffer for receiving and outputting; R, C blocks connected to the LVDS output buffer and configured to output each R, G, B data directly to the source driver IC; Necessary for driving the source driver IC An input buffer configured to input control signals for generating synchronization signals; a timing controller configured to control driving signals of the input buffer and output driving control signals; buffering driving control signals of the timing controller to output gate control signals and data control signals LCD with inputs on LVDS 2-channels To drive the data driver IC using the output signal and the data output signal of the LVDS output buffer directly from the timing controller.

LVDS, ASIC, LCD

Description

Controller of liquid crystal display {CONTROLER OF LCD}

1 is a block diagram of a controller of a general liquid crystal display device

2 is a block diagram of a timing controller of the prior art

3 is a block diagram illustrating a controller of the liquid crystal display according to the present invention.

4 is a detailed configuration diagram of a controller of a liquid crystal display according to the present invention.

Explanation of symbols for the main parts of the drawings

41.LVDS Output Buffer 42.Input Buffer

43. Timing control section 44. Output buffer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a controller of a liquid crystal display device capable of directly outputting a buffer output of an LVDS receiver to a source driver IC without passing through a timing controller.

Recently, flat panel display devices have been developed to have high frequency and high resolution in order to realize a more satisfactory screen of a product.

As a flat panel display device, a liquid crystal display device may be described as a typical case, and a liquid crystal display device has limitations in implementation of high resolution due to EMI problem, noise problem through transmission medium, and limitation of data transmission number in SXGA class or higher module. There is this.

In general, a liquid crystal display device transmits data in a TTL signal having a high frequency. In such an environment, an EMI problem occurs because an image signal is affected by the TTL signal and a voltage level is changed at a corresponding frequency.

In addition, the method of transmitting data or clock signals by the TTL signal described above requires a large number of transmission lines, and thus requires a large number of cables and connectors of the liquid crystal display.

In such an environment, data or clock signals are directly or indirectly affected by noise. When normal data and clock signals are affected by noise, a problem arises in that an abnormal screen is formed.

In addition, the number of data transmission bits supported by a graphics controller that is commonly used to realize full color high resolution is limited. To solve this problem, low voltage differential signaling (hereinafter referred to as low voltage differential signaling) on an interface between a computer main body and a liquid crystal module is required. There is an attempt to introduce "LVDS" technology.

LVDS technology was defined in IEEE 'IEEE P1596.3' in 1996 by the IEEE, and LVDS technology is designed to realize data transmission at low voltage, and has a high transmission speed.

Hereinafter, a controller of a liquid crystal display of the prior art will be described with reference to the accompanying drawings.

1 is a block diagram of a controller of a general liquid crystal display, and FIG. 2 is a block diagram of a timing controller of the related art.

In the controller of the liquid crystal display, as shown in Fig. 1, a graphics card is configured inside a computer main body, which is a signal source, and the graphics card is a first and second LVDS chips 2 and 3, which is a color signal of TTL level R, Apply G and B signals and control signals.

Due to the physical characteristics of the liquid crystal, each of the R, G, and B signals applied to have different polarities to distinguish colors by line inversion or dot inversion is divided and divided into first and second LVDS chips 2 and 3, respectively. Is applied.

In addition, control signals such as a horizontal synchronization signal, a vertical synchronization signal, and a data enable signal are applied to the second LVDS chip 3.

The signals applied to the first and second LVDS chips 2 and 3 are converted into LVDS signals of a predetermined number of channels through the timing controller 1 and transmitted to the source / gate drivers of the liquid crystal display configured for display. do.

Two 85MHz LVDS chips are used to implement LCD modules with SXGA resolution because the main clock is 108MHz.

At this time, the data from LVDS receiver is odd or even 18 or 24, respectively, and it comes out through 4mA buffer.

Along with this data, control signals (DE, CLOCK, horizontal sync signal: HSYNC, vertical sync signal: VSYNC) are received from the timing controller 1 to generate the necessary sync signal, and the data is latchgn back out through the 4mA buffer.

Referring to a detailed configuration of the timing controller and the LVDS chip, as shown in FIG. 2, the first input buffer 21 for receiving the R, G, and B data, and the R, G, and B data of the first input buffer 21 is illustrated. The input data latch unit 22 for latch outputting the clock signal, a clock signal, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a data enable signal DE to be outputted to the timing controller 25. A data processor 23 for processing and outputting data by a second input buffer 24, a clock signal CLK of the second input buffer 24, and a clock signal of the second input buffer 24. An output data latch unit 26 for latching data output from the data processor 23 by CLK, and a first output buffer 27 for buffering and outputting latch output data of the output data latch unit 26. And gate control signals and data control signals under control of the timing controller 25. It consists of the 2nd output buffer 28 which outputs.

Where (a) is an output port block.

The controller of the liquid crystal display device of the prior art unnecessarily doubles the data through the buffer of the LVDS receiver and the timing controller.

The controller and data processor of the liquid crystal display of the prior art have the following problems.

Data is routed out through the LVDS receiver and the timing controller's buffer.                         

This increases the pin count of the timing controller, increasing the size of the IC package.

In addition, resistors (R), beads (L), and capacitors (C) are formed in the output data of the LVDS receiver and the data of the timing controller output, resulting in unnecessary hardware increase.

The present invention solves the problems of the conventional liquid crystal display device, and it is possible to output the buffer output of the LVDS receiver directly to the source driver IC without passing through the timing controller to reduce hardware and power consumption. Its purpose is to provide a controller of a liquid crystal display device.

The controller of the liquid crystal display according to the present invention for achieving the above object is an LVDS output buffer for receiving and outputting R, G, B data; connected to the LVDS output buffer to directly source the respective R, G, B data R and C blocks configured on an output line output to a driver IC; an input buffer for inputting control signals for generating synchronization signals required to drive a source driver IC; outputting driving control signals by controlling the signals of the input buffer. An output buffer configured to output gate control signals and data control signals by buffering the driving control signals of the timing controller, and outputting the LVDS output buffer from the LCD timing controller receiving the LVDS 2-channel Configured to include data driver ICs using signals and data output signals directly The features.

Hereinafter, a controller of the liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating a controller of the liquid crystal display according to the present invention, and FIG. 4 is a detailed block diagram of the controller of the liquid crystal display according to the present invention.

In the present invention, the data output through the buffer of the LVDS receiver is directly output to the source driver IC, and the timing controller 31 receives only Sync and clk signals to synchronize the signals required to drive the source driver IC ( CPH, STH, LOAD, MPOL, STV, CPV, etc.) are synchronized with the data.

That is, as shown in FIG. 3, each of the R, G, and B signals are divided and applied to the first and second LVDS chips 32 and 33, respectively, and the first and second LVDS chips 32 and 33 are respectively applied. Among the signals applied to the data signal, the data signal is directly input to the source driver IC, and a control signal (DE, CLOCK, horizontal synchronizing signal: HSYNC, vertical synchronizing signal: VSYNC) for generating the synchronization signals necessary to drive the source driver IC. Only to the source / gate driver of the liquid crystal display device via the timing controller 31.

Specifically, as shown in FIG. 4, an LVDS output buffer 41 for receiving and outputting R, G, and B data and a source driver IC connected to the LVDS output buffer 41 to directly output each of the R, G, and B data. Input the R and C blocks configured in the output line to be output to the control line, and the control signals (DE, CLOCK, HYNC, VYNNC, VSYNC) to make the synchronization signals required to drive the source driver IC. An input buffer 42, a timing controller 43 for controlling the signals of the input buffer 42 to output driving control signals, and a gate control signal by buffering the driving control signals of the timing controller 43. And an output buffer 44 for outputting data control signals.

The controller of the liquid crystal display according to the present invention sends the data from the LVSD receiver buffer directly to the source driver IC, and the timing controller receives only the synchronization signal and receives the synchronization signals CPH, STH, and the like necessary to drive the source driver IC. LOAD, MPOL, STV, CPV, etc.) are synchronized with the data.

Here, CPH is a horizontal clock signal, STH is a horizontal start signal, CPV is a vertical clock signal, and STV is a vertical start signal.

MPOL is the polarity control signal and LOAD is the load signal.

In this case, internal pulses are generated using the data enable signal DE and CLOCK, and then CPH, CPV, STH, and STV are generated.

The remaining sync data is generated using CPH. The skew difference between the data, CPH, and STH is solved by constructing a delay element by attaching R and C to each signal stage of the data or CPH & STH.

The controller of the liquid crystal display device according to the present invention has the following effects.

First, by reducing the number of input and output pins of the LCD timing controller, it is possible to reduce the size and cost of the LCD controller package.

Second, the EMI filter used between the LVDS and the LCD timing controller can be eliminated, reducing manufacturing costs and hardware burden.                     

Third, the power consumption can be reduced by reducing the output buffer doubled in LVDS and LCD timing controllers.

Claims (2)

An LVDS output buffer for receiving and outputting R, G, and B data; R, C blocks connected to the LVDS output buffer and configured to output R, G, and B data directly to a source driver IC; An input buffer for inputting control signals for producing synchronization signals necessary for driving the source driver IC; A timing controller configured to control the signals of the input buffer and output driving control signals; And an output buffer configured to buffer driving control signals of the timing controller to output gate control signals and data control signals. An LCD timing controller receiving an LVDS 2-channel input drive a data driver IC by directly using an output signal and a data output signal of an LVDS output buffer. The horizontal clock signal CPH, the horizontal start signal STH, the vertical clock signal CPV, the vertical start signal STV, and the polarity control signal MPOL required by the timing controller to drive the source driver IC. And a synchronization signal including a load signal LOAD in synchronization with data.

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