KR100678311B1 - Method of manufacturing a transistor in a semiconductor device - Google Patents
Method of manufacturing a transistor in a semiconductor device Download PDFInfo
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- KR100678311B1 KR100678311B1 KR1020010086873A KR20010086873A KR100678311B1 KR 100678311 B1 KR100678311 B1 KR 100678311B1 KR 1020010086873 A KR1020010086873 A KR 1020010086873A KR 20010086873 A KR20010086873 A KR 20010086873A KR 100678311 B1 KR100678311 B1 KR 100678311B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 50
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 32
- 238000005468 ion implantation Methods 0.000 claims description 28
- 238000010438 heat treatment Methods 0.000 claims description 14
- 230000002265 prevention Effects 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 2
- 239000013043 chemical agent Substances 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 claims 1
- 229910017052 cobalt Inorganic materials 0.000 claims 1
- 239000010941 cobalt Substances 0.000 claims 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000006731 degradation reaction Methods 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 3
- 238000005054 agglomeration Methods 0.000 description 2
- 230000002776 aggregation Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- Condensed Matter Physics & Semiconductors (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract
본 발명은 반도체 소자의 트랜지스터 제조 방법에 관한 것으로, 접합부에서 자체 저항 및 콘택 저항을 감소시키면서 게이트 전극의 면저항을 감소시키기 위하여 샐리사이드 공정을 적용할 때, 게이트 전극의 표면만 선택적으로 비정질화시킨 후에 샐리사이드 공정을 진행하므로서, 얕은 접합부의 표면에는 얇은 금속-실리사이드층이 형성되어 접합부 누설 전류 특성의 저하를 방지할 수 있고, 좁은 선폭의 게이트 전극 표면에는 두꺼운 금속-실리사이드층이 형성되어 게이트 전극의 면저항의 증가를 방지할 수 있어, 소자의 전기적 특성 및 신뢰성을 향상시킬 수 있고, 소자의 고집적화를 실현할 수 있는 반도체 소자의 트랜지스터 제조 방법에 관하여 기술된다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device, wherein when applying the salicide process to reduce the sheet resistance of the gate electrode while reducing the self resistance and the contact resistance at the junction, after only amorphous surface of the gate electrode is selectively amorphous Through the salicide process, a thin metal-silicide layer is formed on the surface of the shallow junction to prevent degradation of the junction leakage current characteristics, and a thick metal-silicide layer is formed on the gate electrode surface of the narrow line width to form a gate electrode. An increase in the sheet resistance can be prevented, the electrical characteristics and reliability of the device can be improved, and a transistor manufacturing method of a semiconductor device capable of realizing high integration of the device is described.
샐리사이드, PAI, 접합부 누설 전류, 게이트전극 면저항Salicide, PAI, Junction Leakage Current, Gate Electrode Sheet Resistance
Description
도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a transistor manufacturing method of a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11: 반도체 기판 12: 소자 분리막11: semiconductor substrate 12: device isolation film
13: 게이트 산화막 14: 게이트 전극13: gate oxide film 14: gate electrode
15: 절연막 스페이서 16: 소오스/드레인 접합부15: insulating film spacer 16: source / drain junction
17: 이온 주입 방지막 18a, 18b: 금속-실리사이드층
17: ion
본 발명은 반도체 소자의 트랜지스터 제조 방법에 관한 것으로, 특히 접합부에서 자체 저항 및 콘택 저항을 감소시키면서 게이트 전극의 면저항을 감소시키기 위하여 샐리사이드 공정을 적용할 때, 접합부 누설 전류 특성의 저하를 방지하면서 게이트 전극의 면저항의 증가를 방지할 수 있는 반도체 소자의 트랜지스터 제조 방법에 관한 것이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device, in particular, when applying a salicide process to reduce the sheet resistance of the gate electrode while reducing the self resistance and contact resistance at the junction, the gate while preventing the degradation of the junction leakage current characteristics. The present invention relates to a transistor manufacturing method of a semiconductor device capable of preventing an increase in sheet resistance of an electrode.
일반적으로, 반도체 소자가 고집적화, 소형화, 고기능화 되어 감에 따라 금속 배선과 접합부와의 사이에 콘택 저항을 낮추고, 게이트 전극의 저항을 낮추기 위한 방안이 연구되어지고 있다. 현재, 콘택 저항 및 게이트 전극의 저항을 낮추기 위한 하나의 방안으로 접합부 표면 및 게이트 전극 표면에 실리사이드층(silicide layer)을 형성하는 방법이 있는데, 이 방법은 샐리사이드(salicide) 공정에 의해 이루어진다.In general, as semiconductor devices become highly integrated, miniaturized, and highly functional, methods for reducing contact resistance between the metal wiring and the junction and lowering the resistance of the gate electrode have been studied. Currently, one method for lowering the resistance of the contact resistance and the gate electrode is a method of forming a silicide layer on the junction surface and the gate electrode surface, which is achieved by a salicide process.
샐리사이드 공정은 Ti, Co와 같은 실리사이드용 금속을 증착하는 공정과 후속 열처리 공정의 2단계로 이루어진다. 이 열처리에 의해 금속 원자와 Si 원자와의 반응으로 접합부 표면 및 게이트 전극 표면이 실리사이드화되어 금속-실리사이드층이 형성된다.The salicide process consists of two steps of depositing a metal for silicide such as Ti and Co and a subsequent heat treatment process. By this heat treatment, the junction surface and the gate electrode surface are silicided by the reaction between the metal atoms and the Si atoms to form a metal-silicide layer.
금속-실리사이드층을 형성하므로 인하여 접합부의 콘택 저항은 낮출 수 있으나, 금속-실리사이드층이 형성되는 과정 동안에 동반되는 접합부의 Si 원자 소모로 인하여 접합부의 기능이 저하되는 문제가 있다. 이러한 문제는 반도체 소자가 고집적화됨에 따라 요구되는 얕은 접합부(shallow junction)에서 더욱 심각하다. 이를 해결하기 위해서는 얕은 접합부에서의 금속-실리사이드층의 두께를 줄여야 하는데, 이 경우 게이트 전극 표면의 금속-실리사이드층도 함께 줄어들어 게이트 전극의 저항을 낮추기가 어렵다. 즉, 금속-실리사이드층의 두께를 줄여 얕은 접합부의 기능 은 향상되지만 게이트 전극의 저항을 낮출 수 없어 반도체 소자의 고집적화 실현을 어렵게 한다. 더욱이, 고집적 소자에서는 게이트 전극의 선폭이 매우 좁기 때문에 금속-실리사이드층의 두께를 줄일 경우 후속 열공정에 의하여 금속-실리사이드층에 응집 작용(agglomeration)이 일어나면서 게이트 전극의 면저항이 급격히 증가하게 된다.The contact resistance of the junction can be lowered by forming the metal-silicide layer, but there is a problem in that the function of the junction is degraded due to the consumption of Si atoms of the junction accompanying the process of forming the metal-silicide layer. This problem is more severe at shallow junctions, which are required as semiconductor devices become more integrated. To solve this problem, it is necessary to reduce the thickness of the metal-silicide layer at the shallow junction. In this case, the metal-silicide layer on the surface of the gate electrode is also reduced, making it difficult to lower the resistance of the gate electrode. In other words, by reducing the thickness of the metal-silicide layer, the function of the shallow junction is improved, but the resistance of the gate electrode cannot be lowered, making it difficult to realize high integration of the semiconductor device. Furthermore, in the highly integrated device, since the line width of the gate electrode is very narrow, when the thickness of the metal-silicide layer is reduced, the sheet resistance of the gate electrode increases rapidly due to the agglomeration of the metal-silicide layer by a subsequent thermal process.
현재, 로직 기술(logic technology) 개발에 있어서, 접합부에서 자체 저항 및 콘택 저항을 감소시키는 것도 중요하지만, 게이트 전극에서의 금속-실리사이드층의 응집 작용으로 게이트 전극의 면저항이 증가되는 것을 방지하는 것이 매우 중요하다. 게이트 전극의 면저항을 줄이기 위한 하나의 방안으로 실리사이드용 금속을 증착하기 전에 비정질화 이온 주입을 통해 게이트 전극 표면을 비정질화시키고, 이후 샐리사이드 공정을 통해 게이트 전극 표면에 균일하면서 열안정성이 높은 두꺼운 금속-실리사이드층을 형성하였다. 그러나, 접합부의 표면에도 두꺼운 금속-실리사이드층이 형성되어 누설 전류 특성이 열화되는 문제가 있다.
At present, in the development of logic technology, it is also important to reduce the self resistance and contact resistance at the junction, but it is very important to prevent the sheet resistance of the gate electrode from increasing due to the cohesion of the metal-silicide layer at the gate electrode. It is important. One method to reduce the sheet resistance of the gate electrode is to amorphous the gate electrode surface through amorphous ion implantation before depositing the metal for silicide, and then, through the salicide process, a thick and high thermal stability metal on the gate electrode surface. A silicide layer was formed. However, there is a problem that a thick metal-silicide layer is also formed on the surface of the junction to degrade leakage current characteristics.
따라서, 본 발명은 접합부에서 자체 저항 및 콘택 저항을 감소시키면서 게이트 전극의 면저항을 감소시키기 위하여 샐리사이드 공정을 적용할 때, 접합부 누설 전류 특성의 저하를 방지하면서 게이트 전극의 면저항의 증가를 방지할 수 있는 반도체 소자의 트랜지스터 제조 방법을 제공함에 그 목적이 있다.
Therefore, when the salicide process is applied to reduce the sheet resistance of the gate electrode while reducing the self resistance and the contact resistance at the junction, the present invention can prevent an increase in the sheet resistance of the gate electrode while preventing degradation of the junction leakage current characteristics. It is an object of the present invention to provide a method for manufacturing a transistor of a semiconductor device.
이러한 목적을 달성하기 위한 본 발명의 실시예에 따른 반도체 소자의 트랜지스터 제조 방법은 반도체 기판에 게이트 전극 및 LDD 구조의 소오스/드레인 접합부를 형성하는 단계; 상기 게이트 전극을 선택적으로 노출시키는 이온 주입 방지막을 형성하는 단계; 상기 이온 주입 방지막이 형성된 상태에서 비정질화 이온 주입 공정을 실시하여 상기 게이트 전극 표면을 비정질화시키는 단계; 및 상기 이온 주입 방지막을 제거시킨 후, 샐리사이드 공정을 실시하고, 이로 인하여 상기 게이트 전극 표면에는 두꺼운 금속-실리사이드층이 형성되고, 상기 소오스/드레인 접합부 표면에는 얇은 금속-실리사이드층이 형성되는 단계를 포함하여 이루어지는 것을 특징으로 한다.
According to an embodiment of the present invention, a transistor manufacturing method of a semiconductor device may include forming a source / drain junction of a gate electrode and an LDD structure on a semiconductor substrate; Forming an ion implantation prevention layer selectively exposing the gate electrode; Performing an amorphous ion implantation process in the state where the ion implantation prevention film is formed to amorphousize the gate electrode surface; And removing the ion implantation prevention layer and then performing a salicide process, whereby a thick metal-silicide layer is formed on the gate electrode surface and a thin metal-silicide layer is formed on the source / drain junction surface. It is characterized by comprising.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of devices for describing a method of manufacturing a transistor in a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 반도체 기판(11)에 소자 분리막(12)을 형성하여 액티브 영역을 정의(define)한다. 액티브 영역의 반도체 기판(11) 상에 게이트 산화막(13) 및 게이트 전극(14)을 형성한다. LDD 이온 주입 공정을 실시한 후, 게이트 전극(14)의 양 측벽에 절연막 스페이서(15)를 형성하고, 소오스/드레인 이온 주입 공정을 실시하여 게이트 전극(14) 양측의 반도체 기판(11)에 LDD 구조의 얕은 소오스/드레인 접합부(16)를 형성한다.
Referring to FIG. 1A, an
도 1b를 참조하면, 게이트 전극(14)만 선택적으로 노출되도록 이온 주입 방지막(17)을 형성한다. 이온 주입 방지막(17)이 형성된 상태에서 비정질화 이온 주입 공정을 실시하여 게이트 전극(14) 표면을 비정질화시킨다.Referring to FIG. 1B, the ion
상기에서, 이온 주입 방지막(17)은 포토레지스트를 코팅(coating)한 후 패터닝을 통하여 게이트 전극(14) 부분만 포토레지스트를 제거하여 형성된다. 비정질화 이온 주입 공정은 아르곤(Ar)을 사용하며, 1E14 atoms/cm2의 이온 주입량으로 약 20keV의 이온 주입 에너지의 조건으로 실시한다.In the above, the ion
도 1c를 참조하면, 이온 주입 방지막(17)을 제거한 후, 샐리사이드 공정을 실시하고, 이로 인하여 게이트 전극(14)의 표면에는 균일하면서 열안정성이 높은 두꺼운 금속-실리사이드층(18a)이 형성되고, 소오스/드레인 접합부(16)의 표면에는 게이트 전극(14)의 표면에 형성된 금속-실리사이드층(18a)의 두께보다 상대적으로 얇은 금속-실리사이드층(18b)이 형성된다.Referring to FIG. 1C, after the ion
상기에서, 금속-실리사이드층(18a 및 18b)은 게이트 전극(14) 및 소오스/드레인 접합부(16)를 포함한 전체 구조 상부에 실리사이드용 금속층으로 코발트(Co)를 50Å ~ 150Å의 두께로 증착한 후, 급속 열처리(RTP) 장비를 이용하여 350℃ ~ 600℃의 온도 범위에서 30초 ~ 90초간 1차 열처리 공정을 진행하고, 1차 열처리 공정 후에 미반응된 물질을 제거하기 위하여 SC-1과 SC-2 화학제로 선택적 식각 공정을 진행하고, 급속 열처리(RTP) 장비를 이용하여 700℃ ~ 850℃의 온도 범위에서 20초 ~ 40초간 2차 열처리 공정을 진행하여 형성한다. SC-1 화학제는 NH4OH, H2O2
및 DI의 혼합 용액이고, SC-2 화학제는 HCl, H2O2 및 DI의 혼합 용액이다.In the above, the metal-
한편, 실리사이드용 금속층을 증착한 후에 캡핑층(capping layer)으로 Ti 또는 TiN을 증착할 수 있다. Ti는 80Å ~ 150Å의 두께로, TiN는 150Å ~ 300Å의 두께로 증착한다.
Meanwhile, after depositing the silicide metal layer, Ti or TiN may be deposited as a capping layer. Ti is deposited at a thickness of 80 kPa to 150 kPa and TiN is deposited at a thickness of 150 kPa to 300 kPa.
상기한 본 발명은 게이트 전극 부분에만 비정질화 이온 주입 공정이 진행되도록 하여 그 표면을 비정질화시키고, 소오스/드레인 접합부는 이온 주입 방지층으로 막아주므로, 고집적 반도체 소자에서 요구되는 얕은 접합부의 기능이 저하되는 것을 방지하면서 고집적 반도체 소자에서 요구되는 선폭이 좁은 게이트 전극 상부의 금속-실리사이드층의 응집 작용(agglomeration)으로 인한 게이트 전극의 면저항이 급격히 증가하는 것을 방지할 수 있다.
According to the present invention, the amorphous ion implantation process is performed only on the gate electrode portion, and the surface is amorphous, and the source / drain junction is prevented by the ion implantation prevention layer, thereby reducing the function of the shallow junction required in the highly integrated semiconductor device. It is possible to prevent a sudden increase in the sheet resistance of the gate electrode due to the agglomeration of the metal-silicide layer on the narrow gate width of the gate electrode required for the highly integrated semiconductor device.
상술한 바와 같이, 본 발명은 로직 소자가 고집적화됨에 따라 나타나는 좁은 선폭의 게이트 전극에서의 샐리사이드 특성 열화를 비정질화 이온 주입 공정으로 개선시킬 수 있고, 비정질화 이온 주입 공정시 나타날 수 있는 소오스/드레인 접합부에서의 누설 전류 특성 열화를 방지할 수 있어, 소자의 전기적 특성 및 신뢰성을 향상시킬 수 있고, 소자의 고집적화를 실현할 수 있다.As described above, the present invention can improve the degradation of salicide characteristics in the gate electrode having a narrow line width as the logic element is highly integrated, and can be improved by an amorphous ion implantation process, and the source / drain may appear during the amorphous ion implantation process. Deterioration of the leakage current characteristic at the junction can be prevented, the electrical characteristics and reliability of the device can be improved, and high integration of the device can be realized.
Claims (10)
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