KR100678228B1 - Apparatus for preventing overflow of uart - Google Patents

Abstract

According to an aspect of the present invention, there is provided an apparatus for preventing a general-purpose asynchronous transceiver overflow, comprising: a main reception memory storing data received under a predetermined control; and an overflow pre-detection using a difference between a write pointer and a read pointer of the main reception memory. A pre-overflow detector, a sub receive memory for storing data received after the pre-overflow detection under predetermined control, and a receive memory controller for controlling data storage in the main receive memory and the sub receive memory.

Universal Asynchronous Receiver and Transmitter (UART), overflow protection

Description

Device for preventing universal asynchronous transceiver overflow {APPARATUS FOR PREVENTING OVERFLOW OF UART}             

1 is an example of a UART block configuration embedded in a mobile terminal;

2 is a block diagram illustrating a reception memory control unit and a reception memory of FIG. 1 according to the prior art;

3 is a block diagram illustrating an apparatus for preventing UART overflow according to an exemplary embodiment of the present invention.

The present invention relates to a memory control device, and more particularly, to an apparatus for preventing overflow in a universal asynchronous receiver and transmitter (UART) embedded in a mobile terminal.

The mobile terminal has a UART (Universal Asynchronous Receiver and Transmitter) for serial interface with an external source (such as a computer). UART enables serial data transfer between a computer and a computer and between the computer and the mobile terminal. The main function of UART is to convert serial data into parallel byte and store it in RX FIFO (First In First Out buffer) so that the controller can read it.In contrast, when the controller writes parallel data to TX FIFO, the parallel data is written. Convert the serial data and send it.

1 illustrates an example of a UART block configuration embedded in a mobile terminal. In FIG. 1, a UART includes a UART transmission block and a UART reception block, a TX memory (TX Random Access Memory (TX_RAM)) 22, and a reception memory (RX_RAM) 24.

The UART transmission block is a block which the control unit (not shown in FIG. 1) reads parallel data written to the transmission memory (TX_RAM) 22, converts it into serial data, and then transmits it. The UART transmission block is composed of TX_MEM_CNTL (26), TX_MEM_STATUS (30), TX_STATE (34), TX_CLKGEN (28), TX_SFT (32), and DATA_OUT (36). The TX_MEM_CNTL 26 is a block for generating the write pointer signal WR_PTR, the read pointer signal RD_PTR, the write enable WR_WEB, and the read chip select signal RD_CSB signal of the signals TX_RAM 22 related to the TX_RAM 22 control. The TX_MEM_STATUS 30 receives the WR_PTR and RD_PTR signals from the TX_MEM_CNTL 26 and generates signals related to the memory state. TX_STATE 34 generates enable signals necessary for converting the parallel data written by the controller into serial data. TX_CLKGEN 28 uses the basic clock provided by UART CLKGEN 16 to generate clocks for transmission. The TX_SFT 32 serves to shift 8-bit data from the TX_RAM 22 in response to the basic clock provided from the UART CLKGEN 16. TX_DATA_OUT 36 serves to trim the data before transmitting the final data.

The UART reception block converts serial data into parallel data and stores the serial data in the reception memory (RX_RAM) 24. The UART receiving block is composed of RX_MEM_CNTL 42, RX_MEM_STATUS 44, RX_STATE 48, RX_CLKGEN 40, RX_SFT 50, and RX_TIME_OUT 46. The RX_MEM_CNTL 42 is a block that generates the write pointer signal WR_PTR, the read pointer signal RD_PTR, the write enable signal WR_WEB, and the read chip select signal RD_CSB signal of the signals related to the RX_RAM 24 control to the RX_RAM 24. to be. In FIG. 2, data input / output and control signals between the RX_MEM_CNTL 42 and the RX_RAM 24 are more clearly shown. The RX_MEM_STATUS 44 of the receiving block receives the WR_PTR and RD_PTR signals from the RX_MEM_CNTL 42 and generates signals related to the memory state. The RX_STATE 48 generates a control signal and an enable signal for converting serial data sent from a transmitter to parallel data into serial data. The RX_CLKGEN 40 generates the clocks for reception using the basic clock provided by the UART CLKGEN 16. The RX_SFT 50 shifts DP_RX_DATA received from the MUX 30 to convert it into parallel data. The RX_TIME_OUT 46 generates a reception timeout interrupt signal RX_STALE_INT when the control unit does not perform a read operation for a predetermined time while the received data is stored in the RX_RAM 24.

In FIG. 1, REG_DEF & ADDR_DEC 10 is a register and address decoder. The BAUD_MN_CLK 14 generates a source clock necessary for performing the UART operation and supplies it to the UART CLKGEN 16. UART CLKGEN 16 divides the source clock provided from BAUD_MN_CLK 14 to generate a basic clock. The CHANNEL 18 generates signals for controlling the UART transmission block and the reception block, and enables the controller to read the memory state during the UART operation. UART_INT 20 is a block for generating UART interrupt signals UART_INT.

Among the factors that determine the data flow rate of the UART as shown in FIG. 1, the biggest influence is the control of the memory TX_RAM 22 and the RX_RAM 24. The larger the memory size, the faster the transfer speed. However, considering the chip area and the power supply, the memory size cannot be increased indefinitely. The control of the transmission memory TX_RAM 22 does not cause a big problem because the control unit performs the data flow control with all the information. However, the control of the reception memory TX_RAM 22 has a threshold value of the number of input bytes in advance. An interrupt is generated when a large number of bytes of data is input. Therefore, the control unit reads the data in the reception memory. However, when the reception memory becomes full faster than the speed at which the controller reads from the reception memory, data may be lost. That is, an RX overrun error occurs. Of course, there are several control methods to prevent the reception overrun error, but if a data overflow occurs, to regain lost data, the external source must be requested again. Therefore, from the controller's point of view, a significant load is generated, and a data transmission delay is generated as long as the source retransmits data.

When a received memory overflow occurs, the lost data must be received again from an external source to regain the lost data. Therefore, there is a significant obstacle to the UART transmission speed, namely transmission delay.

Accordingly, an object of the present invention is to provide an apparatus for overflow prevention in a general-purpose asynchronous transceiver.

In accordance with the above object, the present invention provides a device for preventing a general-purpose asynchronous transceiver overflow, using a main receiving memory for storing data received under predetermined control, and a difference between a write pointer and a read pointer of the main receiving memory. A pre-overflow detector for pre-overflow detection, a sub receive memory for storing data received after the pre-overflow detection under predetermined control, and a receive memory control unit for controlling data storage in the main receive memory and the sub receive memory It is characterized by the configuration.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the same elements in the figures are represented by the same numerals wherever possible. In addition, detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

3 is a block diagram illustrating an apparatus for preventing UART overflow according to an exemplary embodiment of the present invention. As shown in FIG. 3, the apparatus for preventing overflow according to an embodiment of the present invention may include a main receive memory (MAIN_RX_RAM) 62, a sub receive memory (SUB_RX_RAM) 64, and a receive memory controller (RX_MEM_CNTL) 60. ), An overflow pre-detector 66 and a selector 68. In the exemplary embodiment of the present invention, the size of the sub receiving memory 64 is 1/4 of the size of the main receiving memory 62.

Typically, the reception data is stored in the main reception memory 62 under the control of the reception memory control unit 60. When the received data is continuously stored in the main receiving memory 62 in this way, the memory controller 60 keeps increasing the write pointer WR_PTR in response. If the difference between the write pointer WR_PTR and the read pointer RD_PTR of the main receiving memory 62 is greater than the preset reception threshold level, the interrupt signal UART_INT is transmitted to the UART control unit by the RX_MEM_STATUS 48 and the UART_INT (20 in FIG. 1). Accordingly, the UART control unit reads the stored data from the main receiving memory 62.

Hereinafter, an example in which the main receiving memory 62 may overflow may occur when the sub receiving memory 64 and the pre-overflow detector 66 are not present. When the write pointer WR_PTR of the main receiving memory 62 exceeds the preset memory size value, the write pointer WR_PTR returns to "0" again. Until this time, if the UART controller does not read data from the main receive memory 62, a receive memory overflow occurs. The fact that the reception memory overflow occurs means that the first input data among the data that is not read into the main reception memory 62 is lost by inputting the next reception data into the main reception memory 62.

An embodiment of the present invention includes a pre-overflow detector 66, a sub receive memory 64, and a selector 68 to solve a problem such as a reception memory overflow.

Before the overflow, the detector 66 calculates the difference between the write pointer WR_PTR and the read pointer RD_PTR in the main receiving memory 62 and outputs the overflow pre-interrupt signal PRE_DETECT_INT to the RX_MEM_STATUS 44 when the difference becomes less than or equal to "10". At the same time, the overflow pre-detection signal PRE_DETECT_STB is output to the selector 68 and the reception memory controller 60. Accordingly, the RX_MEM_STATUS 44 informs the UART_INT 20 of the overflow pre-interrupt signal PRE_DETECT_INT, and the UART_INT 20 provides the interrupt signal UART_INT to the UART control unit. The UART controller prevents further reception of data in response to the interrupt signal UART_INT. Meanwhile, the reception memory controller 60 receiving the overflow pre-detection signal PRE_DETECT_STB controls the reception data to be written to the main reception memory 62 to be written to the sub reception memory 64. Accordingly, data to be written to the main receiving memory 52 after the overflow pre-detection is written to the sub receiving memory 64.

The UART control then uses the selector 68 to first read data from the main receive memory 62 and then to read data from the sub receive memory 64. When all data from the sub receiving memory 64 is read, the overflow pre-detection signal PRE_DETECT_STB is cleared. Accordingly, the received data is input to the main receiving memory 62, and in response, the write pointer WR_PTR of the main receiving memory 62 increases again.

In the above description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the equivalent of claims and claims.

As described above, the present invention can prevent the overflow in the reception memory in advance by using the sub receiving memory and the pre-overflow detector when the overflow occurs. As a result, the load on the UART control unit can be reduced, thereby reducing overall system performance and UART data transmission time.

Claims (3)

An apparatus for preventing universal asynchronous transceiver overflow, A main receiving memory for storing data received under predetermined control; A pre-overflow detector for calculating a difference between a write pointer and a read pointer of the main receiving memory, and generating an interrupt signal to detect an overflow of the main receiving memory when the difference has a value smaller than a preset threshold value; A sub receiving memory for storing data received in response to the generated interrupt signal; And a reception memory controller configured to stop a write operation of the main receive memory and start a write operation of the sub receive memory in response to the generated interrupt signal. The overflow preventing apparatus of claim 1, wherein the size of the sub receive memory is one fourth of the size of the main receive memory. The overflow preventing apparatus according to claim 1, further comprising a selector for selectively reading first data from the main receiving memory and second data from the sub receiving memory.

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