KR100221297B1 - First-in and first-out buffer - Google Patents

Abstract

The present invention relates to an improved FIFO buffer, comprising: a RAM array (1) for storing data to be transferred between processors; A write pointer 2 for storing a pointer value indicating a position at which data is to be stored in the RAM array 1; A read pointer 3 for storing a pointer value indicating a position to read data stored in the RAM array 1; A flag generating unit 4 for indicating whether the write and read operations are possible; A pointer setting unit 5 that newly sets a pointer value so that data write and read operations can be started at an arbitrary position of the RAM array 1; A write control unit 6 for storing data at a location corresponding to a pointer value stored in the write pointer 1 and incrementing a pointer value by 1 when the WR signal is input; And a read control unit 7 for reading the data corresponding to the pointer value stored in the read pointer 3 and decreasing the pointer value by 1 when the RD signal is inputted. When the data is written to or read from the FIFO buffer, The pointer and the write pointer can be arbitrarily designated, whereby data can be read and written at an arbitrary position in the memory, and the data read / write operation can be performed quickly and efficiently.

Description

Improved first-in first-out buffer (An improved FIFO buffer)

FIG. 1 is an internal block diagram of a conventional first-in first-out (FIFO) buffer.

FIG. 2 is an internal block diagram of an improved first-in first-out (FIFO) buffer according to the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

1: RAM array 2: read pointer

3: write pointer 4: flag generator

5: pointer setting unit 6: write control unit

7: Read control section 8: Write pointer register

9: Read pointer register 10: Pointer register

WR: Write signal RD: Read signal

FF: full flag signal EF: empty flag signal

WPS: Write pointer set signal RPS: Read pointer set signal

The present invention relates to a first-in first-out (FIFO) buffer, and more particularly to an improved FIFO buffer capable of reading and writing data at an arbitrary memory location by changing a data reading pointer and a writing pointer of the FIFO buffer .

Generally, when data is transferred between processors, there is a difference in data processing speed of each processor. Therefore, a standby state occurs during data transfer. To prevent such a situation and to shorten data processing speed, And a FIFO buffer is placed between the processor and the processor to buffer the input and output of the transmission data. At this time, the method of processing the data transmitted from the FIFO buffer is a first-in first-out method in which the first data inputted first is output first.

Data transfer between the processors using the FIFO buffer will be described as follows.

FIG. 1 is an internal block diagram of a conventional FIFO buffer. As shown in FIG. 1, a RAM array 1, a write pointer 2, a read pointer 3, a flag generating section 4, a write control section 6, and a read control section 7 Consists of.

Here, the RAM array 1 stores data to be transferred between the processor and the processor, and if the current FIFO buffer has no area for storing data, the flag generator 4 outputs a full flag Quot; LOW "state so that the transmission processor, not shown, can not write data to the FIFO buffer, and if there is no data stored in the current FIFO buffer, an empty flag (EF) Quot; LOW "state so that the receiving processor, which is not shown, can no longer read data in the FIFO buffer.

In addition, the pointer pointer 2 and the read pointer 3 store the current pointer value at which data is read and written, and the pointer value is increased or decreased according to the read and write operations.

When a write signal is input from the transmission processor, the write control unit 6 stores the data input through the bus in a location designated by the pointer value of the write pointer 2, and increments the pointer value by 1 The read control unit 7 outputs the data designated by the read pointer 3 when the read signal RD is input from the reception processor, and then decrements the pointer value by one.

However, in the conventional FIFO buffer operating as described above, when the data which has already been read is re-read or the data is written from the memory corresponding to the current write pointer value, Re-Transmit function is used to move the pointer to the initial position to read or write data. Therefore, when the length of the FIFO buffer is long, the data reading or writing operation is inefficient.

In order to solve the above problems, the present invention provides an improved FIFO buffer which can read and write data at an arbitrary position by changing the data read pointer and the write pointer of the FIFO buffer in processing the data of the FIFO buffer. The purpose of the buffer is to provide.

According to an aspect of the present invention, there is provided a method of controlling a processor including a RAM array for storing data to be transferred between processors, A write pointer for storing a pointer value indicating a position at which data is to be stored in the RAM array; A read pointer for storing a pointer value indicating a location to read data stored in the RAM array; A flag generating unit for indicating whether a write and a read operation are possible; A pointer setting unit that newly sets a pointer value so that writing and reading operations of data can be started at an arbitrary address of the RAM array; A write controller for storing data at a location corresponding to a pointer value stored in the write pointer and incrementing the pointer value by 1 when a WR signal is input; And a read control unit for reading data corresponding to a pointer value stored in the read pointer and decrementing the pointer value by 1 when an RD signal is input.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is an internal block diagram of an improved first-in first-out (FIFO) buffer according to the present invention.

As shown in FIG. 2, the present invention comprises a RAM array 1 for storing data transferred between processors; A write pointer 2 for storing a pointer value indicating a position at which data is to be stored in the RAM array 1; A read pointer 3 for storing a pointer value indicating a position to read data stored in the RAM array 1; A flag generating unit 4 for indicating whether the write and read operations are possible; A pointer setting unit 5 for newly setting a pointer value so that data write and read operations can be started at an arbitrary position of the RAM array 1; A write controller 6 for storing data corresponding to a pointer value stored in the write pointer 2 and increasing the pointer value by 1 when a WR signal is input; And a read control unit 7 for reading data corresponding to a pointer value stored in the read pointer 3 and decrementing the pointer value by 1 when an RD signal is input.

The pointer setting unit 5 includes a write pointer register 8 for storing a designated write pointer value for performing a data write operation at an arbitrary position of the RAM array 1; A read pointer register (9) for storing a designated read pointer value for reading data from an arbitrary position of the RAM array (1); And a pointer register 10 for storing a pointer value of the write pointer 2 and a pointer value of the read pointer 3 immediately before a write and a read operation are arbitrarily performed with the designated pointer value.

The functions and effects of the preferred embodiment of the present invention constructed as described above are as follows.

In order to perform a data write operation on the RAM array 1, the transmitting processor must first check the FF signal state of the flag generator 4. If the state of the FF signal is confirmed to be "High ", the WR signal is input to the write control unit 6 at the transmission processor side. At this time, the write control unit 6 sets the pointer value of the write pointer 2 Performs a write operation from the corresponding position of the RAM array (1) and increases the value of the write pointer (2) by one. When a normal write operation as described above is performed, a write pointer set (WPS) signal input to the pointer setting unit 5 is disabled in a "high" state.

If the WPS signal is enabled in the "LOW" state, a write pointer value for performing a data write operation from an arbitrary position in the RAM array 1 is written to the write pointer register 8, And a pointer value of the write pointer 2 immediately before the WPS "low" signal is input is stored in the pointer register 10. [

Accordingly, a data write operation is performed from the position of the RAM array 1 corresponding to the write pointer value stored in the write pointer register 8, and the pointer value of the write pointer 2 is stored in the write pointer register 8, Is incremented by 1 from the value of the write pointer stored in < / RTI >

When the WPS "high" signal is input in the middle of a data write operation from an arbitrary position of the RAM array 1 as described above, the value of the write pointer 2 is written to the write pointer register 8 , And the pointer value of the write pointer 2 is incremented by one from the write pointer value stored in the pointer register 10, so that the data write operation is normally performed.

Conversely, in order to read the data input to the RAM array 1, the receiving processor must first check the EF signal state of the flag generator 4. If the state of the EF signal is confirmed to be in the "High" state, the RD signal is input on the receiving processor side. At this time, the read controller 7 reads out the RAM array 1 ), And decrements the value of the read pointer 3 by one. When a normal read operation as described above is performed, a read pointer set (RPS) signal input to the pointer setting unit 5 is disabled in a "high" state.

If the RPS signal is enabled in a low state, a pointer value for performing a data read operation from an arbitrary position of the RAM array 1 is stored in the read pointer register 9 as a data bus And the pointer value of the read pointer 3 immediately before the RPS "low" signal is input is stored in the pointer register 10.

The pointer value of the read pointer 3 is read from the position of the RAM array 1 corresponding to the read pointer value stored in the read pointer register 9, Is decremented by 1 from the value of the read pointer stored in the read pointer.

When the RPS "high" signal is input in the middle of a data read operation from an arbitrary position of the RAM array 1 as described above, the value of the read pointer 3 is set in the read pointer register 9 , And the pointer value of the read pointer 2 is decremented by one from the read pointer value stored in the pointer register 10, and the data read operation is normally performed.

As described above, according to the present invention, when data is written to or read from the FIFO buffer, a data read pointer and a write pointer can be arbitrarily designated, whereby data can be read and written at an arbitrary position in the memory, The reading or writing operation can be performed quickly and efficiently.

Claims (1)

A read pointer for storing a pointer value indicating a location to read data stored in the RAM array, a write pointer for storing a pointer value indicating a location where data is to be stored in the RAM array, A write control unit for storing data at a location corresponding to a pointer value stored in the write pointer and incrementing the pointer value by 1 when a WR signal is input; (FIFO) buffer for reading data corresponding to a pointer value stored in the read pointer and decrementing the pointer value by 1, the buffer comprising: To save the specified write pointer value to perform the action Write pointer register; A read pointer register for storing a read pointer value designated for reading data from an arbitrary position of the RAM array; And a pointer register for storing a pointer value of the write pointer and a pointer value of the read pointer immediately before a write operation and a read operation are arbitrarily performed according to the designated pointer value, And a pointer setting unit for newly setting a pointer value to start at an arbitrary position in the array.