KR100676315B1 - High thermal emissive semiconductor chip package - Google Patents

High thermal emissive semiconductor chip package Download PDF

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KR100676315B1
KR100676315B1 KR1020000013015A KR20000013015A KR100676315B1 KR 100676315 B1 KR100676315 B1 KR 100676315B1 KR 1020000013015 A KR1020000013015 A KR 1020000013015A KR 20000013015 A KR20000013015 A KR 20000013015A KR 100676315 B1 KR100676315 B1 KR 100676315B1
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semiconductor chip
heat
chip package
cooling
heat dissipation
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KR20010091380A (en
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정연근
김영대
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삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

본 발명은 고열방출 반도체 칩 패키지로서, 반도체 칩의 동작 시에 발생하는 열의 전도 또는 방출을 위하여, 전극패드가 일면에 형성된 반도체 칩과, 그 반도체 칩이 실장된 기판, 및 반도체 칩을 봉지하는 봉지부를 포함하며, 반도체 칩의 전극패드 형성면과 수평을 이루면서 봉지부를 관통하게 형성된 복수의 냉각구멍이 형성된 것을 특징으로 한다. 본 발명에 따르면 공기와 접하는 면적이 증가되어 열방출이 잘 이루어질 수 있다. 방열판 내부 또는 기판과 방열판의 사이의 공간에 냉각구멍을 갖도록 하여 방열 또는 냉각 효과를 극대화시키고, 반도체 칩과 직접적으로 닿는 부분을 냉각시켜 안정적인 고속 동작을 확보할 수 있다. 특히, 고속 중앙처리장치에 효과적으로 적용될 수 있다.The present invention is a high heat dissipation semiconductor chip package, in order to conduct or dissipate heat generated during operation of a semiconductor chip, a semiconductor chip having an electrode pad formed on one surface thereof, a substrate on which the semiconductor chip is mounted, and an encapsulation sealing the semiconductor chip. And a plurality of cooling holes formed to pass through the encapsulation part while being parallel to the electrode pad forming surface of the semiconductor chip. According to the present invention, the area in contact with the air is increased, so that heat can be released well. Cooling holes may be provided in the heat sink or in the space between the substrate and the heat sink to maximize the heat dissipation or cooling effect, and cool the part directly contacting the semiconductor chip to ensure stable high speed operation. In particular, it can be effectively applied to a high speed central processing unit.

히트 스프레드, 히트 슬러그, 방열판, 반도체 칩 패키지, 중앙처리장치Heat Spreads, Heat Slugs, Heat Sinks, Semiconductor Chip Packages, Central Processing Units

Description

고 열방출 반도체 칩 패키지{High thermal emissive semiconductor chip package}High thermal emissive semiconductor chip package

도 1과 도 2는 종래 기술에 따른 반도체 칩 패키지의 일 예를 나타낸 단면도,1 and 2 are cross-sectional views showing an example of a semiconductor chip package according to the prior art;

도 3은 본 발명에 따른 고 열방출 반도체 칩 패키지의 제 1실시예를 나타낸 단면도,3 is a cross-sectional view showing a first embodiment of a high thermal emission semiconductor chip package according to the present invention;

도 4는 본 발명에 따른 고 열방출 반도체 칩 패키지의 제 2실시예를 나타낸 단면도,4 is a cross-sectional view showing a second embodiment of a high thermal emission semiconductor chip package according to the present invention;

도 5는 본 발명에 따른 고 열방출 반도체 칩 패키지의 제 3실시예를 나타낸 단면도,5 is a cross-sectional view showing a third embodiment of a high thermal emission semiconductor chip package according to the present invention;

도 6은 본 발명에 따른 고 열방출 반도체 칩 패키지의 제 4실시예를 나타낸 단면도이다.6 is a cross-sectional view showing a fourth embodiment of a high heat dissipation semiconductor chip package according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

10; 반도체 칩 패키지 11; 반도체 칩10; Semiconductor chip package 11; Semiconductor chip

13; 전극패드 15; 도전성 금속선13; Electrode pads 15; Conductive metal wire

21; 기판 23; 접합패드21; Substrate 23; Bonding pad

25; 방열판 26; 냉각구멍25; Heat sink 26; Cooling hole

27; 냉각관 28; 외부 접속 핀27; Cooling tube 28; External connection pin

29; 금속덮개(metal lid)29; Metal lid

본 발명은 반도체 칩 패키지에 관한 것으로서, 더욱 상세하게는 반도체 칩의 동작 시에 발생하는 열의 전도 또는 방출을 위한 냉각구멍이 형성된 고 열방출 반도체 칩 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip package, and more particularly, to a high heat dissipation semiconductor chip package having cooling holes for conducting or releasing heat generated during operation of a semiconductor chip.

집적회로가 형성된 반도체 칩을 내장하여 구성되는 반도체 칩 패키지는 기판에 실장되어 동작될 때 열이 발생하게 된다. 발생된 열은 집적회로에 손상을 일으킬 뿐만 아니라 패키지 내부에 열로 인한 응력이 발생되어 여러 가지 문제점을 야기한다. 특히, 이러한 문제는 컴퓨터의 중앙처리장치(CPU)에 적용되는 반도체 칩 패키지에서 더욱 문제시되며, 워크 스테이션 등에서 사용되는 중앙처리장치는 고전력(high power)을 이용하기 때문에 더욱 그러하다. 따라서, 반도체 칩 패키지 내부에서 발생하는 열을 효율적으로 제거하는 것이 매우 중요하다. 중앙처리장치에 사용되는 대표적인 반도체 칩 패키지는 전기적 연결에 있어서의 특징에 따라 와이어 본딩(wire bonding) 기술을 이용한 형태와 플립 칩 본딩(flip chip bonding) 기술을 이용한 형태의 두 가지 구조로 구분될 수 있다. 이를 살펴보기로 한다.A semiconductor chip package including a semiconductor chip having an integrated circuit formed therein generates heat when mounted and operated on a substrate. The generated heat not only damages the integrated circuit, but also causes heat stress inside the package, which causes various problems. In particular, this problem is more problematic in a semiconductor chip package applied to a central processing unit (CPU) of a computer, and more particularly since a central processing unit used in a workstation or the like uses high power. Therefore, it is very important to efficiently remove heat generated inside the semiconductor chip package. The representative semiconductor chip package used in the central processing unit can be divided into two structures, one using wire bonding technology and one using flip chip bonding technology, depending on the characteristics of the electrical connection. have. Let's look at it.

도 1은 와이어 본딩 기술을 이용한 종래의 반도체 칩 패키지를 나타낸 단면도이다.1 is a cross-sectional view illustrating a conventional semiconductor chip package using a wire bonding technique.

도 1을 참조하면, 이 반도체 칩 패키지(110)는 반도체 칩(111)과의 전기적인 연결에 있어서 와이어 본딩 기술을 이용한 전형적인 중앙처리장치의 반도체 칩 패키지이다. 반도체 칩(111)은 기판(121)의 중앙부에 형성된 홈에 위치하도록 하여 기판(121)에 부착된 방열판(125)에 실장된다. 반도체 칩(111)의 전극패드(113)는 기판(121)의 접속패드(123)에 도전성 금속선(127)으로 와이어 본딩되어 전기적인 연결을 이루며, 기판(121)에 형성되어 있는 내부 공간은 금속 덮개(metal lid; 129)로 밀폐된다. 기판(121)으로부터 돌출되도록 형성되어 있는 외부 접속 핀(128)이 외부 기판에의 실장에 이용된다. 그리고, 방열판(125)은 내부에서 발생된 열을 외부로 방출시킨다.Referring to FIG. 1, this semiconductor chip package 110 is a semiconductor chip package of a typical central processing unit using wire bonding technology in electrical connection with the semiconductor chip 111. The semiconductor chip 111 is mounted on the heat sink 125 attached to the substrate 121 so as to be positioned in a groove formed in the center portion of the substrate 121. The electrode pad 113 of the semiconductor chip 111 is wire-bonded with a conductive metal wire 127 to the connection pad 123 of the substrate 121 to form an electrical connection, and the internal space formed on the substrate 121 is made of metal. It is sealed with a metal lid 129. The external connection pin 128 formed to protrude from the substrate 121 is used for mounting on the external substrate. Then, the heat sink 125 releases heat generated therein to the outside.

도 2는 플립 칩 본딩 기술을 이용한 종래의 반도체 칩 패키지를 나타낸 단면도이다.2 is a cross-sectional view illustrating a conventional semiconductor chip package using a flip chip bonding technique.

도 2를 참조하면, 이 반도체 칩 패키지(130)는 플립 칩 본딩 기술을 이용한 전형적인 중앙처리장치의 반도체 칩 패키지이다. 반도체 칩(131)은 평판 형태의 기판(141) 중앙부에 플립 칩 본딩, 즉 반도체 칩(131)에 형성된 범프(134)와 기판(141)의 접합패드(143)가 접합되어 반도체 칩(131)의 실장과 전기적인 연결을 동시에 이룬다. 반도체 칩(131)을 포함하여 기판(131) 상부는 에폭시계 성형 수지 등의 봉지재로 형성되는 봉지부(149)에 둘러싸여 외부환경으로부터 보호된다. 이 반도체 칩 패키지(130) 역시 기판(141)으로부터 돌출되도록 형성되어 있는 외부 접속 핀(148)이 외부 기판에의 실장에 이용된다. 봉지부(149)에는 동작 시에 발생되는 열의 방출을 위하여 방열판(145)이 부착된다.2, the semiconductor chip package 130 is a semiconductor chip package of a typical central processing unit using flip chip bonding technology. In the semiconductor chip 131, flip chip bonding, that is, a bump 134 formed on the semiconductor chip 131 and a bonding pad 143 of the substrate 141 are bonded to a center portion of the substrate 141 having a flat plate shape, thereby forming the semiconductor chip 131. The electrical connection is made at the same time. The upper portion of the substrate 131 including the semiconductor chip 131 is surrounded by an encapsulation portion 149 formed of an encapsulant such as an epoxy-based molding resin and protected from an external environment. The semiconductor chip package 130 also uses an external connection pin 148 formed to protrude from the substrate 141 to be mounted on the external substrate. A heat sink 145 is attached to the encapsulation part 149 to release heat generated during operation.

이와 같은 반도체 칩 패키지는 동작 시에 발생되는 내부의 열이 방열판을 통해 외부로 방출시키는 구조로 제조 공정이 간단하고 제조 비용이 저렴한 이점을 가지고 있다. 그러나, 전력소비의 증가와 동작 주파수가 높아짐에 따라 도전성 금속선을 통한 전기적 신호의 전송속도가 상대적으로 느려지며 열의 방출에도 한계가 있다. 반도체 칩 패키지의 주변에 보조 냉각 장치를 추가하여 반도체 칩 패키지의 동작 시에 발생하는 열의 냉각을 위한 방안들이 모색되고 있기는 하지만, 반도체 칩 패키지 자체로서 발생된 열을 신속하게 방출시킬 수 있는 방안이 요구되고 있다.Such a semiconductor chip package has a structure in which internal heat generated during operation is released to the outside through a heat sink, which has a simple manufacturing process and low manufacturing cost. However, as the power consumption increases and the operating frequency increases, the transmission speed of the electrical signal through the conductive metal wire is relatively slow and there is a limit in heat emission. Although a method for cooling the heat generated when the semiconductor chip package is operated by adding an auxiliary cooling device around the semiconductor chip package is being sought, there is a method to rapidly release the heat generated by the semiconductor chip package itself. It is required.

본 발명의 목적은 신호 처리 속도와 소비 전력의 증가에 따른 열 방출 문제를 해결하여 보다 동작에 있어서의 신뢰성을 향상시킬 수 있는 구조의 반도체 칩 패키지를 제공하는 데 있다.An object of the present invention is to provide a semiconductor chip package having a structure that can improve the reliability in operation by solving the heat dissipation problem caused by the increase in signal processing speed and power consumption.

이와 같은 목적을 달성하기 위한 본 발명에 따른 고 열방출 반도체 칩 패키지는, 집적회로가 형성된 반도체 칩이 내재되어 봉지되는 반도체 칩 패키지로서 복수의 냉각구멍이 형성되어 있는 것을 특징으로 한다. 냉각구멍은 반도체 칩을 밀폐시키는 봉지부에 형성되거나 그 봉지부에 열방출을 위해 부착되는 히트싱크에 형성되며, 반도체 칩과 수평을 이루는 방향으로 반도체 칩 패키지를 관통하도록 형성된다. 이에 따라 공기와 접하는 면적이 증가되어 열방출이 잘 이루어질 수 있다. 그리고, 냉각구멍의 배치형태는 "+"자 형태나 "×"자 형태가 되도록 복수의 냉각구멍 을 형성하는 것이 바람직하다. 냉각구멍은 봉지부 또는 히트싱크를 형성할 때 만들어 질 수 있으나, 냉각구멍을 형성하는 냉각관의 삽입으로 용이하게 형성할 수 있다. 이때, 냉각관은 사각, 원, 및 세모형 등 다양한 형태의 것이 사용될 수 있다.The high heat dissipation semiconductor chip package according to the present invention for achieving the above object is characterized in that a plurality of cooling holes are formed as a semiconductor chip package in which a semiconductor chip in which an integrated circuit is formed is enclosed. The cooling hole is formed in an encapsulation part enclosing the semiconductor chip or in a heat sink attached to the encapsulation part for heat dissipation, and is formed to penetrate the semiconductor chip package in a direction parallel to the semiconductor chip. Accordingly, the area in contact with the air is increased, so that the heat can be released well. And it is preferable to form a some cooling hole so that the arrangement | positioning form of a cooling hole may become a "+" shape or a "x" shape. The cooling hole may be made when the encapsulation part or the heat sink is formed, but may be easily formed by the insertion of the cooling tube forming the cooling hole. At this time, the cooling tube may be used in various forms such as square, circle, and triangular.

이하 첨부 도면을 참조하여 본 발명에 따른 고 열방출 반도체 칩 패키지를 보다 상세하게 설명하고자 한다.Hereinafter, a high thermal emission semiconductor chip package according to the present invention will be described in detail with reference to the accompanying drawings.

도 3은 본 발명에 따른 고 열방출 반도체 칩 패키지의 제 1실시예를 나타낸 단면도이다.3 is a cross-sectional view showing a first embodiment of a high thermal emission semiconductor chip package according to the present invention.

도 3을 참조하면, 이 반도체 칩 패키지(10)는 와이어 본딩 기술을 이용한 예로서 방열 특성의 향상을 위해 냉각구멍(26)이 형성된 특징을 가지고 있다. 반도체 칩(11)은 기판(21)에 부착된 방열판(25)에 실장되어 전극패드(13)가 기판(21)의 접합패드(23)와 도전성 금속선(15)으로 와이어 본딩되어 기판(21) 하부로 돌출된 외부 접속 핀(28)에 전기적으로 연결된 구조로서, 반도체 칩(11)은 금속덮개(29)에 의해 봉지되어 있다. 그리고, 방열판(25)에는 그 방열판(25)을 관통하는 냉각구멍(26)이 형성되어 반도체 칩(11)의 전극패드(13) 형성면과 수평을 이루도록 하여 복수 개가 일정 간격을 이루고 있다. 소자 동작시 기판(21)과 반도체 칩(11)에 부착된 방열판(25)으로 열이 전달되어 발산 및 냉각되며, 특히 방열판(25)에 형성된 냉각구멍(26)에 의해 공기와의 접촉 면적이 증가되어 방열 효과를 향상시킨다. 냉각구멍(26)은 방열판(25) 전체에 걸쳐 고른 분포를 갖고 있어 더욱 우수한 방열의 효과를 얻을 수 있다. 방열판(25)에 형성된 냉각구멍(26)은 방열판 제조 단계에서 형성할 수 있다.Referring to FIG. 3, the semiconductor chip package 10 has a feature in which cooling holes 26 are formed to improve heat dissipation characteristics as an example using a wire bonding technique. The semiconductor chip 11 is mounted on a heat sink 25 attached to the substrate 21 so that the electrode pad 13 is wire-bonded with the bonding pad 23 of the substrate 21 and the conductive metal wire 15 to the substrate 21. The semiconductor chip 11 is encapsulated by the metal cover 29 as the structure electrically connected to the external connection pin 28 protruding downward. Cooling holes 26 penetrating through the heat sink 25 are formed in the heat sink 25 so as to be parallel to the electrode pad 13 forming surface of the semiconductor chip 11 at a predetermined interval. During device operation, heat is transferred to the heat sink 25 attached to the substrate 21 and the semiconductor chip 11 to dissipate and cool. In particular, the contact area with air is reduced by the cooling holes 26 formed in the heat sink 25. It is increased to improve the heat dissipation effect. The cooling holes 26 have an even distribution over the entire heat sink 25, so that an excellent heat dissipation effect can be obtained. The cooling hole 26 formed in the heat sink 25 may be formed in the heat sink manufacturing step.

도 4는 본 발명에 따른 고 열방출 반도체 칩 패키지의 제 2실시예를 나타낸 단면도이다.4 is a cross-sectional view showing a second embodiment of a high heat dissipation semiconductor chip package according to the present invention.

도 4를 참조하면, 이 반도체 칩 패키지(30)는 플립 칩 본딩 기술을 이용한 반도체 칩 패키지로서, 역시 냉각구멍(46a)이 방열판(45)에 형성되어 있는 특징이 있다. 반도체 칩(31)은 기판(41)에 플립 칩 본딩 기술에 의해 범프(34)와 기판(41)의 접합패드(43)가 접합되어 기판(41) 하부로 돌출된 외부 접속 핀(48)에 전기적으로 연결된 구조이다. 기판(41)과 방열판(45) 사이의 공간은 봉지재로 봉지부(49)가 형성되어 반도체 칩(31)을 보호한다. 그리고, 방열판(45)에는 그 방열판을 관통하는 냉각구멍(46a)이 형성되어 있다. 냉각구멍(46a)은 반도체 칩(31)의 전극패드(33) 형성면과 수평을 이루도록 하여 복수 개가 일정 간격을 이룬다. 또한, 반도체 칩(31)과 방열판(45)의 사이에 냉각구멍(46b)을 형성하도록 중심이 비어 있는 얇고 가는 냉각관(47)이 삽입되어 있다.Referring to FIG. 4, the semiconductor chip package 30 is a semiconductor chip package using a flip chip bonding technique, in which cooling holes 46a are formed in the heat sink 45. The semiconductor chip 31 is bonded to the substrate 41 by the flip chip bonding technique, and the bump 34 and the bonding pad 43 of the substrate 41 are bonded to the external connection pins 48 protruding below the substrate 41. It is an electrically connected structure. The space between the substrate 41 and the heat sink 45 is formed with an encapsulant 49 to protect the semiconductor chip 31. And the heat sink 45 is formed with the cooling hole 46a which penetrates the heat sink. The plurality of cooling holes 46a are formed to be parallel to the electrode pad 33 forming surface of the semiconductor chip 31 to form a plurality of predetermined intervals. In addition, a thin thin cooling tube 47 having an empty center is inserted between the semiconductor chip 31 and the heat sink 45 so as to form the cooling holes 46b.

여기서, 방열판(45)에 형성된 냉각구멍(46a)은 방열판 제작 시에 형성할 수 있으며, 봉지부(49)에 형성된 냉각구멍(46b)은 봉지할 때 중심이 비어있는 얇고 가는 냉각관(47)의 삽입으로 형성할 수 있다. 냉각관(47)의 형태는 사각, 원, 삼각 등 다양한 형태가 적용될 수 있으며, 그 길이는 방열판(45)의 길이와 같거나 작도록 형성한다. 냉각관(47)의 길이가 방열판(45)의 길이와 동일한 경우 공기의 흐름으로 냉각이 가능하여 냉각효과가 향상되고, 냉각관(47)의 길이가 방열판(45)의 길이보다 짧은 경우에 냉매의 삽입으로 냉각효과가 향상될 수 있다. 냉각구멍들(46a,46b)이 공기와 접촉하는 경우에 반도체 칩 패키지(30) 외부에 설치 되는 냉각팬(도시안됨)에서 발생되는 바람을 냉각구멍을 통하여 한쪽 방향으로 흐르게 함으로써 급속한 냉각 작용이 가능하게 된다.Here, the cooling hole 46a formed in the heat sink 45 may be formed at the time of manufacturing the heat sink, and the cooling hole 46b formed in the encapsulation part 49 may be a thin and thin cooling tube 47 having an empty center when sealed. It can be formed by the insertion of. The shape of the cooling tube 47 may be applied in various forms such as square, circle, triangular, the length is formed to be equal to or less than the length of the heat sink (45). If the length of the cooling tube 47 is the same as the length of the heat sink 45, cooling is possible by the flow of air to improve the cooling effect, the refrigerant when the length of the cooling tube 47 is shorter than the length of the heat sink 45 By the insertion of the cooling effect can be improved. When the cooling holes 46a and 46b come into contact with air, the air generated by the cooling fan (not shown) installed outside the semiconductor chip package 30 flows in one direction through the cooling holes to enable rapid cooling. Done.

냉각구멍(46a,46b)들은 "+"자 형태나 "×"자 모양으로 교차시켜 2중으로 형성시킬 수도 있으며, 냉각관의 교차점에 구멍을 뚫어 공기가 자연스럽게 대류가 되도록 하여 냉각효과를 극대화시킬 수도 있다.Cooling holes 46a and 46b may be doubled by intersecting in a "+" shape or a "×" shape, and may maximize the cooling effect by opening a hole at the intersection of the cooling pipe to allow air to naturally convection. have.

본 발명은 위에 소개한 실시예에 제한되는 것은 아니며, 본 발명의 기술적 중심사상을 벗어나지 않는 범위 내에서 다양한 형태로 변형 실시될 수 있다. 와이어 본딩 또는 플립 칩 본딩 기술의 어느 하나를 이용하는 반도체 칩 패키지 형태에 제한되지 않고 다양하게 변형 실시될 수 있으며, 냉각구멍의 형성위치도 다양한 형태로 변화될 수 있다. 예를 들어, 도 5는 본 발명에 따른 고 열방출 반도체 칩 패키지의 제 3실시예를 나타낸 단면도로서, 이 반도체 칩 패키지(50)는 냉각구멍(46)을 방열판(25)에만 갖고 있고, 도 6은 본 발명에 따른 고 열방출 반도체 칩 패키지의 제 4실시예를 나타낸 단면도로서, 이 반도체 칩 패키지(60)는 냉각구멍(46b)을 형성하는 냉각관(47)을 봉지부(49)에만 갖는다. The present invention is not limited to the above-described embodiments, and may be modified in various forms without departing from the technical spirit of the present invention. The present invention is not limited to a semiconductor chip package using any one of wire bonding or flip chip bonding techniques, and various modifications may be made. The location of the cooling hole may be changed in various forms. For example, FIG. 5 is a cross-sectional view showing a third embodiment of the high heat dissipation semiconductor chip package according to the present invention. The semiconductor chip package 50 has the cooling holes 46 only in the heat sink 25, and FIG. 6 is a cross-sectional view showing a fourth embodiment of the high heat dissipation semiconductor chip package according to the present invention, in which the semiconductor chip package 60 has only the sealing portion 49 having the cooling tube 47 forming the cooling holes 46b. Have

이상과 같은 본 발명에 의한 반도체 칩 패키지는 종래의 반도체 칩 패키지 구조와는 달리 방열판 내부 또는 기판과 방열판의 사이공간에 냉각구멍을 갖도록 하여 방열 또는 냉각효과를 극대화시키고, 반도체 칩과 직접적으로 닿는 부분을 냉각시켜 안정적인 고속 동작을 확보할 수 있다. 특히, 고속 중앙처리장치에 효과적으로 적용될 수 있다.Unlike the conventional semiconductor chip package structure, the semiconductor chip package according to the present invention has a cooling hole in the heat sink or a space between the substrate and the heat sink to maximize the heat dissipation or cooling effect, and the part directly contacting the semiconductor chip. Cooling can secure stable high speed operation. In particular, it can be effectively applied to a high speed central processing unit.

Claims (4)

전극패드가 일면에 형성된 반도체 칩과 상기 반도체 칩이 실장된 기판 및 상기 반도체 칩을 봉지하는 봉지부를 포함하며, 상기 봉지부에 상기 반도체 칩의 전극패드 형성면과 수평을 이루면서 상기 봉지부를 관통하게 복수의 냉각구멍이 형성된 것을 특징으로 하는 고열방출 반도체 칩 패키지.An electrode pad includes a semiconductor chip formed on one surface, a substrate on which the semiconductor chip is mounted, and an encapsulation portion encapsulating the semiconductor chip. The encapsulation portion penetrates the encapsulation portion while being parallel to the electrode pad forming surface of the semiconductor chip. A high heat-emitting semiconductor chip package, characterized in that the cooling hole of the formed. 제1 항에 있어서, 상기 반도체 칩과 상기 봉지부 중 적어도 어느 하나에 부착되는 방열판을 가지며, 상기 방열판이 상기 반도체 칩의 전극패드 형성면과 수평을 이루면서 상기 방열판을 관통하게 복수의 냉각구멍이 형성된 것을 특징으로 하는 고 열방출 반도체 칩 패키지.The semiconductor device of claim 1, further comprising a heat dissipation plate attached to at least one of the semiconductor chip and the encapsulation unit, wherein the heat dissipation plate is horizontal to the electrode pad forming surface of the semiconductor chip, and a plurality of cooling holes are formed through the heat dissipation plate. A high heat dissipation semiconductor chip package, characterized in that. 제 1항에 있어서, 상기 봉지부를 관통하게 냉각관이 삽입되어 상기 냉각구멍이 형성된 것을 특징으로 하는 고 열방출 반도체 칩 패키지.The high heat dissipation semiconductor chip package according to claim 1, wherein a cooling tube is inserted through the encapsulation portion to form the cooling hole. 전극패드가 형성된 반도체 칩과, 상기 반도체 칩이 플립 칩 본딩되는 기판과, 상기 반도체 칩을 봉지시키는 봉지부, 및 상기 봉지부에 부착되고 상기 반도체 칩의 전극패드 형성면과 수평을 이루면서 상기 봉지부를 관통하게 형성된 복수의 냉각구멍이 형성된 방열판을 구비하며, 상기 반도체 칩의 전극패드 형성면과 수평을 이루면서 상기 봉지부를 관통하게 복수의 냉각구멍이 형성된 것을 특징으로 하는 고 열방출 반도체 칩 패키지.A semiconductor chip having an electrode pad formed thereon, a substrate on which the semiconductor chip is flip chip bonded, an encapsulation portion encapsulating the semiconductor chip, and an encapsulation portion attached to the encapsulation portion and horizontally formed with an electrode pad forming surface of the semiconductor chip. And a heat dissipation plate having a plurality of cooling holes formed therethrough, and having a plurality of cooling holes penetrating the encapsulation portion while being horizontal with the electrode pad forming surface of the semiconductor chip.
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