KR100673113B1 - Method for forming semiconductor device - Google Patents

Method for forming semiconductor device Download PDF

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KR100673113B1
KR100673113B1 KR1020040115454A KR20040115454A KR100673113B1 KR 100673113 B1 KR100673113 B1 KR 100673113B1 KR 1020040115454 A KR1020040115454 A KR 1020040115454A KR 20040115454 A KR20040115454 A KR 20040115454A KR 100673113 B1 KR100673113 B1 KR 100673113B1
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South Korea
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forming
film
interlayer insulating
semiconductor device
insulating film
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KR1020040115454A
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Korean (ko)
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KR20060076685A (en
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김남경
박병준
이창구
김현수
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

Abstract

본 발명은 반도체 소자의 형성 방법에 관한 것으로, 반도체 소자의 캐패시터 형성 후 메탈 콘택 플러그를 형성하는 단계에서 발생하는 침상형 굴곡부에 의한 메탈 콘택 플러그 브릿지(Bridge) 현상을 방지하기 위하여, 상기 침상형 굴곡부를 매립하기 위한 ALD 방식을 이용한 절연물질 박막을 증착시킴으로써, 후속의 메탈 라인 형성 시 콘택 플러그가 브릿지되는 현상을 방지하고 반도체 소자의 전기적 특성 및 신뢰성을 향상시킬 수 있는 반도체 소자의 형성 방법에 관한 것이다.The present invention relates to a method of forming a semiconductor device, in order to prevent the metal contact plug bridge (Bridge) phenomenon caused by the needle-shaped bent portion generated in the step of forming a metal contact plug after the formation of the capacitor of the semiconductor device, the needle-shaped bent portion By depositing an insulating material thin film using an ALD method for embedding the metal, the present invention relates to a method of forming a semiconductor device capable of preventing a contact plug from being bridged during subsequent metal line formation and improving electrical characteristics and reliability of the semiconductor device. .

Description

반도체 소자의 형성 방법{METHOD FOR FORMING SEMICONDUCTOR DEVICE}Method of forming a semiconductor device {METHOD FOR FORMING SEMICONDUCTOR DEVICE}

도 1a 및 도 1b는 종래의 기술에 따른 반도체 소자의 형성 방법을 도시한 단면도들.1A and 1B are cross-sectional views illustrating a method of forming a semiconductor device according to the related art.

도 2a 내지 도 2e는 본 발명에 따른 반도체 소자의 형성 방법을 도시한 단면도들.2A to 2E are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

< 도면의 주요 부분에 대한 부호 설명 ><Explanation of Signs of Major Parts of Drawings>

10, 100 : 반도체 기판 15, 115 : 소자분리막10, 100: semiconductor substrate 15, 115: device isolation film

20, 120 : 게이트 25, 125 : 제 1 층간절연막20, 120: gate 25, 125: first interlayer insulating film

30, 130 : 비트라인 35, 135 : 스토리지노드콘택플러그30, 130: bit line 35, 135: storage node contact plug

40, 140 : 제 2 층간절연막 50, 150 : 질화막층40, 140: second interlayer insulating film 50, 150: nitride film layer

60, 160 : 캐패시터 70, 170 : 희생산화막60, 160: capacitor 70, 170: sacrificial oxide film

80, 180 : 제 3 층간절연막 185 : 박막80, 180: third interlayer insulating film 185: thin film

90, 200 : 메탈 콘택 플러그 190 : 산화막90, 200: metal contact plug 190: oxide film

195 : 메탈 콘택홀195: metal contact hole

본 발명은 반도체 소자의 형성 방법에 관한 것으로, 반도체 소자의 캐패시터 형성 후 메탈 콘택 플러그를 형성하는 단계에서 발생하는 침상형 굴곡부에 의한 메탈 콘택 플러그 브릿지(Bridge) 현상을 방지하기 위하여, 캐패시터 상부에 층간절연막을 형성한 후 상기 침상형 굴곡부를 매립하는 박막 및 산화막을 형성하는 반도체 소자의 형성 방법에 관한 것이다.The present invention relates to a method of forming a semiconductor device, in order to prevent the metal contact plug bridge (Bridge) phenomenon caused by the needle-shaped bent portion that occurs in the step of forming the metal contact plug after the formation of the capacitor of the semiconductor device, the interlayer on the capacitor The present invention relates to a method of forming a semiconductor device for forming a thin film and an oxide film which fills the needle-shaped bent portion after forming an insulating film.

반도체 소자의 형성 공정에 있어서, 특히 DRAM(Dynamic Random Acess Memories)소자의 전기적 특성 및 신뢰성 확보를 위해서는 공정을 진행하면서 열처리 단계를 고려해야한다. 그 중에서도 반도체 소자의 메탈 콘택 플러그를 형성하는 공정에서 캐패시터 상부에 층간절연막을 형성하고 이를 평탄화하는 단계에서의 온도에 따라서 캐패시터의 누설 전류와 신뢰성에 대한 마진은 크게 좌우된다. 따라서, 캐패시터 상부에 형성하는 층간절연막을 저온 증착 방식의 PE-TEOS막으로 사용하게 된다. 그러나, PE-TEOS막은 강한 인장피로도(tensile stress)를 갖는 물질로 마찰에 매우 약하기 때문에 CMP를 이용한 평탄화 공정 시 표면에 스크래치(scractch)가 발생하는 문제가 있다. In the process of forming a semiconductor device, in particular, in order to secure electrical characteristics and reliability of a DRAM (Dynamic Random Access Memories) device, a heat treatment step should be considered while the process is performed. Among them, the margin of leakage current and reliability of the capacitor largely depends on the temperature at the step of forming and planarizing the interlayer insulating film on the capacitor in the process of forming the metal contact plug of the semiconductor device. Therefore, the interlayer insulating film formed on the capacitor is used as the low-temperature deposition PE-TEOS film. However, since the PE-TEOS film is a material having a strong tensile stress and very weak to friction, scratches are generated on the surface during the CMP planarization process.

도 1a 및 도 1b는 종래의 기술에 따른 반도체 소자의 형성 방법을 도시한 단면도들이다.1A and 1B are cross-sectional views illustrating a method of forming a semiconductor device according to the related art.

도 1a를 참조하면, 반도체 기판(10) 상에 소자분리막(15)을 형성하고 게이트(20) 및 제 1 층간절연막(125)을 형성한다.Referring to FIG. 1A, an isolation layer 15 is formed on a semiconductor substrate 10, and a gate 20 and a first interlayer insulating layer 125 are formed.

다음에는 제 2층간절연막(40)을 형성한 후 스토리지 노드 콘택 플러그(35)를 형성하고, 캐패시터(60)를 형성하기 위한 질화막층(50) 및 희생산화막(70)을 형성 하게 된다.Next, after forming the second interlayer insulating film 40, the storage node contact plug 35 is formed, and the nitride film layer 50 and the sacrificial oxide film 70 for forming the capacitor 60 are formed.

그 다음에는, 메탈 라인을 형성하기 위한 절연층으로 캐패시터(60) 및 희생산화막(70) 상부에 제 3 층간절연막(80)을 형성하게 된다. 이때, 저온 증착방식을 이용한 PE-TEOS막을 사용하는 것이 바람직하나, PE-TEOS막의 부서지기 쉬운(brittle) 특성 때문에 도면에 도시된 바와 같은 침상형의 굴곡부가 발생하게 된다.Next, the third interlayer insulating film 80 is formed on the capacitor 60 and the sacrificial oxide film 70 as an insulating layer for forming the metal line. At this time, it is preferable to use a PE-TEOS film using a low-temperature deposition method, but because of the brittle characteristics of the PE-TEOS film, the needle-shaped bent portion as shown in the figure is generated.

도 1b를 참조하면, 메탈 라인 형성을 위한 메탈 콘택 플러그(90)를 형성하는 경우 침상형 굴곡부가 형성된 영역에 콘택 홀이 형성되면서 메탈 콘택 플러그(90)가 서로 연결되어 전기적으로 통전이 되는 브릿지 현상이 발생하게 된다. 따라서, 반도체 소자의 전기적 특성 및 신뢰성을 저하시키고 캐패시터의 리프레쉬(refresh) 특성이 열화되는 문제가 발생한다.Referring to FIG. 1B, when the metal contact plug 90 for forming a metal line is formed, a bridge hole in which a metal contact plug 90 is electrically connected to each other while contact holes are formed in an area where a needle-shaped bend is formed is connected to each other. This will occur. Accordingly, there is a problem that the electrical characteristics and reliability of the semiconductor device are lowered and the refresh characteristics of the capacitor deteriorate.

상기 문제점을 해결하기 위하여, 본 발명은 침상형 굴곡부를 매립하기 위한 ALD 방식을 이용한 절연물질 박막을 증착시킴으로써, 후속의 메탈 라인 형성 시 콘택 플러그가 브릿지되는 현상을 방지하고 반도체 소자의 전기적 특성 및 신뢰성을 향상시킬 수 있는 반도체 소자의 형성 방법을 제공하는 것을 그 목적으로 한다.In order to solve the above problems, the present invention by depositing a thin film of the insulating material using the ALD method for embedding the needle-shaped bent portion, thereby preventing the contact plug is bridged during the subsequent metal line formation and electrical characteristics and reliability of the semiconductor device It is an object of the present invention to provide a method for forming a semiconductor device capable of improving the temperature.

상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 형성 방법은,Method for forming a semiconductor device according to the present invention for achieving the above object,

소자분리막, 게이트, 제 1층간절연막, 캐패시터, 제 2층간절연막 및 비트라인이 구비된 반도체 기판 상에, 제 3층간절연막을 형성하는 단계와, Forming a third interlayer insulating film on a semiconductor substrate provided with an isolation layer, a gate, a first interlayer insulating film, a capacitor, a second interlayer insulating film, and a bit line;                     

상기 제 3층간절연막을 CMP 공정으로 연마하는 단계와,Polishing the third interlayer insulating film by a CMP process;

상기 제 3층간절연막 상부에 제 3층간 절연막 표면의 침상형 굴곡부를 매립하는 박막을 형성하는 단계와,Forming a thin film on the third interlayer insulating film to fill the needle-shaped bent portion on the surface of the third interlayer insulating film;

전체 표면 상부에 산화막을 형성하는 단계와,Forming an oxide film over the entire surface,

상기 구조물에 메탈 콘택홀을 형성하는 단계 및Forming a metal contact hole in the structure; and

상기 메탈 콘택홀을 매립하는 메탈 콘택 플러그를 형성하는 단계를 포함하는 것을 특징으로 한다.And forming a metal contact plug to fill the metal contact hole.

이하에서는 첨부한 도면을 참조하여 본 발명에 따른 반도체 소자의 형성 방법을 상세히 설명하기로 한다.Hereinafter, a method of forming a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2e는 본 발명에 따른 반도체 소자의 형성 방법을 도시한 단면도들이다.2A through 2E are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

도 2a를 참조하면, 반도체 기판(100) 상에 소자분리막(115), 게이트(120), 제 1층간절연막(125), 비트라인(130), 제 2 층간절연막(140) 및 스토리지 노드 콘택(135)을 형성한다.Referring to FIG. 2A, an isolation layer 115, a gate 120, a first interlayer insulating layer 125, a bit line 130, a second interlayer insulating layer 140, and a storage node contact may be formed on a semiconductor substrate 100. 135).

도 2b를 참조하면, 도 2a에서 반도체 기판(100) 상에 형성된 하부 구조를 보호하기 위한 질화막층(150)을 형성한 후 캐패시터(160)를 구비하는 희생산화막(170)을 형성한다. 이때, 캐패시터(160)는 HfO3, ZrO3, Al2O3, SrTiO3 또는 (Ba, Sr)TiO3(BST)물질의 각각 및 이들의 혼합으로 형성하는 것이 바람직하다.Referring to FIG. 2B, after forming the nitride layer 150 to protect the lower structure formed on the semiconductor substrate 100 in FIG. 2A, the sacrificial oxide layer 170 including the capacitor 160 is formed. At this time, the capacitor 160 is preferably formed of each of HfO 3 , ZrO 3 , Al 2 O 3 , SrTiO 3 or (Ba, Sr) TiO 3 (BST) materials and mixtures thereof.

다음에는, 상기 구조물 상부에 메탈 라인을 형성하기 위하여 제 3 층간절연 막(180)을 형성하고, 이를 평탄화 하는 공정을 수행한다. 이때, 제 3 층간절연막(180)은 저온 증착 방식을 적용한 PE-TEOS, PE-USG(undoped silicon glass)막 및 SOG(spin on glass)막 중 어느 하나를 사용하여, 1000 ~ 10000Å의 두께로 형성하는 것이 바람직하다. Next, in order to form a metal line on the structure, a third interlayer insulating film 180 is formed and a process of planarizing it is performed. In this case, the third interlayer insulating layer 180 is formed to have a thickness of 1000 to 10000Å using any one of a PE-TEOS, a PE-USG (undoped silicon glass) film, and a spin on glass (SOG) film to which a low temperature deposition method is applied. It is desirable to.

이로 인해, 캐패시터(160)가 열적 손상을 받아 리프레쉬 특성이 열화되는 문제는 해결가능하나, 상기 절연막들의 깨지기 쉬운 특성을 갖고 있기 때문에 CMP 공정을 통한 평탄화 과정에서 도시된 바와 같이 침상형의 굴곡부가 발생하게 된다. As a result, the problem that the capacitor 160 deteriorates the refresh characteristics due to thermal damage is solved. However, since the insulating layers are fragile, needle-shaped bent portions are generated as shown in the planarization process through the CMP process. Done.

도 2c를 참조하면, 제 3 층간절연막(180) 표면의 침상형 굴곡부를 매립하는 박막(185)을 형성한다. 이때, 박막(185)은 알루미나, 산화막 및 질화막 중 어느 하나를 이용하여 형성하는 것이 바람직하다.Referring to FIG. 2C, a thin film 185 may be formed to fill the needle-shaped bent portion of the surface of the third interlayer insulating layer 180. In this case, the thin film 185 is preferably formed using any one of an alumina, an oxide film, and a nitride film.

그 중에서도, 특히 알루미나는 ALD 또는 PE-ALD 방법을 사용하고, 100 ~ 700℃의 온도, 200 ~ 2000W의 전압 및 100mtorr ~ 30Torr의 압력하에서 10 ~ 10000Å의 두께로 형성하는 것이 더 바람직하다. 이때, ALD 방법에 있어서, 반응 소스는 N2O, H2O, H2O2 및 O2 중 선택된 어느 하나의 가스를 이용한다.Especially, it is more preferable to form alumina in thickness of 10-10000 Pa using ALD or PE-ALD method, under the temperature of 100-700 degreeC, the voltage of 200-2000W, and the pressure of 100mtorr-30 Torr. At this time, in the ALD method, the reaction source uses any one gas selected from N 2 O, H 2 O, H 2 O 2 and O 2 .

도 2d를 참조하면, 반도체 기판(100) 전체 표면 상부에 산화막(190)을 형성하고, 상기 구조물에 메탈 콘택홀(195)을 형성한다. 이때, 산화막(190)은 저온 증착 방식을 적용한 PE-TEOS, PE-USG막 및 SOG막 중 어느 하나를 사용하여, 200 ~ 10000Å의 두께로 형성하는 것이 바람직하다.Referring to FIG. 2D, an oxide layer 190 is formed on the entire surface of the semiconductor substrate 100, and a metal contact hole 195 is formed in the structure. At this time, the oxide film 190 is preferably formed to a thickness of 200 ~ 10000 Pa using any one of the PE-TEOS, PE-USG film and SOG film to which the low temperature deposition method is applied.

도 2e를 참조하면, 메탈 콘택홀(195)을 매립하는 메탈 콘택 플러그(200)를 형성하는 단계를 포함하는 것을 특징으로 한다. 이때, 메탈 콘택홀(195)에 베리어 메탈로 TiN, Ti, Ru, Ir, RuOx 및 irOx 중 선택된 어느 하나를 이용하고, 플러그 물질로 TiN, Ti, Ru, Ir, RuOx, irOx, W 및 WN 중 선택된 어느 하나를 이용하는 것이 바람직하다.Referring to FIG. 2E, the method may include forming a metal contact plug 200 to fill the metal contact hole 195. In this case, any one selected from TiN, Ti, Ru, Ir, RuOx, and irOx is used as the barrier metal in the metal contact hole 195, and among the TiN, Ti, Ru, Ir, RuOx, irOx, W, and WN as plug materials. It is preferable to use any one selected.

이상에서 설명한 바와 같이, 본 발명은 침상형 굴곡부를 매립하기 위한 ALD 방식을 이용한 절연물질 박막을 증착시킴으로써, 후속의 메탈 라인 형성 시 콘택 플러그가 브릿지되는 현상을 방지할 수 있다. 따라서, 캐패시터의 리프레쉬 특성을 열화시키지 않으면서도 반도체 소자의 전기적 특성 및 신뢰성을 향상시킬 수 있고, 반도체 소자의 형성 수율을 향상시킬 수 있는 효과를 제공한다.As described above, according to the present invention, by depositing an insulating material thin film using an ALD method for embedding the needle-shaped bent portion, it is possible to prevent the phenomenon that the contact plug is bridged during subsequent metal line formation. Therefore, the electrical characteristics and reliability of the semiconductor device can be improved without degrading the refresh characteristics of the capacitor, and the effect of improving the formation yield of the semiconductor device is provided.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (5)

소자분리막, 게이트, 제 1층간절연막, 캐패시터, 제 2층간절연막 및 비트라인이 구비된 반도체 기판 상에, 제 3층간절연막을 형성하는 단계;Forming a third interlayer insulating film on a semiconductor substrate including a device isolation film, a gate, a first interlayer insulating film, a capacitor, a second interlayer insulating film, and a bit line; 상기 제 3층간절연막을 CMP 공정으로 연마하는 단계;Polishing the third interlayer insulating film by a CMP process; 상기 제 3층간절연막 상부에 제 3층간 절연막 표면의 침상형 굴곡부를 매립하는 박막을 형성하는 단계;Forming a thin film on the third interlayer insulating film to fill the needle-shaped bent portion on the surface of the third interlayer insulating film; 전체 표면 상부에 산화막을 형성하는 단계;Forming an oxide film over the entire surface; 상기 구조물에 메탈 콘택홀을 형성하는 단계; 및Forming a metal contact hole in the structure; And 상기 메탈 콘택홀을 매립하는 메탈 콘택 플러그를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 형성 방법.And forming a metal contact plug to fill the metal contact hole. 제 1 항에 있어서,The method of claim 1, 상기 제 3 층간절연막은 저온 증착 방식을 적용한 PE-TEOS, PE-USG막 및 SOG막 중 어느 하나를 사용하여, 1000 ~ 10000Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 형성 방법.The third interlayer insulating film is formed of a thickness of 1000 ~ 10000Å by using any one of the PE-TEOS, PE-USG film and SOG film to which the low temperature deposition method is applied. 제 1 항에 있어서,The method of claim 1, 상기 박막은 알루미나, 산화막 및 질화막 중 어느 하나를 이용하여 형성하는 것을 특징으로 하는 반도체 소자의 형성 방법.The thin film is formed by using any one of alumina, oxide film and nitride film. 제 3 항에 있어서,The method of claim 3, wherein 상기 알루미나는 ALD 또는 PE-ALD 방법을 사용하고, 반응 소스는 N2O, H2O, H2O2 및 O2 중 선택된 어느 하나의 가스를 이용하면서 100 ~ 700℃의 온도, 200 ~ 2000W의 전압 및 100mtorr ~ 30Torr의 압력 하에서 10 ~ 10000Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 형성 방법.The alumina uses an ALD or PE-ALD method, the reaction source is a temperature of 100 ~ 700 ℃, 200 ~ 2000W using any one selected from N 2 O, H 2 O, H 2 O 2 and O 2 The method of forming a semiconductor device, characterized in that to form a thickness of 10 ~ 10000Å under a voltage of 100mtorr ~ 30Torr. 제 1 항에 있어서,The method of claim 1, 상기 산화막은 저온 증착 방식을 적용한 PE-TEOS, PE-USG막 및 SOG막 중 어느 하나를 사용하여, 200 ~ 10000Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 형성 방법.The oxide film is a method of forming a semiconductor device, characterized in that to form a thickness of 200 ~ 10000Å by using any one of the PE-TEOS, PE-USG film and SOG film to which a low temperature deposition method is applied.
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