KR100672782B1 - Method for fabrication of semiconductor device capable of preventing pattern collapse - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can effectively remove the scum when forming a photoresist pattern, which is an ion implantation mask, while ensuring a process margin, the present invention for forming a conductive pattern on a substrate step; Applying a photoresist on the conductive pattern; Preheating the photoresist; Exposing the photoresist to remain partially after development; Developing the exposed photoresist to form a photoresist pattern; Post-heat treating the photoresist pattern; And it provides a method for manufacturing a semiconductor device comprising the step of performing a decom process to the target to remove the residual photoresist 1500 ~ 2000Å.

In addition, the present invention comprises the steps of selecting a sample wafer to form a photoresist pattern using the method described above; Visually inspecting the overlay of the photoresist pattern through SEM (Scanning Electron Microscopy) imaging to determine defects; Forming a photoresist pattern on the main wafer using the method described above as a result of the defect determination; And determining a defect by measuring critical dimensions of the main wafers through SEM imaging.

Halo ion implantation, scum, discom, photoresist, pattern collapse.

Description

Semiconductor device capable of preventing pattern collapse and manufacturing method thereof {METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING PATTERN COLLAPSE}             

1 is a flow chart showing a halo ion implantation process according to the prior art.

Figure 2 is a planar photograph showing the collapse phenomenon of the halo ion implantation mask.

3 is a cross-sectional view taken along the line a-a 'in FIG. 2;

Figure 4 is a plan view showing a halo ion implantation mask before the in-process discom process according to the prior art.

5 is a flow chart illustrating a halo ion implantation mask formation process including a test.

6 is a flow chart illustrating a halo ion implantation process according to an embodiment of the present invention.

7 is a planar photograph showing that the pattern collapse of the halo ion implantation mask is prevented.

8 is a cross-sectional view taken along the line b-b 'of FIG. 7;

9 is a planar photograph showing a halo ion implantation mask before a transient decom process during a process according to an embodiment of the present invention.                 

10 is a flow chart illustrating a halo ion implantation mask formation process including the test of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the technology of ion implantation of semiconductor devices, and more particularly to a halo ion implantation method.

As semiconductor devices become highly integrated, each cell becomes finer and the internal electric field strength increases. This increase in electric field strength causes a hot-carrier effect in which carriers in the channel region are accelerated and injected into the gate oxide layer in the depletion layer near the drain during device operation. The carrier injected into the gate oxide film creates a level at the interface between the semiconductor substrate and the gate oxide film, thereby changing the threshold voltage (VTH) or lowering the mutual conductance, thereby degrading device characteristics. Therefore, in order to reduce the deterioration of device characteristics due to the hot-carrier effect, a structure in which the drain structure is changed such as a lightly doped drain (LDD) or the like should be used.

In order to increase the impurity concentration of the active region of the substrate after the gate formation and before the LDD formation, in order to prevent the punch-through phenomenon due to the shortening of the channel, fluorine (F), chlorine (Cl) and bromine in the Group 17 element of the periodic table Halo implantation is performed using halogen elements such as (Br), iodine (I), and asatin (At).                         

As the high integration of devices is required, the source / drain formation method of the LDD method also reaches its limit due to the short channel effect. To solve this problem, a halo LDD scheme is introduced.

Meanwhile, in a semiconductor device manufacturing process to which a design rule of 0.1 μm or less is applied, a process such as ion implantation is more difficult than a critical layer forming process.

An example of an ion implantation mask forming process for halo ion implantation is as follows.

After forming a device isolation layer (Isolation) and a gate electrode, which is one of DRAM (Dynamic Random Access Memory) semiconductor device patterns, bromine (Br) or the like is implanted in order to provide electrical characteristics between the fine patterns.

When a design rule of 0.1 μm is applied, a space between the gate electrodes is secured at least about 60 nm. At this time, since the vertical height (Height) of the patterned gate electrode is about 2000 게이트, the height of the gate electrode has a very high step compared to the width of the space.

The photolithography process for forming a halo ion implantation mask uses an exposure apparatus one step lower than the exposure apparatus for forming a gate electrode pattern, which is a critical process on such a step. This is an essential process condition for reducing manufacturing costs. In forming a halo ion implantation mask, the photoresist positioned between the gate electrode patterns requiring ion implantation should be removed through development, and the photoresist should be covered between the gate electrode patterns to which ion implantation should be blocked.

However, due to the above step, light is not transmitted in the space (bone) between the deep gate electrodes and remains in the form of a scum even after development, which remains as a barrier in the halo ion implantation process. Acts as.

Although the quality of the halo implantation mask patterning may vary depending on the exposure method in the photolithography process, the difference is largely dependent on the topology of the mask pattern of the previous process already formed on the wafer before forming the halo implantation mask. Can be represented.

For example, the gate electrode pattern is patterned with a line width of about 90 nm, and the height of the gate electrode pattern is also formed with a deep step of about 200 mW to 3000 mW. The halo ion implantation mask formation at these pattern steps can be quite difficult. Furthermore, when the space between the gate electrode pattern and the pattern is 90 nm or less, and when the gate spacer is formed on the sidewall of the gate electrode, the space between the gate electrode pattern is 60 nm or less. In some cases, due to non-uniform deposition of the insulating film for spacers, a place where a space is 30 nm or less may occur. In such a place, the photoresist may remain as scum, thus impeding the halo ion implantation process.

The photoresist located in the space between the gate electrodes is outside the depth of focus (hereinafter referred to as DOF) of the reduced exposure apparatus, so that light is not transferred to the photoresist with sufficient energy during exposure and development. After remaining as scum, it becomes an obstacle for halo ion implantation.                         

As described above, a process for removing the remaining scum, that is, a descum is additionally performed, but even in such a discom process, it is difficult to remove in some cases. The thickness of the photoresist, which is the remaining ion implantation mask, may become thin and cause problems.

1 is a flow chart illustrating a halo ion implantation process according to the prior art, and looks at a conventional halo ion implantation process with reference to this.

First, the wafer is cleaned before the photoresist is applied (S101). The cleaning consists of O ₂ cleaning and wetting. By applying a high temperature O ₂ plasma treatment to the foreign matter or silicon oxide film present in the wafer, it is possible to smoothly apply the photoresist.

Here, the wafer is a sample wafer or main wafer for a halo ion implantation test, and a gate electrode is formed.

In particular, the O ₂ plasma treatment is intended to facilitate filling of photoresist deep to a wafer having a deep stepped topology, or to improve flow characteristics.

Subsequently, after applying the photoresist (S102), a pre-baking process is performed before exposure (S103). The preheating is carried out in a conventional manner for 90 seconds at a temperature of 100 ° C. The preheating process is carried out to evaporate the volatile components present in the photoresist.                         

Subsequently, an exposure process using a reticle is performed to induce a photocrosslinking reaction in the photoresist (S104). Therefore, in the case of a positive type photoresist, a photocrosslinking reaction occurs in the exposed portion.

At this time, the exposure energy is transferred to the photoresist positioned in the valley between the gate electrodes by performing over-exposure.

Subsequently, the development process is performed (S105) to remove the photoresist in which the photocrosslinking reaction has occurred, thereby forming a photoresist pattern which is an ion implantation mask for halo ion implantation.

Subsequently, a post-baking, that is, a hard baking process is performed to harden the ion implantation mask (S106). The post heat treatment is carried out in a conventional manner at a temperature of 110 ° C. for 90 seconds. The post heat treatment process is performed to cure the photoresist pattern to serve as an etching barrier in the subsequent etching process.

Subsequently, an O ₂ plasma treatment process is performed with a shallow discom target to remove the captive resist remaining in the form of scum at a portion having a deep step (S107). The descom process is performed in about 13 seconds with a target to which a photoresist of about 600 microseconds is etched.

Next, a halo ion implantation process is performed using the photoresist pattern as an ion implantation mask (S108).

Scum removal of the above-described conventional halo-ion implantation photoresist pattern that is, subjected to excessive exposure process during exposure to the discharge compartment and then to avoid possible scum, scum, etc., which in part retained as is the O ₂ plasma after the heat treatment Removed from the descom process for several seconds.

However, when the photoresist pattern forming process is performed with a wafer in which the valley step of the gate electrode pattern is too large on the wafer and the gate electrode pattern and the like are formed in a non-ideal form, problems due to scum residue still occur.

In particular, since such problems do not usually appear and occur suddenly or very rarely and irregularly, solving the problem due to scum residue is one of the very important tasks for improving the yield.

FIG. 2 is a planar photograph showing the collapse of the halo ion implantation mask, and it can be seen that the ion implantation mask is broken at the 'X' portion.

3 is a cross-sectional view taken along the line a-a 'of FIG. 2.

2 and 3, an isolation layer 301 is formed on the substrate 300. The device isolation layer 301 divides the active region ACT and the device isolation region. The gate electrode 302 is formed on the substrate 300. A photoresist pattern 303 is formed between the gate electrodes 302, and the photoresist pattern 303 protrudes above the gate electrode 302 as shown in 304. Due to the scum remaining when the photoresist pattern 303 is formed, the adhesive property of the photoresist pattern 303 becomes poor, resulting in a pattern collapse phenomenon such as 'X'.                         

4 is a planar photograph illustrating a halo ion implantation mask before a descom process during the process according to the prior art.

Referring to FIG. 4, scum does not occur in most regions, but scum remains in the vulnerable region, such as 'Y'.

Scum that remains like 'Y' in vulnerable areas is difficult to completely remove with a shallow target decom process.

FIG. 5 is a flowchart illustrating a halo ion implantation mask forming process including a test, and looks at a conventional halo ion implantation mask forming process with reference to the flowchart.

First, one sampling wafer for C-halo ion implantation is selected and a halo ion implantation mask forming process is performed (S501).

Specifically, the wafer cleaning process, the application of the photoresist, the pre-heat treatment process, the exposure, the development, the post-heat treatment and the decom process are performed. At this time, the above-described recipe of FIG. 1 is applied to each process step.

Subsequently, a critical dimension (hereinafter referred to as CD) of an ion implantation mask formed on the sampled wafer is measured by SEM (Sacnning Electron Microscopy) imaging (S502).

At this time, the overlay overlap between the ion implantation mask and the gate is measured using X and Y coordinates. As a result of the measurement, if the CD of the ion implantation mask for the sampling wafer is defective, the recipe is changed and the 'S501' step is repeated.

If the measurement result is satisfactory, the halo ion implantation mask forming process for the main wafer is performed (S503).

At this time, the wafer cleaning process as in step S501, the application of the photoresist, the pre-heat treatment process, the exposure, the development, the post-heat treatment, and the decom process are performed.

Subsequently, the CD of the ion implantation mask formed on the main wafer is measured by SEM imaging (S504).

As a result of the measurement, if the CD of the ion implantation mask for the main wafer is defective, the recipe is changed and the 'S501' step is repeated.

If satisfactory, the ion implantation mask forming process is completed and halo ion implantation is performed using the ion implantation mask.

The overlay measurement of the ion implantation mask and the gate electrode in steps S502 and S504 monitors whether the degree of alignment of the ion implantation mask is aligned on the gate electrode.

 CD measurement through SEM imaging determines whether the pattern of the ion implantation mask is about 0 nm to 60 nm at the top of the gate electrode. It is preferable that the ion implantation mask located at the top of the gate electrode is removed so as to be removed in a subsequent decom process to prevent a pattern collapse phenomenon.

In the halo ion implantation mask formation process including the conventional test as described above, the exposure energy margin (Exposure Latitude; hereinafter referred to as E / L) is about 4 mJ when the exposure is performed using the KrF exposure source, and the DOF of the reduced exposure apparatus is The process margin is small because it is within 0.1 μm. Therefore, it is difficult to secure process margins during ion implantation.

The present invention has been proposed to solve the above problems of the prior art, while effectively removing scum when forming a photoresist pattern as an ion implantation mask, It is an object of the present invention to provide a method for manufacturing a semiconductor device which can secure a margin.

The present invention to achieve the above object, forming a conductive pattern on a substrate; Applying a photoresist on the conductive pattern; Preheating the photoresist; Exposing the photoresist to remain partially after development; Developing the exposed photoresist to form a photoresist pattern; Post-heat treating the photoresist pattern; And it provides a method for manufacturing a semiconductor device comprising the step of performing a decom process to the target to remove the residual photoresist 1500 ~ 2000Å.

In addition, to achieve the above object, the present invention comprises the steps of selecting a sample wafer to form a photoresist pattern using the method described above; Visually inspecting the overlay of the photoresist pattern through SEM (Scanning Electron Microscopy) imaging to determine defects; Forming a photoresist pattern on the main wafer using the method described above as a result of the defect determination; And determining a defect by measuring critical dimensions of the main wafers through SEM imaging.

In the conventional case, excessive exposure was performed when forming a photoresist pattern, which is an ion implantation mask, to minimize scum generation, and subsequent scum processes, that is, an O ₂ plasma treatment process, were performed with a thin target to remove residual scum.

However, according to the present invention, when forming a photoresist pattern, which is an ion implantation mask, underexposure is performed, and subsequent scum processes, that is, an O ₂ plasma treatment process, are performed with excessive targets to remove residual scum.

Through this, the problem of the collapse of the photoresist pattern generated after the O ₂ plasma treatment is also solved, and halo ion implantation using bromine or the like is smoothly performed.

In addition, the margin of EL and DOF can be increased to increase the process margin.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

FIG. 6 is a flowchart illustrating a halo ion implantation process according to an embodiment of the present invention, and looks at the halo ion implantation process of the present invention with reference to the flowchart.                     

First, the wafer is cleaned before the photoresist is applied (S601). The cleaning consists of O ₂ cleaning and wetting. By applying a high temperature O ₂ plasma treatment to the foreign matter or silicon oxide film present in the wafer, it is possible to smoothly apply the photoresist.

Here, the wafer is a sample wafer or main wafer for a halo ion implantation test, and a gate electrode is formed.

In particular, the O ₂ plasma treatment is preferably performed for 5 to 10 seconds in order to facilitate filling of the photoresist to a deep position or to improve flow characteristics in a wafer having a deep stepped topology.

Next, a photoresist is applied (S602). The photoresist is preferably applied so as to have a thickness of about 1000 GPa to 2000 GPa above the gate electrode.

Before the exposure is subjected to a pre-heat treatment step (S603). The preheating is carried out in a conventional manner for 90 seconds to 150 seconds at a temperature of 90 ℃ to 100 ℃. The pretreatment process volatilizes a solvent, etc., present in the photoresist, and is performed to increase gap-fill characteristics to the valleys between the gate electrodes.

Subsequently, an exposure process using a reticle is performed to induce a photocrosslinking reaction in the photoresist (S604). Therefore, in the case of a positive type photoresist, a photocrosslinking reaction occurs in the exposed portion.

At this time, under-exposure is performed so that the photoresist on the gate electrode is exposed for sufficient pattern formation, while the valley between the gate electrodes is not completely exposed and is less than 100 μs even after development. , 0Å-100Å).

Subsequently, the development process is performed (S605) to remove the photoresist in which the photocrosslinking reaction has occurred, thereby forming a photoresist pattern which is an ion implantation mask for halo ion implantation.

Subsequently, a post-heat treatment, that is, a hard baking process is performed to harden the ion implantation mask (S606). After the heat treatment is carried out in a conventional manner for 90 seconds to 150 seconds at a temperature of 140 ℃ to 150 ℃. A conventional post-heat treatment process is performed to cure the photoresist pattern to serve as an etch barrier in the subsequent etching process. In the present invention, not only this purpose but also the remaining photoresist may flow from a high temperature to a deep bottom. There is also a purpose of resist flow.

On the other hand, it may be carried out for 60 seconds to 90 seconds at a temperature of 180 ℃ to 200 ℃ to reduce the post-heat treatment process time.

Subsequently, an O ₂ plasma treatment process is performed on the thick disc system target to remove the captive resist remaining in the form of scum at the portion having a deep step (S607). In the conventional discom process, the photoresist of about 600 GPa is etched in about 13 seconds, but in the present invention, the photoresist of about 1500 GPa to 2000 GP is removed for 30 seconds to 50 seconds. That is, the disc process is about three times stronger than in the prior art.

Next, a halo ion implantation process is performed using the photoresist pattern as an ion implantation mask (S608).

In the halo ion implantation process according to the embodiment of the present invention, an underexposure process is performed during the exposure of the photoresist so that some scums remain, and the remaining scums are then subjected to a post-heat treatment, followed by a thick target O ₂ plasma. Removed completely in the descom process using.

7 is a planar photograph showing that the pattern collapse of the halo ion implantation mask is prevented, and it can be seen that the ion implantation mask is not collapsed.

8 is a cross-sectional view taken along the line b-b 'of FIG. 7.

8 and 7, an isolation layer 801 is formed on the substrate 800. The device isolation layer 801 divides the active region ACT and the device isolation region. The gate electrode 802 is formed on the substrate 800. The photoresist pattern 803 is formed between the gate electrodes 802. The protruding portion of the photoresist pattern 803 as '804' is surrounded by the gate electrode 802, so that a pattern collapse occurs. Since it is protected by the gate electrode 802, defects are prevented in the subsequent halo ion implantation process.

FIG. 9 is a planar photograph illustrating a halo ion implantation mask before a transient decom process during a process according to an embodiment of the present invention.

Referring to FIG. 9, it can be seen that after forming the halo ion implantation mask, scum partially covers the interlayer dielectric layer pattern and is positioned at the centers of the gate electrodes of both the halo ion implantation masks.

Reference numeral 'P' denotes an area in which the pattern is not opened by the scum of the photoresist, and reference numeral 'Q' denotes an area in which the interlayer insulating film pattern is opened.

This scum is almost eliminated by the subsequent descum process of excessive targets.

FIG. 10 is a flowchart illustrating a halo ion implantation mask forming process including a test of the present invention, and looks at the halo ion implantation mask forming process of the present invention with reference to the flowchart.

First, one sampling wafer for C-halo ion implantation is selected and a halo ion implantation mask forming process is performed (S110).

Specifically, the wafer cleaning process, the application of the photoresist, the pre-heat treatment process, the exposure, the development, the post-heat treatment and the decom process are performed. At this time, the above-described recipe of FIG. 6 is applied to each process step.

Next, a mask pattern visual inspection of the sampled wafer is performed (S111).

In other words. CD measurement of the ion implantation mask formed on the wafer sampled by SEM imaging is omitted, and the pattern overlapping degree of the halo ion implantation mask is measured by selecting one of the X and Y directions. At this time, only the pattern overlay matching the direction of the bottom gate electrode is measured and one is ignored even if it is out of specification.

At this time, by checking the profile of the mask pattern and whether both ends are located in the center of the gate electrode pattern, it is possible to replace the overlay measurement process.                     

Therefore, it is preferable to perform the exposure process so that about half of the interlayer insulating film pattern is opened in the SEM photograph of FIG. 9.

When checking the overlay by CD SEM, the degree of overlay between the halo ion implantation mask and the gate electrode pattern is checked. Specifically, when the center of the halo ion implantation mask pattern positioned on the top of the gate electrode coincides with the center of two gate electrode patterns on both sides, it is a good case that the state does not deviate from 1/2 of the line width of the halo ion implantation mask.

As a result of the measurement, if the CD of the ion implantation mask for the sampling wafer is defective, the recipe is changed and the 'S110' step is repeated.

If the measurement result is satisfactory, the halo ion implantation mask forming process for the main wafer is performed (S112).

In this case, the wafer cleaning process, the photoresist coating, the pre-heat treatment process, the exposure, the development, the post-heat treatment, and the decom process are performed as in the step S110.

Subsequently, the CD of the ion implantation mask formed on the main wafer is measured by SEM imaging (S113).

As a result of the measurement, if the CD of the ion implantation mask for the main wafer is bad, the recipe is changed and the step 'S110' is repeated.

If satisfactory, the ion implantation mask forming process is completed and halo ion implantation is performed using the ion implantation mask.

In the conventional case, when the overlay measurement of the ion implantation mask and the gate electrode in the step 'S110' is observed, the degree of alignment of the ion implantation mask is observed on the upper portion of the gate electrode. It was measured whether or not about 0nm to 60nm at the top of the gate electrode.

However, the present invention shows that although the halo ion implantation mask is aligned at the center of the two gate electrode patterns in the overlay measurement process with the gate electrode of the halo ion implantation mask which selects one of X and Y, the CD SEM visual inspection Check and do not measure with a separate overlay measuring device. Omission of the overlay measurement process can reduce the TAT (Turn Around Time).

According to the present invention made as described above, the conventional E / L, which was about 4 mJ, can be increased to about 10 mJ, and the DOF of the reduced exposure apparatus can be increased from 0.1 m to 0.5 m, thereby improving the process margin.

In the conventional halo ion implantation mask, scum remained in the valleys between the gate electrodes when incomplete wafers were worn. The present invention has a sufficient margin and can be easily removed by a transient descom process.

Overlay measurement is performed simultaneously with visual inspection by CD SEM, so it is possible to reduce cost and shorten process TAT by not using expensive overlay measuring device.

Since the photoresist pattern standing on the gate electrode is formed within the depth of half of the inside of the gate electrode pattern valley, a halo ion implantation mask is formed so that even if the photoresist pattern collapse occurs, it does not act as a defect, but a stable halo ion implantation process. It was found through the example roll that it can proceed.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above example, a halo ion implantation mask and a halo ion implantation process using the same are exemplified, but it can be applied to all masks and all ion implantation processes for ion implantation.

The present invention as described above, while effectively removing scum when forming a photoresist pattern as an ion implantation mask, can secure a process margin, thereby improving the yield of a semiconductor device.

In addition, the process time and cost can be reduced, thereby increasing the price competitiveness and productivity.

Claims (12)

Forming a conductive pattern on the substrate; Applying a photoresist on the conductive pattern; Preheating the photoresist; Exposing the photoresist to remain partially after development; Developing the exposed photoresist to form a photoresist pattern; Post-heat treating the photoresist pattern; And Performing a decom process to a target from which 1500 포토 to 2000 Å of residual photoresist is removed; Semiconductor device manufacturing method comprising a. The method of claim 1, In the exposing step, the photoresist is left to 0Å to 100Å after development. The method of claim 1, In the step of performing the discom process, a semiconductor device manufacturing method characterized in that using the O ₂ plasma. The method of claim 1, The heat treatment after the semiconductor device manufacturing method, characterized in that carried out for 90 seconds to 150 seconds at a temperature of 140 ℃ to 150 ℃. The method of claim 1, The heat treatment after the semiconductor device manufacturing method, characterized in that carried out for 60 seconds to 90 seconds at a temperature of 180 ℃ to 200 ℃. The method of claim 1, The pre-heating step is a semiconductor device manufacturing method, characterized in that carried out for 90 seconds to 150 seconds at a temperature of 90 ℃ to 100 ℃. The method of claim 1, The photoresist is applied in a thickness of 1000kPa to 2000kPa semiconductor device manufacturing method. The method of claim 1, Before applying the photoresist, And cleaning the substrate using O ₂ plasma for 5 seconds to 10 seconds. The method of claim 1, After the step of performing the discom process, And implanting impurities into the substrate on the side surface of the conductive pattern by using the photoresist pattern. Selecting a sample wafer to form a photoresist pattern using the method of any one of claims 1 to 8; Visually inspecting the overlay of the photoresist pattern through SEM (Scanning Electron Microscopy) imaging to determine defects; Forming a photoresist pattern on the main wafer using the method of any one of claims 1 to 8 as a result of the defect determination; And Determining a defect by measuring the critical dimension for the main wafers through SEM imaging Semiconductor device manufacturing method comprising a. The method of claim 10, In the step of visually inspecting the overlay of the photoresist pattern, only the alignment of the conductive pattern and the photoresist pattern with the naked eye, and the critical dimension measurement is not carried out. The method of claim 10 or 11, In the step of visually inspecting the overlay of the photoresist pattern, And visually confirming only the alignment of the conductive pattern and the photoresist pattern and not measuring the critical dimension.

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