KR100659581B1 - A method for crystallizing silicon and a thin film transistor manufactured by the crystallizing method and a method for manufacturing the same - Google Patents

Abstract

A method for crystallizing silicon, a thin film transistor manufactured by the same, and its manufacturing method are provided to improve electron mobility of the thin film transistor by metal-catalyst-induced crystallization. A crystalline filter(120) is formed on a substrate(100). A metal catalyst layer(130) is formed in the crystalline filter. A resist pattern having holes is formed on the substrate. The substrate is patterned along the resist pattern to form the crystalline filter of a well structure. An amorphous silicon layer(140) is deposited on the whole substrate including the crystalline filter. The substrate is thermally processed to crystallize the amorphous silicon layer by metal-catalyst-induced crystallization, so that electron mobility of a thin film transistor is improved.

Description

A method for crystallizing silicon and a thin film transistor manufactured by the crystallizing method and a method for manufacturing the same

1A to 1E are side cross-sectional views illustrating a crystallization method according to an embodiment of the present invention.

2 is a side cross-sectional view showing silicon crystallized according to the crystallization method of the present invention.

3A to 3G are side cross-sectional views illustrating a crystallization method according to another embodiment of the present invention.

4A to 4E are views illustrating a manufacturing process of a thin film transistor using a semiconductor layer grown by the crystallization method according to the present invention.

* Reference numerals for key parts *

100, 200, 300, 401: substrate 130, 230, 231, 330: metal catalyst

120, 220, 221, 310, 321, 410, 411, 412: grain filter (etch groove)

140, 240, 340, 341: amorphous silicon

150a, 150b, 250a, 250b, 260a, 260b, 350a, 350b: grains

170, 270, 370, 420a, 420b: interface 430: active layer

440: gate insulating film 450: gate electrode

The present invention relates to a silicon crystallization method and a thin film transistor manufactured by the crystallization method and a method for manufacturing the same, and in particular, a silicon crystallization method for forming a high quality polysilicon thin film using a metal catalyst induced crystallization and a poly formed by the crystallization method The present invention relates to a thin film transistor manufactured using silicon and a method of manufacturing the same.

In general, to form a poly-silicon thin film, pure amorphous silicon may be used in various methods, such as plasma enhanced chemical vapor deposition (PECVD) and low pressure chemical vapor deposition (LPCVD). deposition on a substrate, or the like. The deposited amorphous silicon may be subjected to laser annealing (ELA), solid phase crystallization (SPC), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), and the like. To crystallize.

Among the crystallization methods, the laser heat treatment method (ELA) is a polysilicon forming method that is currently widely studied. The polysilicon is formed by supplying laser energy to a substrate on which amorphous silicon is deposited to make amorphous silicon in a molten state and then forming polysilicon by cooling. Way. However, the laser heat treatment method has disadvantages of using expensive equipment, and since the surface of silicon becomes rough after heat treatment, electron mobility is lowered due to scattering due to an irregular potential barrier when electrons move.

The solid phase crystallization method (SPC) is a method of obtaining polysilicon by depositing amorphous silicon on a glass substrate or a quartz substrate capable of withstanding high temperature of 600 ° C. or higher, and then performing heat treatment at a high temperature for a long time. However, the solid phase crystallization method is not easy to obtain the desired polysilicon shape at a high temperature for a long time, and the electron mobility is not high because the crystal grain growth direction is irregular and the grain size of the polysilicon is not large and nonuniform. .

Accordingly, compared with ELA or SPC having such a problem, a metal induction crystallization method or a metal induction side crystallization method using a low process temperature and a low process cost is used. The metal induced crystallization method (MIC) may use a glass substrate by depositing a metal on amorphous silicon deposited on a substrate and then crystallizing the polysilicon. The metal induced side crystallization method (MILC) is a method of forming an oxide pattern in an active region and then depositing a metal to form polysilicon, which improves carrier mobility because silicon crystals grow laterally from the bottom of the oxide pattern. can do. However, MIC and MILC can form polysilicon using low-cost, large-area glass substrates, but the reliability of polysilicon film quality is somewhat higher because metal residues are more likely to be present in the network inside the polysilicon. There is a problem that can fall. In addition, in the case of using the metal-induced crystallization method described above, metal residues are present in the silicon, thereby deteriorating the characteristics of the polysilicon thin film, which causes leakage current when the thin film transistor is formed using the thin film transistor. Because of the presence of a metal catalyst on the substrate, crystals grow in various directions around the metal catalyst when silicon is crystallized, and when grains meet different crystals grown in different directions, grain boundaries are formed. It has a disadvantage in that the electron mobility is lowered.

Therefore, in recent years, methods for improving existing crystallization methods have been tried. Particularly, in order to solve the nonuniformity of grain growth direction, which is a disadvantage of MILC, a grain filter or the like has been proposed. By forming a passage-type grain filter having a predetermined width so that the grains pass between the active layer in which the metal catalyst is formed in the thin film transistor and the active layer in which the channel of the element is formed, only the grains passing through the filter are induced to grow to the channel region. However, this method has a disadvantage in that workability is inferior because an additional layout area for crystal growth is required.

In recent years, a micro-Czochralski method for inserting a grain filter into a substrate has been proposed. The micro Czochralski method forms a well structure on a substrate, deposits amorphous silicon on the substrate, and then crystallizes through laser heat treatment. While the upper silicon layer melts all by laser heat treatment, the laser energy is not sufficiently delivered to the silicon in the deep well, leaving the micro crystal nucleus, and growing crystal grains from the nucleus when the upper silicon causes a phase change back to the solid state. This is how you do it. However, the use of the above method requires expensive equipment, and thus has the disadvantage of deviating from the purpose of the recent crystallization method of crystallizing amorphous silicon by using it in a low temperature process without using expensive equipment.

Accordingly, the present invention is an invention designed to solve the above-mentioned problems, the object of the present invention is that the metal catalyst residue does not affect the active layer, the electron mobility by growing the crystal growth direction by the metal catalyst in one direction only To provide a silicon crystallization method and a thin film transistor manufactured by using the crystallization method and a method for manufacturing the same.

In addition, another object of the present invention is a crystallization method for crystallizing amorphous silicon using a metal catalyst at a low temperature so as to be used in a display device or a logic switching element that can implement a three-dimensional integrated circuit, and a thin film transistor manufactured by the crystallization method and It is to provide a manufacturing method.

Still another object of the present invention is to grow a single grain at a desired position, thereby preventing carrier collision occurring at the interface of the grain, thereby improving the electron mobility and the thin film prepared by the crystallization method It is to provide a transistor and a method of manufacturing the same.

According to an aspect of the present invention, to achieve the above object, the present method for crystallizing silicon comprises forming a grain filter on a substrate; Forming a metal catalyst layer on the grain filter; Depositing an amorphous silicon layer over the substrate including the grain filter; And heat treating the substrate to crystallize the amorphous silicon layer.

Preferably, the forming of the grain filter may include forming a resist pattern having a hole formed on the substrate, and patterning the substrate according to the resist pattern to form a crystal filter having a well structure having a predetermined depth and width in the substrate. Forming a step. In the forming of the grain filter, the substrate is activated ion etched according to the resist pattern. The well structure has a cross-sectional width of 0.5 μm or less and a depth of 0.1 to 1 μm.

The forming of the metal catalyst layer on the grain filter includes forming the metal catalyst layer on the bottom of the grain filter of the well structure and on the resist pattern, and removing at least one region of the resist pattern. Forming the metal catalyst layer is deposited using one of sputtering, thermal evaporation, and E-beam deposition. The metal catalyst layer uses any one of gold, silver, aluminum, tin, indium, nickel, molybdenum, palladium, titanium, copper, iron, and chromium. The metal catalyst layer is deposited within a range of 200 kPa.

Crystallizing the amorphous silicon layer may include: growing the amorphous silicon layer in the well structure to the upper part of the well structure by the metal catalyst; and growing the amorphous silicon layer on the substrate laterally by the upwardly grown grains. And stopping grain growth when the laterally grown grains form an interface with other grains.

In addition, according to another aspect of the present invention, the thin film transistor includes a substrate having a well structure; An active layer having a grain structure growing from the bottom of the well structure to the top by a metal catalyst provided in the well structure; A gate insulating layer formed on the active layer; A gate electrode formed on the gate insulating layer; And a source / drain electrode electrically connected to one region of the active layer.

According to another aspect of the invention, the method of manufacturing the thin film transistor includes the steps of forming a well structure recessed to a predetermined depth on the substrate; Forming a metal catalyst layer on the well structure; Depositing an amorphous silicon layer over the substrate including the well structure; Heat treating the substrate to crystallize the amorphous silicon layer; Patterning the crystallized amorphous silicon layer to form an active layer including a channel region; Forming a gate insulating film on the active layer region, and forming a gate electrode on the gate insulating film; Implanting impurities into the active layer region to form a source / drain region; And forming a source / drain electrode in electrical contact with the source / drain region.

Preferably, the forming of the well structure includes forming a resist pattern having a hole formed on the substrate, and patterning the substrate according to the resist pattern to form the well structure to have a predetermined depth and width in the substrate. It includes a step. The patterning of the substrate according to the resist pattern uses an activated ion etching process.

The forming of the metal catalyst layer may include forming the metal catalyst layer on the lower portion of the well structure and on the resist pattern, and removing at least one region of the resist pattern. The well structure has a cross-sectional width of 0.5 μm or less and a depth of 0.1-1 μm. Forming the metal catalyst layer is deposited using one of sputtering, thermal evaporation and E-beam deposition. The metal catalyst layer uses any one of gold, silver, aluminum, tin, indium, nickel, molybdenum, palladium, titanium, copper, iron, and chromium. The metal catalyst layer is formed in the range of 200 kPa or less.

Crystallizing the amorphous silicon layer may include growing an amorphous silicon layer in the well structure to the upper part of the well structure by the metal catalyst, and growing the amorphous silicon layer on the substrate laterally by the grown crystal grains. And stopping grain growth if the laterally grown grains form an interface with other grains. In the forming of the active layer, the grain boundary is not positioned in a region where the channel region and the gate electrode overlap.

Hereinafter, a crystallization method according to the present invention, a thin film transistor using the crystallization method, and a manufacturing method thereof will be described in detail with reference to the accompanying drawings.

1A to 1E are side cross-sectional views illustrating a crystallization method according to an embodiment of the present invention. In order to crystallize the silicon layer according to the present invention, first, the substrate 100 is prepared. The substrate 100 may be formed using an insulating material such as plastic or glass, and the type of the substrate 100 may be appropriately selected according to the characteristics of the semiconductor device to be manufactured.

As shown in FIG. 1A, a resist pattern 110 is formed on the substrate 100 in which a through hole 111 having a predetermined width is formed using lithography. Next, referring to FIG. 1B, a crystal filter 120 having a narrow well structure is formed on the substrate 100. The grain filter 120 recessed in the substrate 100 is formed by a dry etching process using the resist pattern 110 formed on the substrate 100 as a mask. In the present embodiment, the plasma using the CF _x gas series is used. Use etching. The grain filter 120 is to be used in the subsequent silicon crystallization process, and serves as a filter during the crystal growth of silicon. The grain filter 120 may be formed in an appropriate shape according to a user's request, but in order to have the crystal grains induced by the metal catalyst (not shown) to be deposited on the bottom of the grain filter 120 have one crystal direction. The smaller the width, the better. Preferably, the width is 500 nm or less and 100 nm or less.

Next, referring to FIG. 1C, the metal catalyst 130 is formed on the resist pattern 110 formed on the substrate 100. The metal catalyst 130 is formed on the entire surface of the substrate 100 and is also formed on the bottom surface of the grain filter 120. However, the metal catalyst 130 may not be deposited on the sidewall surface of the grain filter 120 having a narrow and deep well structure. This is to facilitate grain filtering in later silicon crystallization, ie to induce crystal growth with the same orientation. In this case, the metal catalyst 130 is made of metals such as gold (Au), silver (Ag), aluminum (Al), tin (Sb), indium (In), nickel (Ni), molybdenum (Mo), and palladium (Pd). And metals forming silicides such as titanium (Ti), copper (Cu), iron (Fe), chromium (cr) and the like. The metal catalyst 130 is formed in a thickness range of 200 kPa or less.

In the next step, as shown in FIG. 1D, the resist pattern 110 formed on the substrate 100 is removed. The resist pattern 110 formed on the substrate 100 may be removed by a lift-off process, thereby removing the metal catalyst 130 formed on the upper surface of the resist pattern 110. Amorphous silicon 140 is deposited on the substrate 100 from which the resist pattern 110 is removed. Amorphous silicon 140 may be deposited differently depending on the characteristics of the device to be manufactured, in this embodiment is deposited to about 500 ~ 1000Å. Amorphous silicon is deposited by chemical vapor deposition such as LPCVD or PECVD, and when the deposition is performed, the step coverage should be well formed to prevent voids in the etch groove 130, which is a grain filter having a narrow and long well structure.

When depositing amorphous silicon 140, when using LPCVD and PECVD, it must be deposited at 550 ° C. or lower using SiH 4 or Si 2 H 6 gas. This is to prevent solid phase crystallization from occurring during deposition. In the case of using PECVD, dehydrogenation heat treatment may be required so that defects do not occur in the silicon thin film due to hydrogen gas ejection during heat treatment for later crystallization. At this time, the amorphous silicon 140 is deposited to a thickness of 200 ~ 2000Å.

In the next step, referring to FIG. 1E, the substrate 100 is heat-treated so that the amorphous silicon 140 is crystallized. At this time, the heat treatment uses a rapid heat treatment or a quartz high temperature furnace, and the temperature applied to the substrate during the heat treatment uses a temperature range in which the amorphous silicon 140 can be crystallized by the metal catalyst 130, but does not cause self-solid crystallization. Use a temperature range (ie, between 450 and 600 ° C.). Of course, a method of applying a voltage to the amorphous silicon 140 deposited at the same time using a rapid heat treatment or a quartz high temperature furnace may be used, which is to shorten the crystallization time of the amorphous silicon 140. In the case of crystallization by a method of applying a voltage, a voltage of about 10 to 500 V / cm is applied to the amorphous silicon 140, and a time range of about 10 to 300 minutes is used.

Through such various heat treatment methods, the amorphous silicon 140 is crystallized. In the case of the amorphous silicon 140 filled in the grain filter 120 having a well structure, the amorphous silicon 140 is surrounded by an insulating material to receive more thermal effects locally. Thus, crystallization by metal-silicide can be induced at a lower temperature than conventional metal catalyst induced crystallization. In the case of laser heat treatment, only the upper amorphous silicon is directly exposed to the laser to melt and crystallize as it solidifies again. However, in the case of rapid heat treatment or a quartz high temperature furnace, the temperature of the sample itself rises as a whole. The amorphous silicon of may be allowed to crystallize first. Referring to FIG. 1E, as the grains grow from the bottom of the grain filter 120 to the top, only the grains 150a having the vertical direction among the several grains formed at the same time may grow to the upper silicon layer 140. That is, since the grains grown in the other direction are trapped in the well and can no longer grow, the narrow and deep grain filter 120 structure serves as a filter. The grains 150a grown to the top are grown to the left and right 150b along the horizontal direction of the amorphous silicon 140. Crystal grains 150b grown from side to side continue to grow until they encounter grains for constituting other elements.

2 is a side cross-sectional view showing silicon crystallized according to the crystallization method of the present invention. Referring to FIG. 2, in the present embodiment, a pair of well-formed grain filters 220 and 221 are formed on the substrate 200, and metal catalysts 230 and 231 are deposited on the grain filters 220 and 221. do. A detailed description of the crystal growth process is omitted since it is the same as in FIGS. 1A to 1E. The crystal grains 250a and 260a grown up to the upper silicon layer 240 react with the upper silicon layer 240 to continue crystallization (250b and 260b) along the side, and the crystallization continues and other etching grooves 220 and 221 are continued. Meet the crystal grains (250b, 260b) grown from the metal catalyst grown in the) to form a grain boundary 270, the growth is stopped when the grain 270 is formed. In this case, a metal catalyst inducing crystallization of amorphous silicon may remain at the grain boundary interface 270.

3A to 3G are side cross-sectional views illustrating a crystallization method according to another embodiment of the present invention. In order to crystallize the silicon layer according to the present invention, first, the substrate 300 is prepared. The prepared substrate 300 is formed with a substrate etching groove 310 for use as a grain filter of a predetermined width. Since the etching groove 310 may be formed using the process described above with reference to FIGS. 1A and 1B, a detailed description of the etching groove 310 forming process is omitted. In this embodiment, the width of the etching groove 310 is formed in the range of 100nm ~ 500nm, the depth is formed to about 100 ~ 1000nm.

Next, referring to FIG. 3B, a buffer layer 320 is formed on the substrate 300 on which the etching groove 310 is formed. The buffer layer 320 prevents the metal used in the subsequent metal catalyst induced crystallization from being transferred through the substrate to other portions of the substrate to contaminate the substrate. In addition, the buffer layer 320 may serve to narrow the width of the formed etching groove 310, and is formed by depositing a silicon oxide film or a silicon nitride film by PECVD or LPCVD. The deposition thickness of the buffer layer 320 may be appropriately adjusted according to the formation width of the etching groove 310, and may be deposited to a thickness of about 20 to 100 nm. After the buffer layer 320 is deposited on the etching groove 310 formed on the substrate 300, a narrow etching groove 321 is formed.

Referring to FIG. 3C, a metal catalyst 330 is deposited on the buffer layer 320. The metal catalyst 330 is also formed on the bottom surface of the etching groove 321. However, it is preferable that the metal catalyst 330 is not deposited on the narrow and deep etching grooves 321, that is, the sidewalls of the buffer layer 320, to facilitate grain filtering during silicon crystallization. , To induce growth with the same directionality. At this time, the metal catalyst 330 is a metal such as gold (Au), silver (Ag), aluminum (Al), tin (Sb), indium (In) and nickel (Ni), molybdenum (Mo), palladium (Pd) It is formed using a metal forming a silicide such as titanium (Ti), copper (Cu), iron (Fe), chromium (cr) and the like. At this time, the metal catalyst 130 is selected and formed in a thickness range of 200 kPa or less.

Next, referring to FIG. 3D, a first amorphous silicon layer 340 is formed on the buffer layer 320 on which the metal catalyst 330 is deposited. In this case, the step coverage should be good at the time of deposition so that voids do not occur even in the narrow and long etching grooves 310. In the next step, referring to FIG. 3E, in order to selectively remove the metal catalyst 330 formed in addition to the etching groove 321, the substrate 300 is etched to a predetermined thickness range from the surface of the substrate 300. In this case, the etching thickness is etched to a thickness range sufficient to remove both the amorphous silicon layer 340 and the buffer layer 320 formed on the substrate 300. At this time, all of the metal catalysts 330 formed on the buffer layer 320 are also removed. When etching the substrate 300, a plasma etching or chemical mechanical polishing (CMP) process having anisotropic etching characteristics is used.

Referring to FIG. 3F, a second amorphous silicon layer 341 is formed on the substrate 300 on which the buffer layer 320 is etched to form a semiconductor layer of the thin film transistor. The thickness of the second amorphous silicon 341 may be differently deposited according to the characteristics of the semiconductor device to be manufactured. In the present embodiment, the second amorphous silicon 341 may be deposited to have a thickness of about 500˜1000 Å to manufacture a thin film transistor. The second amorphous silicon layer 341 is deposited by chemical vapor deposition such as LPCVD or PECVD.

When the second amorphous silicon 341 is deposited, when LPCVD is used, the deposition of the second amorphous silicon 341 should be performed at about 450 to 550 ° C. to prevent solid phase crystallization during the LPCVD deposition. If PECVD is used, dehydrogenation heat treatment may be necessary so that defects do not occur in the silicon thin film due to hydrogen gas ejection during heat treatment for later crystallization.

In a next step, referring to FIG. 3G, the substrate 300 is heat treated to crystallize the second amorphous silicon 341. In this case, the heat treatment uses a metal heat treatment or a quartz high temperature furnace, and the temperature applied to the substrate during the heat treatment uses a temperature range in which the first and second amorphous silicon 340 and 341 are crystallized by the metal catalyst 330. Temperature ranges (eg, between 450 and 600 ° C.) where self-solid crystallization does not occur should be used. As another method of crystallization, a method of crystallizing the amorphous silicon 340 by applying a voltage to the amorphous silicon 340 may be used. In this case, the crystallization time of the first and second amorphous silicon 340 and 341 may be shortened. can do. At this time, the voltage applied to the amorphous silicon (340, 341) is about 10 ~ 500V / cm, the time is made in the range of 10 ~ 300 minutes.

The first and second amorphous silicon 340 and 341 are crystallized by the applied heat. In the case of the first amorphous silicon 340 filled in the narrow and deep etching grooves 321, the first and second amorphous silicon 340 and 341 are surrounded by an insulating material. The thermal effect is obtained, and crystallization by the metal silicide may be induced at a lower temperature than the general metal catalyst induced crystallization. Thereafter, only the grains 350a having a vertical direction among the various grains simultaneously generated as the grains grow upward in the etching groove 321 may grow up to the second amorphous silicon layer 341. That is, since the grains grown in the other direction are trapped in the well and can no longer be grown, the narrow and deep etching groove 321 structure serves as a grain filter. The crystal grain 350a grown to the second amorphous silicon layer 341 continues to crystallize along the side in response to the first amorphous silicon layer 340 (350b), and the crystallization continues and grows in another etching groove. The grains grown from the metal catalyst may be met to form the grain boundary 370.

4A to 4E are views illustrating a manufacturing process of a thin film transistor using a semiconductor layer grown by the crystallization method according to the present invention.

Referring to FIG. 4A, the thin film transistor 400 according to the present method includes a substrate 400 on which a plurality of grain filters 410, 411, 412,..., Having a well structure are formed. In the substrate 400, a polycrystalline silicon layer 420 is formed in which a single crystal grains, which have undergone metal catalyst induced crystallization, are formed in a predetermined arrangement. At this time, the metal catalyst or silicide that induced the crystallization of the amorphous silicon layer may remain on the surfaces 420a and 420b where the crystal grains meet and form a boundary.

Next, referring to FIG. 4B, an active layer 430 of the thin film transistor 400 is formed to electrically isolate the device to form the polycrystalline silicon layer 420. In general, the components of the thin film transistor 400 are arranged so that channel regions (not shown) through which the gate electrode 450 passes through the active layer 430 do not span the grain boundary surfaces 420a and 420b. Grain growth can be induced at a location so that the channel region can be arranged so that the boundary surfaces 420a and 420b do not span.

4C to 4E, the gate insulating layer 440 and the gate metal layer are sequentially stacked on the active layer 430, and then the gate electrode 450 is formed. The gate insulating layer 440 may be a silicon oxide film, a silicon nitride film, or a high dielectric constant thin film such as HfO ₂ , ZrO ₂ , Ta ₂ O ₅ , Y ₂ O ₃ , HfSiON, HfAlON, or the like. The gate electrode 450 may be polysilicon containing impurities, Si _x Ge _{1- x} , or metals such as W, Ti, Ta, Ru, Pt, Mo, or metal nitrides such as TiN, TaN, TaSiN, WN, or Metal silicides such as CoSi, NiSi, WSi _x and the like can be used. Even though the active layer 430 of the thin film transistor 400 spans the silicon grain boundaries 420a and 420b, the silicon is actually determined by the overlapping region of the active layer and the gate electrode, that is, the channel region 430a. It can be free from deterioration of the electrical characteristics of the device by the remaining metal catalyst at the grain boundary.

Next, an impurity is implanted into the active layer 430 and activated by heat treatment to form a source region and a drain region. Finally, the thin film transistor 400 is formed by forming a source / drain electrode (not shown).

Although the present invention has been described with reference to the embodiments shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. There will be.

As described above, according to the above, in the present invention, a high quality polycrystalline silicon layer can be formed by crystallizing the silicon layer on the substrate having the grain filter structure using metal catalyst induction crystallization. In addition, the present invention can improve the electron mobility of the thin film transistor by forming a thin film transistor using the polycrystalline silicon layer crystallized using the crystallization method described above. In addition, the efficiency (for example, luminous efficiency, luminance, etc.) can be improved by using the thin film transistor formed using the above-mentioned manufacturing method in a liquid crystal display device or a display device.

Claims (20)

Forming a grain filter on the substrate; Forming a metal catalyst layer on the grain filter; Depositing an amorphous silicon layer over the substrate including the grain filter; Heat-treating the substrate to crystallize the amorphous silicon layer Silicon crystallization method comprising a. The method of claim 1, Forming the grain filter Forming a resist pattern having holes formed on the substrate; Patterning the substrate according to the resist pattern to form a grain filter having a well structure having a predetermined depth and width on the substrate. The method of claim 2, The forming of the grain filter is a silicon crystallization method of ion etching the substrate according to the resist pattern. The method of claim 3, The well structure has a cross-sectional width of 0.5 μm or less and a depth of 0.1 to 1 μm of silicon crystallization method. The method of claim 2, In the step of forming a metal catalyst layer on the grain filter Forming the metal catalyst layer on the bottom of the grain filter of the well structure and on the resist pattern; Removing at least one region of the resist pattern Silicon crystallization method comprising a. The method of claim 5, Forming the metal catalyst layer is a silicon crystallization method of depositing using one of sputtering, thermal evaporation, E-beam deposition. The method of claim 6, The metal catalyst layer is a silicon crystallization method using any one of gold, silver, aluminum, tin, indium, nickel, molybdenum, palladium, titanium, copper, iron and chromium. The method of claim 6, The metal catalyst layer is silicon crystallization method which is deposited in the range of 200Å or less. The method of claim 2, Crystallizing the amorphous silicon layer, Growing the amorphous silicon layer in the well structure to the upper part of the well structure by the metal catalyst, growing the amorphous silicon layer on the substrate laterally by the upwardly grown grains, and growing the laterally grown crystal grains Grain growth stops when forming an interface with other grains Silicon crystallization method comprising a. A substrate on which a well structure is formed; An active layer having a grain structure growing from the bottom of the well structure to the top by a metal catalyst provided in the well structure; A gate insulating layer formed on the active layer; A gate electrode formed on the gate insulating layer; And Source / drain electrodes electrically connected to one region of the active layer Thin film transistor comprising a. Forming a well structure recessed to a predetermined depth on the substrate; Forming a metal catalyst layer on the well structure; Depositing an amorphous silicon layer over the substrate including the well structure; Heat treating the substrate to crystallize the amorphous silicon layer; Patterning the crystallized amorphous silicon layer to form an active layer including a channel region; Forming a gate insulating film on the active layer region, and forming a gate electrode on the gate insulating film; Implanting impurities into the active layer region to form a source / drain region; And Forming a source / drain electrode in electrical contact with the source / drain region Method of manufacturing a thin film transistor comprising a. The method of claim 11, Forming the well structure Forming a resist pattern having holes formed on the substrate; And patterning the substrate in accordance with the resist pattern to form the well structure to have a predetermined depth and width in the substrate. The method of claim 12, And patterning the substrate according to the resist pattern using an active ion etching process. The method of claim 12, Forming the metal catalyst layer Forming the metal catalyst layer on the bottom of the well structure and on the resist pattern; Removing at least one region of the resist pattern. The method of claim 14, The well structure has a cross-sectional width of 0.5 μm or less and a depth of 0.1 to 1 μm of a method for manufacturing a thin film transistor. The method of claim 11, The forming of the metal catalyst layer may be performed using one of sputtering, thermal deposition, and E-beam deposition. The method of claim 16, The metal catalyst layer is a thin film transistor using any one of gold, silver, aluminum, tin, indium, nickel, molybdenum, palladium, titanium, copper, iron and chromium. The method of claim 16, The metal catalyst layer is a method of manufacturing a thin film transistor is formed in the range of 200mW or less. The method of claim 11, The step of crystallizing the amorphous silicon layer is Growing an amorphous silicon layer in the well structure to the upper part of the well structure by the metal catalyst, growing an amorphous silicon layer on the substrate to the side by the grown grains, and growing the laterally grown crystal grains Formation of the interface with other grains stops grain growth Method of manufacturing a thin film transistor comprising a. The method of claim 19, And forming the active layer so that the grain boundary is not located in an area where the channel region and the gate electrode overlap each other.

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