KR100647602B1 - A structure and manufacturing method for thin film transistor - Google Patents

Abstract

Disclosed are a thin film transistor and a method of manufacturing the thin film transistor to prevent the metal ions constituting the metal induction crystallization from flowing into the gate insulating layer, and to prevent the introduction of impurities from the outside during the heat treatment for crystallization of the active layer. The thin film transistor is characterized in that the metal layer for metal induction crystallization is located between an active layer and an ILD layer. In the method of manufacturing the thin film transistor, a crystallization step may be performed immediately after the metal layer for metal induction crystallization is formed on the active layer or an ILD layer (Inter Layer Dielectric) is further formed on the metal layer for metal induction crystallization and then crystallization. It characterized in that to perform.

Bottom gate, MIC, MILC, TFT

Description

Thin film transistor and manufacturing method {A structure and manufacturing method for thin film transistor}

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 illustrates an embodiment of a stacked structure of a bottom gate thin film transistor according to the present invention.

2 is a flowchart illustrating an embodiment of a method of manufacturing a bottom gate thin film transistor according to the present invention.

3 is a flowchart illustrating another embodiment of a method of manufacturing a bottom gate thin film transistor according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistors, and more particularly, to a structure and a manufacturing method of a bottom gate thin film transistor (TFT).

Currently used flat panel display devices can be divided into a light emitting region and a driving region, and the circuit constituting the driving region is mainly implemented using a thin film transistor.

The thin film transistor includes an active layer in which a channel is formed and a gate electrode for controlling the channel. The thin film transistor may be divided into a top gate structure and a bottom gate structure according to the relative positions of the active layer and the gate electrode.

The top gate structure is stacked in the order of an active layer, a gate insulating film, and a gate electrode using amorphous silicon or polysilicon. The bottom gate structure, listed from the bottom, is stacked in the order of a gate electrode, a gate insulating film, and an active layer using amorphous silicon or polysilicon.

이하의 낮은 전자 이동도(mobility)를 가진다. 이에 따라 최근에는 상기 비정질 실리콘 박막 트랜지스터를 다결정 실리콘 박막 트랜지스터(Polycrystalline Silicon TFT ; Poly-Si TFT)로 대체하는 경향을 보인다. 상기 다결정 실리콘 박막 트랜지스터는 비정질 실리콘 박막 트랜지스터에 비해 전자 이동도가 크고, 빛의 조사에 대한 안정성이 우수하다. 따라서, 상기 다결정 실리콘 박막 트랜지스터는 능동형(Active) 매트릭스 액정표시장치나, 능동형 매트릭스 유기전계 발광표시장치의 구동 및/또는 스위칭 트랜지스터로 사용될 수 있다. Amorphous Silicon TFTs (a-Si TFTs) used in flat panel displays are made of amorphous silicon because the semiconductor active layers constituting the source, drain, and channel are amorphous silicon.

It has the following low electron mobility. Accordingly, recently, the amorphous silicon thin film transistor has a tendency to replace the polycrystalline silicon TFT (Poly-Si TFT). The polycrystalline silicon thin film transistor has a higher electron mobility and superior stability to light irradiation than an amorphous silicon thin film transistor. Accordingly, the polycrystalline silicon thin film transistor may be used as a driving and / or switching transistor of an active matrix liquid crystal display device or an active matrix organic light emitting display device.

When manufacturing thin film transistor (TFT) panel, amorphous silicon is crystallized, solid phase crystallization (SPC) method, excimer laser crystallization (ELC) method, continuous side solid phase Sequential Lateral Solidification (SLS), Metal Induced Crystallization (MIC) or Metal Induced Lateral Crystallization (MILC) is used. Among them, the MIC method or the MILC method has an advantage that the crystallization temperature can be lowered by depositing a metal thin film on the surface of amorphous silicon, and using this as a crystallization catalyst to proceed with crystallization of the silicon film.

However, in the case of using the MIC method or the MILC method, in the case of the top gate structure, since silicon compounds are formed at the interface between the silicon and the gate oxide film, the characteristics of the transistor are deteriorated and the gate oxide film is deteriorated. There is a possibility that the metal material diffuses inside and acts as a mobile charge.

In order to overcome this problem, a bottom gate may be used.

SUMMARY OF THE INVENTION The present invention provides a thin film transistor which prevents metal ions constituting a metal induction crystallization metal from flowing into a gate insulating layer and prevents inflow of impurities from the outside during heat treatment for crystallization of an active layer. have.

Another technical problem to be achieved by the present invention is a method of manufacturing a thin film transistor which prevents metal ions constituting the metal induction crystallization layer from flowing into the gate insulating layer, and prevents inflow of impurities from the outside during heat treatment for crystallization of the active layer. To provide.

In accordance with an aspect of the present invention, a thin film transistor includes a substrate, a gate electrode, a gate insulating layer, an active layer, and a metal layer for metal induction crystallization. The gate electrode is formed on the substrate. The gate insulating layer is formed on the gate electrode. The chemical layer is formed on the gate insulating layer. The metal layer for metal derivatization crystals is formed on the active layer.

According to another aspect of the present invention, a thin film transistor includes a substrate, a gate electrode, a gate insulating layer, an active layer, a metal layer for metal induction crystallization, and an inter layer dielectric (ILD) layer. The gate electrode is formed on the substrate. The gate insulating layer is formed on the gate electrode. The chemical layer is formed on the gate insulating layer. The metal layer for metal derivatization crystals is formed on the active layer. The ILD layer is formed on the metal layer for metal derivatization crystals.

According to another aspect of the present invention, a method of manufacturing a thin film transistor includes: forming a gate electrode on an upper portion of a substrate; Forming a gate insulating layer on the gate electrode; Forming an active layer on top of the gate insulating layer; Forming a metal layer for metal induction crystallization on the active layer; And crystallization of the active layer.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor, including: forming a gate electrode on an upper portion of a substrate; Forming a gate insulating layer on the gate electrode; Forming an active layer on the gate insulating layer; Forming a metal layer for metal induction crystallization on the active layer; Forming an ILD on top of the metal layer; And crystallization of the active layer.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings that illustrate preferred embodiments of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 illustrates an embodiment of a stacked structure of a bottom gate thin film transistor according to the present invention.

Referring to FIG. 1, the bottom gate thin film transistor is formed on the substrate 101, and includes a gate electrode 102, a gate insulating layer 103, an active layer 104, and a metal induction crystallization metal layer 105. And an ILD layer 106 (hereinafter referred to as an interlayer dielectric layer).

The gate electrode 102 is provided on the substrate 101 in a predetermined pattern. The gate insulating layer 103 is provided to cover the gate electrode 102 by silicon dioxide and / or silicon nitride.

In the active layer 104 formed on the gate insulating layer 103, amorphous silicon is crystallized and is made of polycrystalline silicon. Although not shown, the active layer 104 includes a channel region corresponding to the gate electrode 102 and source and drain regions doped with impurity ions.

The metal induction crystallization metal layer 105 is a crystallization induction catalyst material for crystallizing the active layer 104 formed of amorphous silicon into polycrystalline silicon, and is formed on at least a portion of the upper portion of the active layer 104. That is, when crystallization is performed using the MIC method, the metal induction crystallization metal layer 105 is formed over the entire active layer 104. On the other hand, when the crystallization is performed using the MILC method, the metal induction crystallization metal layer 105 is formed only in a portion of the active layer 104, for example, a source and a drain region.

The metal induction crystallization layer 105 is Ni, Pd, Au, Sn, Sb, Cr, Mo, Tr, Ru, Rh, Fe, Co, V, Ti, Al, Ag, Cu and Pt ( One or more metal materials selected from Group).

The interlayer insulating layer 106 may be formed to cover both the active layer 104 and the metal induction crystallization metal layer 105. Although not shown, a source / drain electrode is provided on the interlayer insulating layer 106, and the source / drain electrode of the active layer 104 is formed through a contact hole formed in the interlayer insulating layer 106. It may be in contact with the source / drain region.

2 is a flowchart illustrating an embodiment of a method of manufacturing a bottom gate thin film transistor according to the present invention.

Referring to FIG. 2, the method of manufacturing a bottom gate thin film transistor includes: forming a gate electrode on an upper portion of a substrate (210); forming a gate insulating layer on an upper portion of the gate electrode (220); Forming an active layer of amorphous silicon on top of the 230, forming a metal layer for metal induced crystallization on the active layer 240, and crystallizing the active layer 250.

1 and 2, the step 210 of forming the gate electrode 102 on the substrate 101 may include a material for forming the gate electrode 102 on the substrate 101, for example, A metal material is formed and patterned to form the gate electrode 102 in a predetermined pattern.

In the forming of the gate insulating layer 220, as shown in FIG. 1, the gate insulating layer 103 is formed of silicon dioxide or silicon nitride to cover the patterned gate electrode 102. In this case, as shown in FIG. 1, the gate insulating layer 103 does not necessarily have to be one layer, and may have a structure of two or more layers in which silicon dioxide and silicon nitride are combined.

(angstrom) 정도의 두께로 형성시킨 후, 이를 소정의 활성층(104) 패턴으로 패터닝하는 단계를 포함한다. 다만, 비정질 실리콘의 패터닝은 비정질 실리콘의 결정화 이후에 진행하여도 무방하다. In the forming of the active layer 230, first, amorphous silicon is a predetermined thickness, for example, 500.

After forming a thickness of about (angstrom), and patterning it to a predetermined active layer 104 pattern. However, patterning of amorphous silicon may proceed after crystallization of amorphous silicon.

In the forming step 240 of the metal induction crystallization metal layer, the crystallization induction catalyst material metal layer 105 is formed on a predetermined portion of the split layer 104 made of amorphous silicon. The metal material may be at least one selected from the group consisting of Ni, Pd, Au, Sn, Sb, Cr, Mo, Tr, Ru, Rh, Fe, Co, V, Ti, Al, Ag, Cu, and Pt. Metallic materials can be used. As the formation region of the metal layer, when the MIC method is used for crystallization, the metal induction crystallization metal layer 105 is formed over the entire active layer 104. When the MILC method is used for crystallization, the metal layer 105 for the metal induced crystallization is formed only in a portion of the active layer 104, for example, a source and a drain region.

정도의 온도에서 열처리함으로써 이루어진다. After forming the metal induction crystallization metal layer 105 as described above, in the crystallization step 250, amorphous silicon is crystallized to form polycrystalline silicon. Crystallization is about 500 to 550

It is made by heat treatment at a temperature of about.

In a structure in which the gate is located below the active layer 104, when the silicon constituting the active layer 104 is crystallized by the MIC or MILC method, the active layer is not the interface between the gate insulating layer 103 and the active layer 104. If a metal layer for metal induction crystallization, such as nickel (Ni), is deposited on top of the 104, the deposition of the gate insulating layer 103 and the deposition of amorphous silicon are possible in a short time, so that the amorphous silicon and gate insulating layer 103 Can improve the interface characteristics.

In addition, after the crystallization by heat treatment, the roughness of the surface of the polycrystalline silicon increases, but there is no change in the characteristics of the interface between the active layer 104 and the gate insulating layer 102.

3 is a flowchart illustrating another embodiment of a method of manufacturing a bottom gate thin film transistor according to the present invention.

Referring to Figure 3, the bottom gate thin film transistor manufacturing method,

Forming a gate electrode on the substrate (310), forming a gate insulating layer on the gate electrode (320), forming an active layer on the gate insulating layer (330), Forming a metal layer for metal induction crystallization on the top 340, forming an ILD on the top of the metal layer 350 and crystallization step 360 of the active layer.

During the heat treatment, when the amorphous silicon is exposed to the outside, impurities may be introduced into the silicon from the outside, thereby deteriorating characteristics. Thus, heat treatment may be performed in a process after the deposition of the interlayer insulating layer 106 to prevent this. In addition, there is an advantage that the heat treatment for activating the ions implanted in the source and drain regions of the active layer need not be performed separately. In addition, after the heat treatment, the roughness of the surface of the polycrystalline silicon increases, but there is no change in the characteristics of the interface between the active layer 104 and the gate insulator 103.

In the structure in which the gate electrode is located under the active layer, when the silicon is crystallized by the MIC or MILC method, a metal such as nickel (Ni) is formed between the interlayer insulating film and the active layer, not the interface between the gate insulating film and the silicon. Since the deposition of the gate insulating layer and the deposition of the amorphous silicon can be performed in a short time, the characteristics of the interface between the amorphous silicon and the gate insulating film can be improved.

Since the heat treatment is possible after the interlayer insulating film deposition, it is possible to prevent the contamination of the silicon by impurities generated during the heat treatment. In addition, since the heat treatment is possible after the ion implantation, there is no need to perform a separate heat treatment process for activation (activation), it is possible to improve the MIC and MILC heat treatment rate by the implanted (dopant).

As described above, the optimum embodiment has been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the thin film transistor and the method of manufacturing the thin film transistor according to the present invention have an advantage of keeping the interface between the amorphous silicon and the gate insulating film clean and preventing metal ions from flowing into the gate oxide film.

Claims (7)

A gate electrode formed on the substrate; A gate insulating layer formed on the gate electrode; An active layer formed on the gate insulating layer; A metal layer for metal induction crystallization formed on at least a portion of an upper portion of the active layer; And An interlayer dielectric layer formed on the metal layer for metal induction crystallization, and a source / drain electrode is provided on the interlayer dielectric layer, and the source / drain electrode is formed through a contact hole formed in the interlayer dielectric layer. A thin film transistor, which is in contact with a source / drain region of an active layer. delete The method of claim 1, wherein the active layer, A thin film transistor, characterized in that the polycrystalline silicon layer by a metal induced crystal (Polycrystalline silicon layer). The method of claim 1, wherein the metal layer for metal induction crystallization, The at least one metal material selected from the group consisting of Ni, Pd, Au, Sn, Sb, Cr, Mo, Tr, Ru, Rh, Fe, Co, V, Ti, Al, Ag, Cu, and Pt A thin film transistor comprising a silicon crystallization catalyst material. Forming a gate electrode on top of the substrate; Forming a gate insulating layer on the gate electrode; Forming an active layer of amorphous silicon on top of the gate insulating layer; Forming a metal layer for metal induction crystallization on at least a portion of an upper portion of the active layer; Forming an interlayer insulating layer on the metal layer; Crystallizing the active layer; Forming a tone hole in the interlayer insulating layer such that a source / drain electrode contacts a source / drain region of an active layer; And Forming a source / drain electrode on the interlayer insulating layer. delete The metal layer of claim 5, wherein the metal derivatization crystal layer is The silicon crystallization catalyst comprising at least one metal material selected from the group consisting of Ni, Pd, Au, Sn, Sb, Cr, Mo, Tr, Ru, Rh, Fe, Co, V, Ti, Al, Ag, Cu and Pt A method of manufacturing a thin film transistor, characterized in that provided with a material.

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