WO2012005389A1 - Method for manufacturing a polycrystalline silicon thin film - Google Patents

Method for manufacturing a polycrystalline silicon thin film Download PDF

Info

Publication number
WO2012005389A1
WO2012005389A1 PCT/KR2010/004369 KR2010004369W WO2012005389A1 WO 2012005389 A1 WO2012005389 A1 WO 2012005389A1 KR 2010004369 W KR2010004369 W KR 2010004369W WO 2012005389 A1 WO2012005389 A1 WO 2012005389A1
Authority
WO
WIPO (PCT)
Prior art keywords
oxide film
metal
metal layer
layer
forming step
Prior art date
Application number
PCT/KR2010/004369
Other languages
French (fr)
Korean (ko)
Inventor
이원태
조한식
김상규
Original Assignee
노코드 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 노코드 주식회사 filed Critical 노코드 주식회사
Priority to PCT/KR2010/004369 priority Critical patent/WO2012005389A1/en
Publication of WO2012005389A1 publication Critical patent/WO2012005389A1/en

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02422Non-crystalline insulating materials, e.g. glass, polymers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02491Conductive materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02658Pretreatments
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02672Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0368Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors
    • H01L31/03682Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors including only elements of Group IV of the Periodic System
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0392Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
    • H01L31/03921Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate including only elements of Group IV of the Periodic System
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • H01L31/182Special manufacturing methods for polycrystalline Si, e.g. Si ribbon, poly Si ingots, thin films of polycrystalline Si
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/546Polycrystalline silicon PV cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a method for manufacturing a polycrystalline silicon thin film for use in a solar cell, and more particularly, to a method for effectively producing a polycrystalline silicon thin film of an amorphous silicon thin film by metal induction crystallization.
  • the process requiring high temperature heat treatment in the production of poly-Si is a crystallization heat treatment (Crystallization) that converts the amorphous silicon (a-Si) thin film to a crystalline silicon thin film and an activation heat treatment (Dopant) that is electrically activated after doping Activation).
  • Crystallization that converts the amorphous silicon (a-Si) thin film to a crystalline silicon thin film
  • Dopant activation heat treatment
  • LTPS Low Temperature poly-Si
  • Representative methods for forming a polycrystalline silicon thin film include solid phase crystallization (SPC), excimer laser annealing (ELA), and metal induced crystallization (MIC).
  • Solid Phase Crystallization is the most direct and long used method of obtaining polycrystalline silicon (poly-Si) thin films from amorphous silicon (a-Si).
  • SPC is a method of obtaining a polycrystalline silicon thin film having a grain size of about several micro by heat-treating the amorphous silicon thin film at a temperature of 600 °C or more for several tens of hours.
  • the polycrystalline silicon thin film obtained by this method has a disadvantage in that it is difficult to use a glass substrate because of high defect density in crystal grains and a high heat treatment temperature, and a long process time due to long heat treatment.
  • Excimer Laser Annealing is a method of instantaneously irradiating an excimer laser to a amorphous silicon thin film for nanoseconds to melt and recrystallize the amorphous silicon thin film without damaging the glass substrate.
  • ELA is known to have significant problems in mass production processes.
  • ELA has a very non-uniform grain structure of polycrystalline silicon (poly-Si) thin film according to the laser irradiation amount.
  • ELA has a problem that it is difficult to manufacture a uniform crystalline silicon thin film because of the narrow process range.
  • the surface of the polycrystalline silicon thin film is rough, which adversely affects the characteristics of the device. This problem is more serious in the application of organic light emitting diodes (OLEDs) in which the uniformity of thin film transistors (TFTs) is important.
  • OLEDs organic light emitting diodes
  • MIC Metal Induced Crystallization
  • MIC is a method of inducing crystallization of silicon by applying a metal catalyst to amorphous silicon by sputtering or spin coating, followed by heat treatment at low temperature.
  • metal catalyst various metals such as nickel (Ni), copper (Cu), aluminum (Al), and palladium (Pd) may be used.
  • nickel (Ni) is used as a metal catalyst in MIC, in which reaction control is easy and large grains are obtained.
  • MIC can be crystallized at low temperatures below 700 ° C, but there are significant problems in the actual production process. This problem is that a significant amount of metal diffused in the active region in the TFT causes typical metal contamination, increasing leakage current, one of the TFT characteristics.
  • LTPS low temperature poly-silicon
  • amorphous silicon thin film transistor liquid crystal displays a-Si TFT LCDs
  • AMOLEDs active organic light emitting diodes
  • the method of manufacturing polycrystalline silicon is also important in that active organic light emitting diodes (AMOLEDs) will compete with crystalline wafer forms in solar cells. Therefore, the production cost and market competitiveness of the product are stable and polycrystalline at a lower price than the amorphous silicon thin film transistor liquid crystal display (a-si TFT LCD) and the crystalline wafer type solar cell where the production technology is stabilized. It depends on whether you can make silicon.
  • FIG. 1 schematically shows a manufacturing process for obtaining a polycrystalline silicon thin film from amorphous silicon by a metal induction crystallization method.
  • a buffer layer 2 made of silicon oxide (SiO 2 ) is formed on a substrate 1 such as glass, and an amorphous silicon layer 3 is formed on the buffer layer 2 by plasma chemical vapor deposition (PECVD).
  • PECVD plasma chemical vapor deposition
  • RTA Rapid Thermal Annealing
  • An object of the present invention is to solve the above problems, in the method of manufacturing a polycrystalline silicon thin film using the metal induction crystallization method, precisely control the amount of catalyst metal and enable crystallization at low temperature By providing an efficient method for producing a polycrystalline silicon thin film.
  • a method of manufacturing a polycrystalline silicon thin film according to the present invention includes: forming a metal layer on an insulating substrate;
  • the substrate includes a buffer layer made of SiO 2 between the metal layer and the metal layer.
  • the thickness of the said metal layer is 5 kPa-2000 kPa, and the thickness of the said oxide film is 1 kPa-1500 kPa.
  • the heat treatment temperature in the oxide film forming step is preferably 50 °C to 1000 °C.
  • the metal layer is formed in a state in which the metal and the oxide of the metal is mixed. Forming step;
  • a method of manufacturing a polycrystalline silicon thin film according to another embodiment of the present invention silicon layer forming step of laminating an amorphous silicon layer on an insulating substrate;
  • the method for producing a polycrystalline silicon thin film according to the present invention is effective to manufacture an effective polycrystalline silicon crystallized thin film by precisely controlling the amount of the metal catalyst diffused in the amorphous silicon layer and acting as a nucleus of silicon crystallization in the amorphous silicon layer.
  • the manufacturing method of the polycrystalline silicon thin film according to the present invention has an advantage that can be crystallized at a lower temperature than the conventional manufacturing method.
  • FIG. 1 is a view for explaining a conventional method for producing a polycrystalline silicon thin film by a metal induction crystallization method.
  • FIG. 2 is a view showing a manufacturing process according to a preferred embodiment of the invention.
  • FIG. 3 is a view showing a cross section after the metal layer forming step shown in FIG.
  • FIG. 4 is a view showing a cross section after the oxide film forming step shown in FIG.
  • FIG. 5 is a view illustrating a cross section after the silicon layer forming step illustrated in FIG. 2.
  • FIG. 6 is a cross-sectional view schematically showing how polycrystalline silicon is formed on a substrate after the crystallization step shown in FIG. 2.
  • FIG. 8 is a graph analyzing the wave number of the amorphous silicon illustrated in FIG. 7.
  • FIG. 9 is a photograph of the surface of a crystalline silicon wafer viewed under an optical microscope.
  • FIG. 10 is a graph analyzing the wave number of the silicon wafer illustrated in FIG. 9.
  • FIG. 11 is a photograph of a surface of a polycrystalline silicon thin film manufactured by a conventional metal induction crystallization method viewed with an optical microscope.
  • FIG. 11 is a photograph of a surface of a polycrystalline silicon thin film manufactured by a conventional metal induction crystallization method viewed with an optical microscope.
  • FIG. 12 is a graph analyzing the wave number of the polycrystalline silicon thin film illustrated in FIG. 11.
  • Figure 13 is a photograph of the surface of the polycrystalline silicon thin film prepared according to the present invention with an optical microscope.
  • FIG. 14 is a graph analyzing the wave number of the polycrystalline silicon thin film illustrated in FIG. 13.
  • 15 is a photograph of the surface of a silicon thin film after a crystallization step without forming a metal oxide film as seen under an optical microscope.
  • FIG. 16 is a graph analyzing the wave number of the polycrystalline silicon thin film illustrated in FIG. 15.
  • FIG. 2 is a view showing a manufacturing process according to a preferred embodiment of the invention.
  • 3 is a view showing a cross section after the metal layer forming step shown in FIG. 4 is a view showing a cross section after the oxide film forming step shown in FIG.
  • FIG. 5 is a view illustrating a cross section after the silicon layer forming step illustrated in FIG. 2.
  • 6 is a cross-sectional view schematically showing how polycrystalline silicon is formed on a substrate after the crystallization step shown in FIG. 2.
  • a method of manufacturing a polycrystalline silicon thin film may include a metal layer forming step S1, an oxide film forming step S2, A silicon layer forming step S3 and a crystallization step S4 are included.
  • a metal layer 30 such as nickel (Ni) is formed on an insulating substrate 10 such as glass.
  • the substrate 10 includes a buffer layer 20 made of a material such as silicon oxide (SiO 2 ).
  • the buffer layer 20 is provided to serve as an insulation function.
  • the buffer layer 20 is provided to prevent impurities from being contaminated in the silicon layer 50 by the diffusion of impurities from the substrate 10 to the silicon layer 50 to be described later in the crystallization step (S4) to be described later.
  • the metal layer 30 may be performed by a known method such as plasma chemical vapor deposition (PECVD). It is preferable that the thickness of the said metal layer 30 is 5 kPa-2000 kPa.
  • the thickness of the metal layer 30 is less than 5 ⁇ s, there is a problem in that the reproducibility problem and the uniformity of the metal layer 30 deteriorate when the metal layer 30 is deposited in a large area due to the too thin thickness.
  • the thickness of the metal layer 30 exceeds 2000 ⁇ , a large amount of metal penetrates and causes a metal contamination problem, thereby lowering the characteristics of a device including a crystallized silicon layer.
  • a patterning step of removing a portion of the metal layer 30 by a photolithography method may be performed. If necessary, the patterning step can be omitted.
  • the patterning step is to uniformly distribute the growth nucleus of the crystalline silicon.
  • the metal layer 30 is heat-treated under an atmosphere of vacuum, air, oxygen, or nitrogen to form nickel oxide (NiO) or the like on the surface of the metal layer 30 and the metal layer 30.
  • a metal oxide film 40 such as Ni 2 O 3 ) is formed.
  • the metal oxide film 40 may be formed to be distinguished from the metal layer 30.
  • the metal layer 30 and the metal oxide film 40 may be mixed to form a single layer. It may also form a structure. In the structure in which the metal layer 30 and the metal oxide film 40 are mixed, it is not necessary to independently perform the metal layer forming step S1. That is, in some cases, the metal layer and the oxide film may be mixed by simultaneously performing heat treatment while forming the metal layer in the oxide film forming step (S2).
  • the oxide film 40 is produced at a heat treatment temperature range of 50 °C to 1000 °C.
  • the temperature at which the oxide film 40 is formed is at least 50 ° C, and there is a problem that an oxide of nickel (Ni) is not formed well at a temperature of less than 50 ° C.
  • the heat treatment temperature exceeds 1000 ° C., the substrate 10 made of glass deforms or breaks due to thermal shock.
  • the heat treatment method in the oxide film forming step (S2) may be a high temperature (furnace), rapid heat treatment (RTA), ultraviolet (UV) heating method and the like.
  • the oxide film 40 serves to lower the activation energy during diffusion of the catalyst metal acting as a nucleus of the crystallization of the amorphous silicon layer 50 in the crystallization step S4 described later. It is preferable that the thickness of the said oxide film 40 is 1 kV-1500 kPa. If the thickness of the oxide film 40 is less than 1 mm, the oxide film 40 may be too thin to perform its function. On the other hand, when the thickness of the oxide film 40 exceeds 1500 kPa, there is a problem that it is difficult to penetrate the catalyst metal from the metal layer 30. The oxide film 40 serves to lower the activation energy during diffusion of the catalyst metal acting as a nucleus of the crystallization of the amorphous silicon layer 50 in the crystallization step S4 described later.
  • the silicon layer 50 is formed by stacking amorphous silicon (A-Si) on the oxide film 40.
  • the method of forming the silicon layer 50 may be performed using a method such as a known plasma chemical vapor deposition method.
  • heat treatment is performed such that crystalline silicon 60 is generated in the silicon layer 50 made of amorphous by using metal particles present in the metal layer 30 or the oxide film 40 as a catalyst.
  • the heat treatment in the crystallization step (S4) is performed at 630 ° C using Rapid Thermal Annealing (RTA) equipment.
  • RTA Rapid Thermal Annealing
  • the size of the crystal grains was observed by using an optical microscope and Raman Spectroscopy, and the wave number having the maximum intensity was analyzed.
  • FIG. 7 is a photograph of the surface of amorphous silicon as seen under an optical microscope.
  • FIG. 8 is a graph analyzing the wave number of the amorphous silicon illustrated in FIG. 7.
  • 9 is a photograph of the surface of a crystalline silicon wafer viewed under an optical microscope.
  • FIG. 10 is a graph analyzing the wave number of the silicon wafer illustrated in FIG. 9.
  • FIG. 11 is a photograph of a surface of a polycrystalline silicon thin film manufactured by a conventional metal induction crystallization method viewed with an optical microscope.
  • FIG. FIG. 12 is a graph analyzing the wave number of the polycrystalline silicon thin film illustrated in FIG. 11.
  • Figure 13 is a photograph of the surface of the polycrystalline silicon thin film prepared according to the present invention with an optical microscope.
  • FIG. 14 is a graph analyzing the wave number of the polycrystalline silicon thin film illustrated in FIG. 13.
  • the silicon layer 50 which is amorphous silicon, exhibits a maximum intensity at a wave number of 480 cm ⁇ 1 .
  • the horizontal axis represents a wave number (cm ⁇ 1 ) and corresponds to a frequency.
  • a wave number is a unit of frequency that represents the number of waves in a unit distance by dividing the frequency of light by the speed of light in atomic, molecular, and nuclear spectroscopy.
  • the frequency of a wave is represented by the Greek letter ⁇ (nu), which is equal to the luminous flux c divided by the wavelength ⁇ . That is, ⁇ c / ⁇ .
  • a typical spectral line is a wavelength of 5.8 ⁇ 10 ⁇ 5 cm and corresponds to a frequency of 5.17 ⁇ 10 14 kHz.
  • the frequency divided by the speed of light is ⁇ / c, which is 1 / ⁇ in the above equation.
  • 1 / ⁇ represents the number of waves found within 1m.
  • the wavenumber is usually measured in units of 1 / m, i.e. m- 1 and 1 / cm, i.e. cm- 1 .
  • the vertical axis is a sum of waves measured per unit time and corresponds to intensity (CPS, Count Per Second).
  • the units of the horizontal axis and the vertical axis of FIGS. 10, 12, and 14 are the same as those of FIG. 8.
  • silicon wafers which are typical crystalline silicon, exhibit maximum strength at a wavenumber of 520 cm ⁇ 1 as shown in FIGS. 9 and 10.
  • 11 and 12 show surface photographs and wave number analysis graphs of a polycrystalline silicon thin film manufactured by a conventional metal induction crystallization method. Referring to FIGS. 11 and 12, the maximum strength is shown at a similar frequency compared to the crystalline silicon wafers shown in FIGS. 9 and 10.
  • FIGS. 13 and 14 optical micrographs and wave number analysis graphs of the polycrystalline silicon thin film manufactured by the present invention are shown in FIGS. 13 and 14, respectively.
  • FIG. 14 it can be seen that the wave number representing the maximum strength in the polycrystalline silicon thin film manufactured by the present invention is well represented as in the crystalline silicon wafer shown in FIG. 10.
  • FIG. 13 is an optical micrograph of 1000 times magnification.
  • the grains of the polycrystalline silicon thin film manufactured by the present invention are much larger than those of the polycrystalline silicon thin film manufactured by the conventional method. Able to know.
  • FIG. 15 and 16 show the degree of crystallization of amorphous silicon when the oxide film 40 is not formed as a material for explaining the effects of the present invention.
  • FIG. 15 illustrates that after forming a metal layer 30 such as nickel (Ni) on an insulating substrate 10 and laminating an amorphous silicon layer 50 on the metal layer 30 without forming the oxide film 40, the heat treatment is performed. It is an optical microscope photograph (magnification X1000) which observed whether the silicon layer 50 crystallized.
  • FIG. 16 is a graph in which the wave number of the silicon thin film illustrated in FIG. 15 is analyzed to determine whether the silicon layer 50 illustrated in FIG. 15 is crystallized. Referring to FIG.
  • the wave number showing the maximum intensity is 480 cm ⁇ 1, which is the same as the amorphous silicon thin film shown in FIG. 8. Therefore, it can be seen that crystallization does not occur well when the oxide film 40 does not exist, that is, when there is no metal oxide.
  • the manufacturing method of the polycrystalline silicon thin film according to the present invention is superior to the conventional manufacturing method.
  • the manufacturing method of the polycrystalline silicon thin film according to the present invention has the advantage that it can be crystallized at a lower temperature than the conventional manufacturing method.
  • the method for producing a polycrystalline silicon thin film according to the present invention by precisely controlling the amount of the catalyst metal in advance by disposing the catalyst metal, which is a nucleus of the reaction that is transformed from amorphous silicon into crystalline silicon, in the lower part of the amorphous silicon layer, it is then diffused into the amorphous silicon layer. By doing so, there is an advantage of preventing the inflow of impurities and lowering the activation energy.
  • the crystalline silicon may be generated in the amorphous silicon layer by heat treatment after the oxide film is formed under the amorphous silicon layer.
  • the conventional process may be modified to achieve a desired purpose. can do. That is, as a modified embodiment of the present invention, after the silicon layer forming step of laminating an amorphous silicon layer on an insulating substrate, an oxide film forming step of forming an oxide film in a state in which a metal and an oxide of the metal is mixed on the silicon layer And performing a metal layer forming step of forming a metal layer on the oxide film, and then performing a heat treatment to produce crystalline silicon in the amorphous silicon layer using the metal layer or metal particles of the oxide film as a catalyst. have. That is, since the core process of the present invention is heat treatment after forming the oxide film adjacent to the amorphous silicon layer, the object of the present invention can be achieved even by forming the oxide film on the amorphous silicon layer.
  • the embodiment described with reference to FIGS. 2 to 16 may be modified to sequentially perform the metal layer forming step and the oxide film forming step twice, followed by the silicon layer forming step. That is, the method of manufacturing a polycrystalline silicon thin film according to the modified embodiment includes: forming a first metal layer on an insulating substrate; Forming a metal oxide film on the first metal layer by heat-treating the first metal layer, or forming a metal oxide film by depositing a metal oxide film on the surface of the first metal layer; The second metal layer is formed again on the metal oxide film formed in the first oxide film forming step, and the second metal layer is heat-treated to form a metal oxide film on the surface of the second metal layer or by depositing a metal oxide film on the surface of the second metal layer.
  • a second oxide film forming step of forming an oxide film A silicon layer forming step of laminating an amorphous silicon layer on the oxide film formed in the second oxide film forming step; And a crystallization step of heat-treating the crystalline silicon in the amorphous silicon layer using the metal particles of the first metal layer and the second metal layer or the metal oxide film formed in the first oxide film forming step and the second oxide film forming step as catalysts. It includes.
  • a method of manufacturing a polycrystalline silicon thin film according to the present invention includes: forming a metal layer on an insulating substrate;
  • the substrate includes a buffer layer made of SiO 2 between the metal layer and the metal layer.
  • the thickness of the said metal layer is 5 kPa-2000 kPa, and the thickness of the said oxide film is 1 kPa-1500 kPa.
  • the heat treatment temperature in the oxide film forming step is preferably 50 °C to 1000 °C.
  • the metal layer is formed in a state in which the metal and the oxide of the metal is mixed. Forming step;
  • a method of manufacturing a polycrystalline silicon thin film according to another embodiment of the present invention silicon layer forming step of laminating an amorphous silicon layer on an insulating substrate;
  • a method of manufacturing a polycrystalline silicon thin film according to another embodiment of the present invention the first metal layer forming step of forming a metal layer on an insulating substrate;
  • the second metal layer is formed again on the metal oxide film formed in the first oxide film forming step, and the second metal layer is heat-treated to form a metal oxide film on the surface of the second metal layer or by depositing a metal oxide film on the surface of the second metal layer.

Abstract

A method for manufacturing a polycrystalline silicon thin film comprises the steps of: forming a metal layer on an insulation substrate; heat-treating the metal layer to form a metal oxide film on the metal layer; stacking an amorphous silicon layer on the metal oxide film; and heat-treating the amorphous silicon layer using the metal layer or metal particles of the oxide film as a catalyst to generate crystalline silicon.

Description

다결정 실리콘 박막의 제조방법Method of manufacturing polycrystalline silicon thin film
본 발명은 태양전지 등에 사용되는 다결정 실리콘 박막을 제조하는 방법에 관한 것으로서, 더 구체적으로는 비정질 실리콘의 박막을 금속유도결정화법에 의해 효과적으로 다결정 실리콘 박막을 제조하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a polycrystalline silicon thin film for use in a solar cell, and more particularly, to a method for effectively producing a polycrystalline silicon thin film of an amorphous silicon thin film by metal induction crystallization.
일반적으로, 다결정 실리콘(poly-Si)의 제조에서 일어나는 대부분의 문제점은 고온에서 취약한 유리 기판의 사용으로 인해 공정 온도를 비정질 실리콘(a-Si) 박막이 결정화되는 온도로 충분히 올릴 수 없는 것이다. In general, most problems arising in the production of poly-silicon (poly-Si) are due to the use of glass substrates that are vulnerable at high temperatures, and the process temperature cannot be raised sufficiently to the temperature at which the amorphous silicon (a-Si) thin film is crystallized.
다결정 실리콘(poly-Si)의 제조에서 고온의 열처리가 필요한 공정은 비정질 실리콘(a-Si) 박막을 결정질 실리콘 박막으로 바꾸는 결정화 열처리(Crystallization)와 도핑(Doping) 후 전기적으로 활성화시키는 활성화 열처리(Dopant Activation) 등이다.The process requiring high temperature heat treatment in the production of poly-Si is a crystallization heat treatment (Crystallization) that converts the amorphous silicon (a-Si) thin film to a crystalline silicon thin film and an activation heat treatment (Dopant) that is electrically activated after doping Activation).
현재, 유리 기판이 허용하는 저온의 온도에서, 빠른 시간 내에 다결정 실리콘 박막을 형성하는 다양한 공정(LTPS:Low Temperature poly-Si)이 제안되고 있다. 다결정 실리콘 박막을 형성하는 대표적인 방법은 고상결정화법(SPC, Solid Phase Crystallization), 엑시머 레이저 순간 조사법(ELA, Excimer Laser Annealing), 금속유도 결정화법(MIC, Metal Induced Crystallization) 등이다.At present, a variety of processes (LTPS: Low Temperature poly-Si) have been proposed for forming a polycrystalline silicon thin film in a short time at a low temperature that the glass substrate allows. Representative methods for forming a polycrystalline silicon thin film include solid phase crystallization (SPC), excimer laser annealing (ELA), and metal induced crystallization (MIC).
SPC(Solid Phase Crystallization)는, 비정질 실리콘(a-Si)으로부터 다결정 실리콘(poly-Si) 박막을 얻는 가장 직접적이고도 오래 사용된 방법이다. SPC는 비정질 실리콘 박막을 600℃ 이상의 온도에서 수십 시간 동안 열처리하여 결정립의 크기가 수 마이크로 내외인 다결정 실리콘 박막을 얻는 방법이다. 이 방법으로 얻어진 다결정 실리콘 박막은 결정립 내의 결함밀도가 높고, 열처리 온도가 높기 때문에 유리 기판을 사용하기 어려우며, 장시간의 열처리로 인해 공정시간이 긴 단점이 있다.Solid Phase Crystallization (SPC) is the most direct and long used method of obtaining polycrystalline silicon (poly-Si) thin films from amorphous silicon (a-Si). SPC is a method of obtaining a polycrystalline silicon thin film having a grain size of about several micro by heat-treating the amorphous silicon thin film at a temperature of 600 ℃ or more for several tens of hours. The polycrystalline silicon thin film obtained by this method has a disadvantage in that it is difficult to use a glass substrate because of high defect density in crystal grains and a high heat treatment temperature, and a long process time due to long heat treatment.
ELA(Excimer Laser Annealing)는 비정질 실리콘 박막에 나노초(nano-second) 동안 엑시머 레이저를 순간 조사하여, 유리 기판의 손상 없이 비정질 실리콘 박막을 용융 및 재결정시키는 방법이다.Excimer Laser Annealing (ELA) is a method of instantaneously irradiating an excimer laser to a amorphous silicon thin film for nanoseconds to melt and recrystallize the amorphous silicon thin film without damaging the glass substrate.
그러나, ELA는 양산 공정에서 상당한 문제점이 있는 것으로 알려져 있다. ELA는 레이저 조사량에 따른 다결정 실리콘(poly-Si) 박막의 그레인 구조가 매우 불균일하다. ELA는 공정 범위가 좁아 균일한 결정질 실리콘 박막의 제조가 어려운 문제점이 있다. 또한, 다결정 실리콘 박막의 표면이 거칠어 소자의 특성에 나쁜 영향을 주게 된다. 이러한 문제점은 박막트랜지스터(Thin Film Transistor, TFT)의 균일도가 중요한 유기발광다이오드(Organic Light Emitting Diode, OLED)의 응용에 있어서는 더욱 심각한 것이다.However, ELA is known to have significant problems in mass production processes. ELA has a very non-uniform grain structure of polycrystalline silicon (poly-Si) thin film according to the laser irradiation amount. ELA has a problem that it is difficult to manufacture a uniform crystalline silicon thin film because of the narrow process range. In addition, the surface of the polycrystalline silicon thin film is rough, which adversely affects the characteristics of the device. This problem is more serious in the application of organic light emitting diodes (OLEDs) in which the uniformity of thin film transistors (TFTs) is important.
이러한 문제점을 극복하기 위해 제시된 방법이 금속유도결정화법(MIC, Metal Induced Crystallization)이다. MIC는 비정질 실리콘에 금속 촉매를 스퍼터링이나 스핀 코팅의 방법으로 도포한 후에 낮은 온도에서 열처리하여 실리콘의 결정화를 유도하는 방법이다. 금속 촉매로 니켈(Ni), 구리(Cu), 알루미늄(Al), 팔라듐(Pd) 등의 다양한 금속이 사용 가능하다. 일반적으로 MIC에는 반응 제어가 쉽고 큰 그레인이 얻어지는 니켈(Ni)이 금속 촉매로 사용되고 있다. MIC는 700℃ 미만의 낮은 온도에서 결정화가 가능하나 실제 양산공정에 적용하기에는 상당한 문제점이 있다. 이 문제점은 TFT내 활성화 영역에 확산되는 상당한 양의 금속은 전형적인 금속 오염을 일으켜 TFT 특성 중 하나인 누설전류 증가시키게 된다.To overcome this problem, the proposed method is Metal Induced Crystallization (MIC). MIC is a method of inducing crystallization of silicon by applying a metal catalyst to amorphous silicon by sputtering or spin coating, followed by heat treatment at low temperature. As the metal catalyst, various metals such as nickel (Ni), copper (Cu), aluminum (Al), and palladium (Pd) may be used. In general, nickel (Ni) is used as a metal catalyst in MIC, in which reaction control is easy and large grains are obtained. MIC can be crystallized at low temperatures below 700 ° C, but there are significant problems in the actual production process. This problem is that a significant amount of metal diffused in the active region in the TFT causes typical metal contamination, increasing leakage current, one of the TFT characteristics.
저온 다결정 실리콘(Low temperature poly-Si, LTPS)의 개발은 액정디스플레이장치에 적용할 목적으로 수행되었으나, 최근 능동형 유기발광다이오드(AMOLED : Active Matrix Organic Light Emitting Diode)와 박막형 다결정 실리콘 태양전지의 등장과 더불어 개발의 필요성이 더 높아지고 있다.The development of low temperature poly-silicon (LTPS) has been carried out for the purpose of application to liquid crystal display devices. In addition, the need for development is increasing.
저렴하고 높은 생산성을 갖는 다결정 실리콘(poly-Si)의 제조방법은, 향후 시장에서 능동형 유기발광다이오드(AMOLED)가 많은 디스플레이 제품군에서 비정질 실리콘 박막트랜지스터 액정표시장치(a-Si TFT LCD)와 경쟁할 것이라는 점에서 중요하다. 다결정 실리콘의 제조방법은, 능동형 유기발광다이오드(AMOLED)가 태양전지(solar Cell)에서 결정질 웨이퍼(Wafer) 형태와 경쟁할 것이라는 점에서도 중요하다. 따라서, 제품의 생산 원가 및 시장 경쟁력은, 생산 기술이 안정화 단계에 접어든 비정질 실리콘 박막트랜지스터 액정표시장치(a-si TFT LCD) 및 결정질 웨이퍼 형태의 태양전지와 비교하여 얼마나 싼 가격에 안정적으로 다결정 실리콘을 제조할 수 있느냐에 달려있다.Inexpensive, high-productivity poly-Si fabrication methods will compete with amorphous silicon thin film transistor liquid crystal displays (a-Si TFT LCDs) in the display family with many active organic light emitting diodes (AMOLEDs) in the market. It is important in that it is. The method of manufacturing polycrystalline silicon is also important in that active organic light emitting diodes (AMOLEDs) will compete with crystalline wafer forms in solar cells. Therefore, the production cost and market competitiveness of the product are stable and polycrystalline at a lower price than the amorphous silicon thin film transistor liquid crystal display (a-si TFT LCD) and the crystalline wafer type solar cell where the production technology is stabilized. It depends on whether you can make silicon.
도 1에는 금속유도결정화법에 의해 비정질 실리콘으로부터 다결정 실리콘 박막을 얻는 제조공정이 도식적으로 도시되어 있다. 도 1을 참조하면 종래의 공정에서는 유리와 같은 기판(1)에 실리콘 산화물(SiO2)로 이루어진 완충층(2)을 형성하고 그 완충층(2)에 비정질 실리콘층(3)을 플라즈마 화학증착법(PECVD, Plasma Enhanced Chemical Vapor Deposition)으로 형성한 다음, 비정질 실리콘층(3)에 니켈(Ni)과 같은 금속을 스퍼터링(sputtering)하여 도포한 후에 약 700℃ 정도로 RTA(Rapid Thermal Annealing) 방식으로 열처리하여 비정질 실리콘층(3)으로부터 결정질 실리콘(4)이 형성되도록 한다. 그런데, 종래의 방식에 의하면 비정질 실리콘층(3)의 상부에 도포되는 금속의 양을 정밀하게 제어하기 어렵기 때문에 과잉으로 도포된 금속을 제거하여 주어야 하는 등의 불편한 문제점이 있다. 이러한 공정은 제조비용을 상승시킬 뿐 아니라 결정화된 실리콘의 품질에 나쁜 영향을 미친다.1 schematically shows a manufacturing process for obtaining a polycrystalline silicon thin film from amorphous silicon by a metal induction crystallization method. Referring to FIG. 1, in the conventional process, a buffer layer 2 made of silicon oxide (SiO 2 ) is formed on a substrate 1 such as glass, and an amorphous silicon layer 3 is formed on the buffer layer 2 by plasma chemical vapor deposition (PECVD). After forming by Plasma Enhanced Chemical Vapor Deposition, sputtering and coating a metal such as nickel (Ni) on the amorphous silicon layer (3), and then heat-treated by RTA (Rapid Thermal Annealing) at about 700 ℃ The crystalline silicon 4 is formed from the silicon layer 3. However, according to the conventional method, since it is difficult to precisely control the amount of the metal applied to the upper portion of the amorphous silicon layer 3, there is an inconvenience that it is necessary to remove the excessively applied metal. This process not only increases manufacturing costs but also adversely affects the quality of the crystallized silicon.
본 발명의 목적은 상기와 같은 문제점을 해소하기 위해 안출된 것으로서, 금속유도결정화법을 사용하여 다결정 실리콘 박막을 제조하는 방법에 있어서, 촉매금속의 양을 정밀하게 제어하고 낮은 온도에서 결정화가 가능하게 함으로써 효율적인 다결정 실리콘 박막의 제조방법을 제공함에 있다.An object of the present invention is to solve the above problems, in the method of manufacturing a polycrystalline silicon thin film using the metal induction crystallization method, precisely control the amount of catalyst metal and enable crystallization at low temperature By providing an efficient method for producing a polycrystalline silicon thin film.
상기의 목적을 달성하기 위해 본 발명에 따른 다결정 실리콘 박막의 제조방법은, 절연 기판상에 금속층을 형성시키는 금속층 형성단계;In order to achieve the above object, a method of manufacturing a polycrystalline silicon thin film according to the present invention includes: forming a metal layer on an insulating substrate;
상기 금속층을 열처리하여 그 금속층에 금속 산화막을 형성하는 산화막 형성단계;An oxide film forming step of forming a metal oxide film on the metal layer by heat-treating the metal layer;
상기 산화막 위에 비정질 실리콘층을 적층시키는 실리콘층 형성단계; 및A silicon layer forming step of laminating an amorphous silicon layer on the oxide film; And
상기 금속층 또는 상기 산화막의 금속 입자를 촉매로 하여 상기 비정질 실리콘층에서 결정질 실리콘이 생성되도록 열처리하는 결정화 단계;를 포함하는 점에 특징이 있다.And a crystallization step of heat treating the crystalline silicon in the amorphous silicon layer using the metal particles of the metal layer or the oxide film as a catalyst.
상기 기판은 상기 금속층과의 사이에 SiO2로 이루어진 완충층을 포함한 것이 바람직하다.Preferably, the substrate includes a buffer layer made of SiO 2 between the metal layer and the metal layer.
상기 금속층의 두께는 5Å 내지 2000Å이며, 상기 산화막의 두께는 1Å 내지 1500Å인 것이 바람직하다.It is preferable that the thickness of the said metal layer is 5 kPa-2000 kPa, and the thickness of the said oxide film is 1 kPa-1500 kPa.
상기 산화막 형성단계에서의 열처리 온도는 50℃ 내지 1000℃인 것이 바람직하다.The heat treatment temperature in the oxide film forming step is preferably 50 ℃ to 1000 ℃.
한편, 상기의 목적을 달성하기 위해 본 발명의 다른 실시예에 따른 다결정 실리콘 박막의 제조방법은, 절연 기판상에 금속층을 형성시키면서 그 금속층이 금속과 그 금속의 산화물이 혼재된 상태로 형성되는 산화막 형성단계;On the other hand, in order to achieve the above object, in the method of manufacturing a polycrystalline silicon thin film according to another embodiment of the present invention, while forming a metal layer on an insulating substrate, the metal layer is formed in a state in which the metal and the oxide of the metal is mixed. Forming step;
상기 산화막 위에 비정질 실리콘층을 적층시키는 실리콘층 형성단계; 및A silicon layer forming step of laminating an amorphous silicon layer on the oxide film; And
상기 산화막의 금속 입자를 촉매로 하여 상기 비정질 실리콘층에서 결정질 실리콘이 생성되도록 열처리하는 결정화 단계;를 포함하는 점에 특징이 있다.And a crystallization step of heat-treating the crystalline silicon in the amorphous silicon layer by using the metal particles of the oxide film as a catalyst.
한편, 상기의 목적을 달성하기 위해 본 발명의 또 다른 실시예에 따른 다결정 실리콘 박막의 제조방법은, 절연 기판상에 비정질 실리콘층을 적층시키는 실리콘층 형성단계;On the other hand, in order to achieve the above object, a method of manufacturing a polycrystalline silicon thin film according to another embodiment of the present invention, silicon layer forming step of laminating an amorphous silicon layer on an insulating substrate;
상기 실리콘층 위에 금속과 그 금속의 산화물이 혼재된 상태의 산화막을 형성하는 산화막 형성단계;An oxide film forming step of forming an oxide film in a state in which a metal and an oxide of the metal are mixed on the silicon layer;
상기 산화막 위에 금속층을 형성시키는 금속층 형성단계; A metal layer forming step of forming a metal layer on the oxide film;
상기 금속층 또는 상기 산화막의 금속 입자를 촉매로 하여 상기 비정질 실리콘층에서 결정질 실리콘이 생성되도록 열처리하는 결정화 단계;를 포함하는 점에 특징이 있다.And a crystallization step of heat treating the crystalline silicon in the amorphous silicon layer using the metal particles of the metal layer or the oxide film as a catalyst.
본 발명에 따른 다결정 실리콘 박막의 제조방법은, 비정질 실리콘층에 확산되어 그 비정질 실리콘층에서 실리콘 결정화의 핵 역할을 하는 금속 촉매의 양을 정밀하게 조절하여 효과적인 다결정 실리콘 결정화 박막을 제조할 수 있는 효과가 있다. 또한, 본 발명에 따른 다결정 실리콘 박막의 제조방법은 종래의 제조방법에 비하여 낮은 온도에서 결정화가 가능한 장점이 있다.The method for producing a polycrystalline silicon thin film according to the present invention is effective to manufacture an effective polycrystalline silicon crystallized thin film by precisely controlling the amount of the metal catalyst diffused in the amorphous silicon layer and acting as a nucleus of silicon crystallization in the amorphous silicon layer. There is. In addition, the manufacturing method of the polycrystalline silicon thin film according to the present invention has an advantage that can be crystallized at a lower temperature than the conventional manufacturing method.
도 1은 금속유도결정화법에 의한 종래의 다결정 실리콘 박막의 제조방법을 설명하기 위한 도면이다.1 is a view for explaining a conventional method for producing a polycrystalline silicon thin film by a metal induction crystallization method.
도 2는 발명의 바람직한 실시예에 따른 제조공정을 보여주는 도면이다.2 is a view showing a manufacturing process according to a preferred embodiment of the invention.
도 3은 도 2에 도시된 금속층 형성단계 후의 단면을 보여주는 도면이다.3 is a view showing a cross section after the metal layer forming step shown in FIG.
도 4는 도 2에 도시된 산화막 형성단계 후의 단면을 보여주는 도면이다.4 is a view showing a cross section after the oxide film forming step shown in FIG.
도 5는 도 2에 도시된 실리콘층 형성단계 후의 단면을 보여주는 도면이다.FIG. 5 is a view illustrating a cross section after the silicon layer forming step illustrated in FIG. 2.
도 6은 도 2에 도시된 결정화 단계 후에 다결정 실리콘이 기판에 형성된 모습을 도식적으로 보여주는 단면이다.6 is a cross-sectional view schematically showing how polycrystalline silicon is formed on a substrate after the crystallization step shown in FIG. 2.
도 7은 비정질 실리콘의 표면을 광학 현미경으로 본 사진이다. 7 is a photograph of the surface of amorphous silicon as seen under an optical microscope.
도 8은 도 7에 도시된 비정질 실리콘의 파수를 분석한 그래프이다.FIG. 8 is a graph analyzing the wave number of the amorphous silicon illustrated in FIG. 7.
도 9는 결정질 실리콘 웨이퍼의 표면을 광학 현미경으로 본 사진이다. 9 is a photograph of the surface of a crystalline silicon wafer viewed under an optical microscope.
도 10은 도 9에 도시된 실리콘 웨이퍼의 파수를 분석한 그래프이다.FIG. 10 is a graph analyzing the wave number of the silicon wafer illustrated in FIG. 9.
도 11은 종래의 금속유도결정화법에 의해 제조된 다결정 실리콘 박막의 표면을 광학 현미경으로 본 사진이다. FIG. 11 is a photograph of a surface of a polycrystalline silicon thin film manufactured by a conventional metal induction crystallization method viewed with an optical microscope. FIG.
도 12는 도 11에 도시된 다결정 실리콘 박막의 파수를 분석한 그래프이다.FIG. 12 is a graph analyzing the wave number of the polycrystalline silicon thin film illustrated in FIG. 11.
도 13은 본 발명에 의해 제조된 다결정 실리콘 박막의 표면을 광학 현미경으로 본 사진이다.Figure 13 is a photograph of the surface of the polycrystalline silicon thin film prepared according to the present invention with an optical microscope.
도 14는 도 13에 도시된 다결정 실리콘 박막의 파수를 분석한 그래프이다.FIG. 14 is a graph analyzing the wave number of the polycrystalline silicon thin film illustrated in FIG. 13.
도 15는 금속 산화막을 형성시키지 않고 결정화 단계를 거친 후의 실리콘 박막의 표면을 광학 현미경으로 본 사진이다.15 is a photograph of the surface of a silicon thin film after a crystallization step without forming a metal oxide film as seen under an optical microscope.
도 16은 도 15에 도시된 다결정 실리콘 박막의 파수를 분석한 그래프이다.FIG. 16 is a graph analyzing the wave number of the polycrystalline silicon thin film illustrated in FIG. 15.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
10...기판 20...완충층 10 substrate 20 buffer layer
30...금속층 40...산화막30 metal layer 40 oxide film
50...실리콘층 60...결정질 실리콘50 ... silicone layer 60 ... crystalline silicon
S1...금속층 형성단계 S2...산화막 형성단계S1 ... metal layer forming step S2 ... oxide film forming step
S3...실리콘층 형성단계 S4...결정화 단계S3 ... silicon layer forming step S4 ... crystallization step
이하, 본 발명에 따른 바람직한 실시예들을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2는 발명의 바람직한 실시예에 따른 제조공정을 보여주는 도면이다. 도 3은 도 2에 도시된 금속층 형성단계 후의 단면을 보여주는 도면이다. 도 4는 도 2에 도시된 산화막 형성단계 후의 단면을 보여주는 도면이다. 도 5는 도 2에 도시된 실리콘층 형성단계 후의 단면을 보여주는 도면이다. 도 6은 도 2에 도시된 결정화 단계 후에 다결정 실리콘이 기판에 형성된 모습을 도식적으로 보여주는 단면이다.2 is a view showing a manufacturing process according to a preferred embodiment of the invention. 3 is a view showing a cross section after the metal layer forming step shown in FIG. 4 is a view showing a cross section after the oxide film forming step shown in FIG. FIG. 5 is a view illustrating a cross section after the silicon layer forming step illustrated in FIG. 2. 6 is a cross-sectional view schematically showing how polycrystalline silicon is formed on a substrate after the crystallization step shown in FIG. 2.
도 1 내지 도 6을 참조하면, 본 발명의 바람직한 실시예에 따른 다결정 실리콘 박막의 제조방법(이하, "제조방법"이라 함)은 금속층 형성단계(S1)와, 산화막 형성단계(S2)와, 실리콘층 형성단계(S3)와, 결정화 단계(S4)를 포함하고 있다.1 to 6, a method of manufacturing a polycrystalline silicon thin film (hereinafter, referred to as a “manufacturing method”) according to a preferred embodiment of the present invention may include a metal layer forming step S1, an oxide film forming step S2, A silicon layer forming step S3 and a crystallization step S4 are included.
상기 금속층 형성단계(S1)에서는 유리와 같은 절연 기판(10)상에 니켈(Ni)과 같은 금속층(30)을 형성시킨다. 상기 기판(10)은 실리콘 산화물(SiO2)과 같은 물질로 이루어진 완충층(20)을 포함하고 있다. 상기 완충층(20)은 절연기능을 하기 위해 마련된 것이다. 또한, 상기 완충층(20)은 후술하는 결정화 단계(S4)에서 상기 기판(10)으로부터 후술하는 실리콘층(50)에 불순물이 확산되어 실리콘층(50)에 불순물이 오염되는 것을 방지하기 위해 마련된 것이다. 상기 금속층(30)은 플라즈마 화학증착(PECVD)과 같은 알려진 방법에 의해 수행될 수 있다. 상기 금속층(30)의 두께는 5Å 내지 2000Å인 것이 바람직하다. 상기 금속층(30)의 두께가 5Å 미만인 경우에는 너무 얇은 두께로 인해 공정 재현성 문제와 넓은 면적에 증착시 상기 금속층(30)의 균일성(uniformity)이 나빠지는 문제점이 있다. 한편, 상기 금속층(30)의 두께가 2000Å을 초과하는 경우에는 많은 금속이 침투하여 금속 오염문제가 유발되어 결정화된 실리콘층을 포함하는 디바이스(device)의 특성을 저하시키는 문제점이 있다. 상기 금속층 형성단계(S1) 후에 상기 금속층(30)의 일부분을 사진 식각 방법으로 제거하는 패터닝 단계를 실시할 수 있다. 필요에 따라 상기 패터닝 단계는 생략될 수 있다. 상기 패터닝 단계를 거치는 것은 결정질 실리콘의 성장핵을 균일하게 분포시키기 위한 것이다.In the metal layer forming step S1, a metal layer 30 such as nickel (Ni) is formed on an insulating substrate 10 such as glass. The substrate 10 includes a buffer layer 20 made of a material such as silicon oxide (SiO 2 ). The buffer layer 20 is provided to serve as an insulation function. In addition, the buffer layer 20 is provided to prevent impurities from being contaminated in the silicon layer 50 by the diffusion of impurities from the substrate 10 to the silicon layer 50 to be described later in the crystallization step (S4) to be described later. . The metal layer 30 may be performed by a known method such as plasma chemical vapor deposition (PECVD). It is preferable that the thickness of the said metal layer 30 is 5 kPa-2000 kPa. When the thickness of the metal layer 30 is less than 5 μs, there is a problem in that the reproducibility problem and the uniformity of the metal layer 30 deteriorate when the metal layer 30 is deposited in a large area due to the too thin thickness. On the other hand, when the thickness of the metal layer 30 exceeds 2000Å, a large amount of metal penetrates and causes a metal contamination problem, thereby lowering the characteristics of a device including a crystallized silicon layer. After the metal layer forming step S1, a patterning step of removing a portion of the metal layer 30 by a photolithography method may be performed. If necessary, the patterning step can be omitted. The patterning step is to uniformly distribute the growth nucleus of the crystalline silicon.
상기 산화막 형성단계(S2)에서는 상기 금속층(30)을 진공, 공기, 산소, 질소 중 어느 하나의 분위기하에서 열처리하여 상기 금속층(30)의 표면과 그 금속층(30)의 내부에 니켈 산화물(NiO 또는 Ni2O3)과 같은 금속 산화막(40)을 형성한다. 상기 금속 산화막(40)은 도 4에 도시된 바와 같이 상기 금속층(30)과 구별되도록 형성될 수도 있으으며, 경우에 따라서는 상기 금속층(30)과 상기 금속 산화막(40)은 혼재되어 하나의 적층구조를 형성할 수도 있다. 상기 금속층(30)과 상기 금속 산화막(40)이 혼재되어 있는 구조에서는 굳이 상기 금속층 형성단계(S1)을 독립적으로 실시할 필요가 없다. 즉 경우에 따라서 상기 산화막 형성단계(S2)에서 금속층을 형성하면서 열처리를 동시에 진행하여 금속층과 산화막이 혼재되도록 형성할 수 있다.In the oxide film forming step (S2), the metal layer 30 is heat-treated under an atmosphere of vacuum, air, oxygen, or nitrogen to form nickel oxide (NiO) or the like on the surface of the metal layer 30 and the metal layer 30. A metal oxide film 40 such as Ni 2 O 3 ) is formed. As shown in FIG. 4, the metal oxide film 40 may be formed to be distinguished from the metal layer 30. In some cases, the metal layer 30 and the metal oxide film 40 may be mixed to form a single layer. It may also form a structure. In the structure in which the metal layer 30 and the metal oxide film 40 are mixed, it is not necessary to independently perform the metal layer forming step S1. That is, in some cases, the metal layer and the oxide film may be mixed by simultaneously performing heat treatment while forming the metal layer in the oxide film forming step (S2).
상기 산화막(40)은 열처리 온도 범위가 50℃ 내지 1000℃에서 생성된다. 상기 산화막(40)이 형성되는 온도는 최저 50℃ 이며, 50℃ 미만의 온도에서는 니켈(Ni)의 산화물이 잘 형성되지 않는 문제점이 있다. 한편, 열처리 온도가 1000℃를 초과하는 경우에는 유리(glass)로 된 상기 기판(10)이 열충격에 의해 변형 또는 파손되는 문제점이 발생한다. 상기 산화막 형성단계(S2)에서의 열처리 방법은 고온 공정(furnace), 급속 열처리(RTA), 자외선(UV) 가열법 등을 사용할 수 있다. 상기 산화막(40)은 후술하는 결정화 단계(S4)에서 비정질 실리콘층(50)의 결정화의 핵으로 작용하는 촉매 금속의 확산시 활성화 에너지를 낮추어 주는 작용을 한다. 상기 산화막(40)의 두께는 1Å 내지 1500Å인 것이 바람직하다. 상기 산화막(40)의 두께가 1Å 미만인 경우에는 상기 산화막(40)이 너무 얇아 제 기능을 수행하지 못하는 문제점이 있다. 한편, 상기 산화막(40)의 두께가 1500Å을 초과하는 경우에는 상기 금속층(30)으로부터 촉매 금속이 침투하기 어려워지는 문제점이 있다. 상기 산화막(40)은 후술하는 결정화 단계(S4)에서 비정질 실리콘층(50)의 결정화의 핵으로 작용하는 촉매 금속의 확산시 활성화 에너지를 낮추어 주는 작용을 한다.The oxide film 40 is produced at a heat treatment temperature range of 50 ℃ to 1000 ℃. The temperature at which the oxide film 40 is formed is at least 50 ° C, and there is a problem that an oxide of nickel (Ni) is not formed well at a temperature of less than 50 ° C. On the other hand, when the heat treatment temperature exceeds 1000 ° C., the substrate 10 made of glass deforms or breaks due to thermal shock. The heat treatment method in the oxide film forming step (S2) may be a high temperature (furnace), rapid heat treatment (RTA), ultraviolet (UV) heating method and the like. The oxide film 40 serves to lower the activation energy during diffusion of the catalyst metal acting as a nucleus of the crystallization of the amorphous silicon layer 50 in the crystallization step S4 described later. It is preferable that the thickness of the said oxide film 40 is 1 kV-1500 kPa. If the thickness of the oxide film 40 is less than 1 mm, the oxide film 40 may be too thin to perform its function. On the other hand, when the thickness of the oxide film 40 exceeds 1500 kPa, there is a problem that it is difficult to penetrate the catalyst metal from the metal layer 30. The oxide film 40 serves to lower the activation energy during diffusion of the catalyst metal acting as a nucleus of the crystallization of the amorphous silicon layer 50 in the crystallization step S4 described later.
상기 실리콘층 형성단계(S3)에서는 상기 산화막(40) 위에 비정질 실리콘(A-Si)을 적층시켜 실리콘층(50)을 형성한다. 상기 실리콘층(50)을 형성시키는 방법은 공지된 플라즈마 화학증착법과 같은 방법을 사용하여 행해질 수 있다.In the silicon layer forming step (S3), the silicon layer 50 is formed by stacking amorphous silicon (A-Si) on the oxide film 40. The method of forming the silicon layer 50 may be performed using a method such as a known plasma chemical vapor deposition method.
상기 결정화 단계(S4)에서는 상기 금속층(30) 또는 상기 산화막(40)에 존재하는 금속 입자를 촉매로 하여 비정질로 이루어진 상기 실리콘층(50)에서 결정질 실리콘(60)이 생성되도록 열처리 한다. 상기 결정화 단계(S4)에서의 열처리는 RTA(Rapid Thermal Annealing) 장비를 사용하여 630℃에서 수행한다.In the crystallization step (S4), heat treatment is performed such that crystalline silicon 60 is generated in the silicon layer 50 made of amorphous by using metal particles present in the metal layer 30 or the oxide film 40 as a catalyst. The heat treatment in the crystallization step (S4) is performed at 630 ° C using Rapid Thermal Annealing (RTA) equipment.
이와 같은 제조방법에 의해 제조된 다결정 실리콘 박막의 결정화 상태를 분석하기 위하여 광학 현미경과 라만 분광기(Raman Spectroscopy)를 사용하여 결정립의 크기를 관찰하고 최대 강도를 가지는 파수를 분석하였다.In order to analyze the crystallization state of the polycrystalline silicon thin film manufactured by such a manufacturing method, the size of the crystal grains was observed by using an optical microscope and Raman Spectroscopy, and the wave number having the maximum intensity was analyzed.
도 7은 비정질 실리콘의 표면을 광학 현미경으로 본 사진이다. 도 8은 도 7에 도시된 비정질 실리콘의 파수를 분석한 그래프이다. 도 9는 결정질 실리콘 웨이퍼의 표면을 광학 현미경으로 본 사진이다. 도 10은 도 9에 도시된 실리콘 웨이퍼의 파수를 분석한 그래프이다. 도 11은 종래의 금속유도결정화법에 의해 제조된 다결정 실리콘 박막의 표면을 광학 현미경으로 본 사진이다. 도 12는 도 11에 도시된 다결정 실리콘 박막의 파수를 분석한 그래프이다. 도 13은 본 발명에 의해 제조된 다결정 실리콘 박막의 표면을 광학 현미경으로 본 사진이다. 도 14는 도 13에 도시된 다결정 실리콘 박막의 파수를 분석한 그래프이다.7 is a photograph of the surface of amorphous silicon as seen under an optical microscope. FIG. 8 is a graph analyzing the wave number of the amorphous silicon illustrated in FIG. 7. 9 is a photograph of the surface of a crystalline silicon wafer viewed under an optical microscope. FIG. 10 is a graph analyzing the wave number of the silicon wafer illustrated in FIG. 9. FIG. 11 is a photograph of a surface of a polycrystalline silicon thin film manufactured by a conventional metal induction crystallization method viewed with an optical microscope. FIG. FIG. 12 is a graph analyzing the wave number of the polycrystalline silicon thin film illustrated in FIG. 11. Figure 13 is a photograph of the surface of the polycrystalline silicon thin film prepared according to the present invention with an optical microscope. FIG. 14 is a graph analyzing the wave number of the polycrystalline silicon thin film illustrated in FIG. 13.
도 7 및 도 8을 참조하면 비정질 실리콘인 상기 실리콘층(50)은 파수 480cm-1에서 최대 강도(intensity)가 나타난다. 도 8에서 가로축은 파수(cm-1)를 나타내며 진동수에 대응하는 값이다. 파수(wave number)란 원자·분자·핵 분광학에서 빛의 진동수를 빛의 속도로 나누어서 단위 거리에 있는 파동의 수를 나타내는 진동수의 단위이다. 즉, 어떤 파의 진동수는 그리스 문자 ν(뉴)로 나타내는데 이는 광속 c를 파장 λ로 나눈 값과 같다. 즉 ν〓c/λ이다. 스펙트럼의 가시광선 영역에서 전형적인 스펙트럼 선은 5.8×10-5㎝의 파장이며 5.17×1014㎐의 진동수에 해당한다. 그런데 이와 같은 진동수가 너무 큰 값을 갖기 때문에 이 숫자를 광속으로 나누어서 크기를 작게 하는 것이 편리하다. 진동수를 광속으로 나누면 ν/c인데 이는 위 식에서 1/λ이다. 파장을 m단위로 재면 1/λ는 1m 내에서 발견되는 파의 수를 나타낸다. 파수는 대개 1/m, 즉 m-1와 1/㎝, 즉 ㎝-1의 단위로 측정한다. 7 and 8, the silicon layer 50, which is amorphous silicon, exhibits a maximum intensity at a wave number of 480 cm −1 . In FIG. 8, the horizontal axis represents a wave number (cm −1 ) and corresponds to a frequency. A wave number is a unit of frequency that represents the number of waves in a unit distance by dividing the frequency of light by the speed of light in atomic, molecular, and nuclear spectroscopy. In other words, the frequency of a wave is represented by the Greek letter ν (nu), which is equal to the luminous flux c divided by the wavelength λ. That is, ν〓c / λ. In the visible region of the spectrum, a typical spectral line is a wavelength of 5.8 × 10 −5 cm and corresponds to a frequency of 5.17 × 10 14 kHz. However, because such a frequency has a value that is too large, it is convenient to divide the number by the speed of light to reduce the size. The frequency divided by the speed of light is ν / c, which is 1 / λ in the above equation. When the wavelength is measured in m, 1 / λ represents the number of waves found within 1m. The wavenumber is usually measured in units of 1 / m, i.e. m- 1 and 1 / cm, i.e. cm- 1 .
도 8에서 세로축은 단위 시간당 측정되는 파수의 합으로서 강도(intensity, CPS, Count Per Second)에 해당하는 값이다. 도 10, 도 12, 도 14의 가로축과 세로축의 단위는 도 8과 동일하다. 이에 반하여 정형적인 결정질 실리콘인 실리콘 웨이퍼는 도 9 및 도 10에 도시된 바와 같이 파수 520cm-1에서 최대 강도가 나타나고 있다. 도 11 및 도 12는 종래의 금속유도결정화법에 의해 제조된 다결정 실리콘 박막의 표면사진과 파수 분석 그래프를 보여주고 있다. 도 11 및 도 12를 참조하면 도 9 및 도 10에 도시된 결정질 실리콘 웨이퍼와 비교하여 유사한 파수에서 최대 강도가 나타나고 있다. 그런데, 도 11에 도시된 실리콘 박막의 표면에 대한 광학 현미경 사진은 1000배 확대된 것으로서 비교적 결정립의 크기가 작은 것을 알 수 있다.In FIG. 8, the vertical axis is a sum of waves measured per unit time and corresponds to intensity (CPS, Count Per Second). The units of the horizontal axis and the vertical axis of FIGS. 10, 12, and 14 are the same as those of FIG. 8. In contrast, silicon wafers, which are typical crystalline silicon, exhibit maximum strength at a wavenumber of 520 cm −1 as shown in FIGS. 9 and 10. 11 and 12 show surface photographs and wave number analysis graphs of a polycrystalline silicon thin film manufactured by a conventional metal induction crystallization method. Referring to FIGS. 11 and 12, the maximum strength is shown at a similar frequency compared to the crystalline silicon wafers shown in FIGS. 9 and 10. By the way, it can be seen that the optical micrograph of the surface of the silicon thin film shown in Fig. 11 is magnified 1000 times and the size of the crystal grains is relatively small.
한편, 본 발명에 의해 제조된 다결정 실리콘 박막의 광학 현미경 사진과 파수 분석 그래프가 각각 도 13과 도 14에 도시되어 있다. 도 14를 참조하면 본 발명에 의해 제조된 다결정 실리콘 박막에서 최대 강도를 나타내는 파수는 도 10에 도시된 결정질 실리콘 웨이퍼와 같이 잘 나타나고 있는 것을 알 수 있다. 또한, 도 13은 1000배 확대된 광학 현미경 사진인데, 도 13과 도 11을 비교하면, 본 발명에 의해 제조된 다결정 실리콘 박막의 결정립이 종래의 방법으로 제조된 다결정 실리콘 박막의 결정립 보다 훨씬 큰 것을 알 수 있다.Meanwhile, optical micrographs and wave number analysis graphs of the polycrystalline silicon thin film manufactured by the present invention are shown in FIGS. 13 and 14, respectively. Referring to FIG. 14, it can be seen that the wave number representing the maximum strength in the polycrystalline silicon thin film manufactured by the present invention is well represented as in the crystalline silicon wafer shown in FIG. 10. In addition, FIG. 13 is an optical micrograph of 1000 times magnification. Compared with FIG. 13 and FIG. 11, the grains of the polycrystalline silicon thin film manufactured by the present invention are much larger than those of the polycrystalline silicon thin film manufactured by the conventional method. Able to know.
본 발명의 효과를 설명하기 위한 자료로서 상기 산화막(40)을 형성하지 않은 경우에 비정질 실리콘의 결정화 정도를 보여주는 도면이 도 15 및 도 16에 도시되어 있다. 도 15는 절연 기판(10)에 니켈(Ni)과 같은 금속층(30)을 형성하고 상기 산화막(40)을 형성하지 않고 상기 금속층(30)위에 비정질 실리콘층(50)을 적층한 후 열처리한 후의 그 실리콘층(50)의 결정화 여부를 관찰한 광학 현미경 사진(배율 X1000)이다. 또한, 도 16은 도 15에 도시된 실리콘층(50)의 결정화 여부를 확인하기 위하여 도 15에 도시된 실리콘 박막의 파수를 분석한 그래프이다. 도 16을 참조하면 최대의 강도를 보여주는 파수가 480cm-1로서 도 8에 도시된 비정질 실리콘 박막과 동일하다. 따라서 상기 산화막(40)이 존재하지 않는 경우 즉 금속의 산화물이 존재하지 않는 경우에는 결정화가 잘 일어나지 않는다는 것을 알 수 있다.15 and 16 show the degree of crystallization of amorphous silicon when the oxide film 40 is not formed as a material for explaining the effects of the present invention. FIG. 15 illustrates that after forming a metal layer 30 such as nickel (Ni) on an insulating substrate 10 and laminating an amorphous silicon layer 50 on the metal layer 30 without forming the oxide film 40, the heat treatment is performed. It is an optical microscope photograph (magnification X1000) which observed whether the silicon layer 50 crystallized. In addition, FIG. 16 is a graph in which the wave number of the silicon thin film illustrated in FIG. 15 is analyzed to determine whether the silicon layer 50 illustrated in FIG. 15 is crystallized. Referring to FIG. 16, the wave number showing the maximum intensity is 480 cm −1, which is the same as the amorphous silicon thin film shown in FIG. 8. Therefore, it can be seen that crystallization does not occur well when the oxide film 40 does not exist, that is, when there is no metal oxide.
이와 같은 실험결과로부터 본 발명에 따른 다결정 실리콘 박막의 제조방법이 종래의 제조방법보다 우수한 것을 알 수 있다. 또한, 본 발명에 따른 다결정 실리콘 박막의 제조방법은 종래의 제조방법보다 낮은 온도에서 결정화가 가능한 장점이 있다. 본 발명에 따른 다결정 실리콘 박막의 제조방법은 비정질 실리콘으로부터 결정질 실리콘으로 변태되는 반응의 핵인 촉매 금속을 비정질 실리콘층의 하부에 배치함으로써 촉매 금속의 양을 사전에 정밀하게 제어한 다음 비정질 실리콘층에 확산되도록 함으로써 불순물이 유입되는 것을 방지하고 활성화 에너지를 낮추는 장점이 있다.From the experimental results, it can be seen that the manufacturing method of the polycrystalline silicon thin film according to the present invention is superior to the conventional manufacturing method. In addition, the manufacturing method of the polycrystalline silicon thin film according to the present invention has the advantage that it can be crystallized at a lower temperature than the conventional manufacturing method. In the method for producing a polycrystalline silicon thin film according to the present invention, by precisely controlling the amount of the catalyst metal in advance by disposing the catalyst metal, which is a nucleus of the reaction that is transformed from amorphous silicon into crystalline silicon, in the lower part of the amorphous silicon layer, it is then diffused into the amorphous silicon layer. By doing so, there is an advantage of preventing the inflow of impurities and lowering the activation energy.
한편, 지금까지 상술한 바와 같이 비정실 실리콘층의 하부에 산화막을 형성한 후에 열처리에 의하여 상기 비정질 실리콘층에서 결정질 실리콘을 생성하도록 할 수도 있으나, 이와는 달리 종래의 프로세스를 변형하여 소기의 목적을 달성할 수 있다. 즉, 본 발명의 변형된 실시예로서, 절연 기판상에 비정질 실리콘층을 적층시키는 실리콘층 형성단계 후에, 상기 실리콘층 위에 금속과 그 금속의 산화물이 혼재된 상태의 산화막을 형성하는 산화막 형성단계를 실행하고, 상기 산화막 위에 금속층을 형성시키는 금속층 형성단계를 실행한 후에, 상기 금속층 또는 상기 산화막의 금속 입자를 촉매로 하여 상기 비정질 실리콘층에서 결정질 실리콘이 생성되도록 열처리하는 결정화 단계;를 포함하도록 할 수 있다. 즉, 본 발명의 핵심적인 공정이 비정질 실리콘층에 인접하는 산화막을 형성한 후에 열처리를 하는 것이므로, 산화막을 비정질 실리콘층 위에 형성하도록 하여도 본 발명의 목적을 달성할 수 있다.Meanwhile, as described above, the crystalline silicon may be generated in the amorphous silicon layer by heat treatment after the oxide film is formed under the amorphous silicon layer. Alternatively, the conventional process may be modified to achieve a desired purpose. can do. That is, as a modified embodiment of the present invention, after the silicon layer forming step of laminating an amorphous silicon layer on an insulating substrate, an oxide film forming step of forming an oxide film in a state in which a metal and an oxide of the metal is mixed on the silicon layer And performing a metal layer forming step of forming a metal layer on the oxide film, and then performing a heat treatment to produce crystalline silicon in the amorphous silicon layer using the metal layer or metal particles of the oxide film as a catalyst. have. That is, since the core process of the present invention is heat treatment after forming the oxide film adjacent to the amorphous silicon layer, the object of the present invention can be achieved even by forming the oxide film on the amorphous silicon layer.
한편, 다른 실시예에 의하면 도 2 내지 16을 참조하여 설명한 실시 예를 변형하여 상기 금속층 형성단계, 상기 산화막 형성단계를 순차적으로 2회 실시한 후에 상기 실리콘층 형성단계를 실시할 수도 있다. 즉, 변형된 실시 예에 의한 다결정 실리콘 박막의 제조방법은, 절연 기판상에 금속층을 형성시키는 제1금속층 형성단계; 상기 제1금속층을 열처리하여 그 제1금속층에 금속 산화막을 형성하거나, 상기 제1금속층의 표면에 금속 산화막을 증착하여 금속 산화막을 형성하는 제1산화막 형성단계; 상기 제1산화막 형성단계에서 형성된 금속 산화막 위에 제2금속층을 다시 형성하고 그 제2금속층을 열처리하여 그 제2금속층의 표면에 금속 산화막을 형성하거나 그 제2금속층의 표면에 금속 산화막을 증착하여 금속 산화막을 형성하는 제2산화막 형성단계; 상기 제2산화막 형성단계에서 형성된 산화막 위에 비정질 실리콘층을 적층시키는 실리콘층 형성단계; 및 상기 제1금속층과 상기 제2금속층 또는 상기 제1산화막 형성단계 및 상기 제2산화막 형성단계에서 형성된 금속 산화막의 금속 입자를 촉매로 하여 상기 비정질 실리콘층에서 결정질 실리콘이 생성되도록 열처리하는 결정화 단계;를 포함한다.Meanwhile, according to another embodiment, the embodiment described with reference to FIGS. 2 to 16 may be modified to sequentially perform the metal layer forming step and the oxide film forming step twice, followed by the silicon layer forming step. That is, the method of manufacturing a polycrystalline silicon thin film according to the modified embodiment includes: forming a first metal layer on an insulating substrate; Forming a metal oxide film on the first metal layer by heat-treating the first metal layer, or forming a metal oxide film by depositing a metal oxide film on the surface of the first metal layer; The second metal layer is formed again on the metal oxide film formed in the first oxide film forming step, and the second metal layer is heat-treated to form a metal oxide film on the surface of the second metal layer or by depositing a metal oxide film on the surface of the second metal layer. A second oxide film forming step of forming an oxide film; A silicon layer forming step of laminating an amorphous silicon layer on the oxide film formed in the second oxide film forming step; And a crystallization step of heat-treating the crystalline silicon in the amorphous silicon layer using the metal particles of the first metal layer and the second metal layer or the metal oxide film formed in the first oxide film forming step and the second oxide film forming step as catalysts. It includes.
이상, 바람직한 실시 예들을 들어 본 발명에 대해 설명하였으나, 본 발명이 그러한 예들에 의해 한정되는 것은 아니며, 본 발명의 기술적 사상을 벗어나지 않는 범주 내에서 다양한 형태의 실시예가 구체화될 수 있을 것이다.The present invention has been described above with reference to preferred embodiments, but the present invention is not limited to the examples, and various forms of embodiments may be embodied without departing from the technical spirit of the present invention.
상기의 목적을 달성하기 위해 본 발명에 따른 다결정 실리콘 박막의 제조방법은, 절연 기판상에 금속층을 형성시키는 금속층 형성단계;In order to achieve the above object, a method of manufacturing a polycrystalline silicon thin film according to the present invention includes: forming a metal layer on an insulating substrate;
상기 금속층을 열처리하여 그 금속층에 금속 산화막을 형성하는 산화막 형성단계;An oxide film forming step of forming a metal oxide film on the metal layer by heat-treating the metal layer;
상기 산화막 위에 비정질 실리콘층을 적층시키는 실리콘층 형성단계; 및A silicon layer forming step of laminating an amorphous silicon layer on the oxide film; And
상기 금속층 또는 상기 산화막의 금속 입자를 촉매로 하여 상기 비정질 실리콘층에서 결정질 실리콘이 생성되도록 열처리하는 결정화 단계;를 포함하는 점에 특징이 있다.And a crystallization step of heat treating the crystalline silicon in the amorphous silicon layer using the metal particles of the metal layer or the oxide film as a catalyst.
상기 기판은 상기 금속층과의 사이에 SiO2로 이루어진 완충층을 포함한 것이 바람직하다.Preferably, the substrate includes a buffer layer made of SiO 2 between the metal layer and the metal layer.
상기 금속층의 두께는 5Å 내지 2000Å이며, 상기 산화막의 두께는 1Å 내지 1500Å인 것이 바람직하다.It is preferable that the thickness of the said metal layer is 5 kPa-2000 kPa, and the thickness of the said oxide film is 1 kPa-1500 kPa.
상기 산화막 형성단계에서의 열처리 온도는 50℃ 내지 1000℃인 것이 바람직하다.The heat treatment temperature in the oxide film forming step is preferably 50 ℃ to 1000 ℃.
한편, 상기의 목적을 달성하기 위해 본 발명의 다른 실시예에 따른 다결정 실리콘 박막의 제조방법은, 절연 기판상에 금속층을 형성시키면서 그 금속층이 금속과 그 금속의 산화물이 혼재된 상태로 형성되는 산화막 형성단계;On the other hand, in order to achieve the above object, in the method of manufacturing a polycrystalline silicon thin film according to another embodiment of the present invention, while forming a metal layer on an insulating substrate, the metal layer is formed in a state in which the metal and the oxide of the metal is mixed. Forming step;
상기 산화막 위에 비정질 실리콘층을 적층시키는 실리콘층 형성단계; 및A silicon layer forming step of laminating an amorphous silicon layer on the oxide film; And
상기 산화막의 금속 입자를 촉매로 하여 상기 비정질 실리콘층에서 결정질 실리콘이 생성되도록 열처리하는 결정화 단계;를 포함하는 점에 특징이 있다.And a crystallization step of heat-treating the crystalline silicon in the amorphous silicon layer by using the metal particles of the oxide film as a catalyst.
한편, 상기의 목적을 달성하기 위해 본 발명의 또 다른 실시예에 따른 다결정 실리콘 박막의 제조방법은, 절연 기판상에 비정질 실리콘층을 적층시키는 실리콘층 형성단계;On the other hand, in order to achieve the above object, a method of manufacturing a polycrystalline silicon thin film according to another embodiment of the present invention, silicon layer forming step of laminating an amorphous silicon layer on an insulating substrate;
상기 실리콘층 위에 금속과 그 금속의 산화물이 혼재된 상태의 산화막을 형성하는 산화막 형성단계;An oxide film forming step of forming an oxide film in a state in which a metal and an oxide of the metal are mixed on the silicon layer;
상기 산화막 위에 금속층을 형성시키는 금속층 형성단계; A metal layer forming step of forming a metal layer on the oxide film;
상기 금속층 또는 상기 산화막의 금속 입자를 촉매로 하여 상기 비정질 실리콘층에서 결정질 실리콘이 생성되도록 열처리하는 결정화 단계;를 포함하는 점에 특징이 있다.And a crystallization step of heat treating the crystalline silicon in the amorphous silicon layer using the metal particles of the metal layer or the oxide film as a catalyst.
한편, 상기의 목적을 달성하기 위해 본 발명의 또 다른 실시예에 따른 다결정 실리콘 박막의 제조방법은, 절연 기판상에 금속층을 형성시키는 제1금속층 형성단계; On the other hand, to achieve the above object, a method of manufacturing a polycrystalline silicon thin film according to another embodiment of the present invention, the first metal layer forming step of forming a metal layer on an insulating substrate;
상기 제1금속층을 열처리하여 그 제1금속층에 금속 산화막을 형성하거나, 상기 제1금속층의 표면에 금속 산화막을 증착하여 금속 산화막을 형성하는 제1산화막 형성단계; Forming a metal oxide film on the first metal layer by heat-treating the first metal layer, or forming a metal oxide film by depositing a metal oxide film on the surface of the first metal layer;
상기 제1산화막 형성단계에서 형성된 금속 산화막 위에 제2금속층을 다시 형성하고 그 제2금속층을 열처리하여 그 제2금속층의 표면에 금속 산화막을 형성하거나 그 제2금속층의 표면에 금속 산화막을 증착하여 금속 산화막을 형성하는 제2산화막 형성단계;The second metal layer is formed again on the metal oxide film formed in the first oxide film forming step, and the second metal layer is heat-treated to form a metal oxide film on the surface of the second metal layer or by depositing a metal oxide film on the surface of the second metal layer. A second oxide film forming step of forming an oxide film;
상기 제2산화막 형성단계에서 형성된 산화막 위에 비정질 실리콘층을 적층시키는 실리콘층 형성단계; 및A silicon layer forming step of laminating an amorphous silicon layer on the oxide film formed in the second oxide film forming step; And
상기 제1금속층과 상기 제2금속층 또는 상기 제1산화막 형성단계 및 상기 제2산화막 형성단계에서 형성된 금속 산화막의 금속 입자를 촉매로 하여 상기 비정질 실리콘층에서 결정질 실리콘이 생성되도록 열처리하는 결정화 단계;를 포함하는 점에 특징이 있다.A crystallization step of heat-treating the crystalline silicon in the amorphous silicon layer using the metal particles of the first metal layer and the second metal layer or the metal oxide film formed in the first oxide film forming step and the second oxide film forming step as catalysts; It is characteristic in that it includes.

Claims (6)

  1. 절연 기판상에 금속층을 형성시키는 금속층 형성단계;A metal layer forming step of forming a metal layer on the insulating substrate;
    상기 금속층을 열처리하여 그 금속층에 금속 산화막을 형성하는 산화막 형성단계;An oxide film forming step of forming a metal oxide film on the metal layer by heat-treating the metal layer;
    상기 산화막 위에 비정질 실리콘층을 적층시키는 실리콘층 형성단계; 및A silicon layer forming step of laminating an amorphous silicon layer on the oxide film; And
    상기 금속층 또는 상기 산화막의 금속 입자를 촉매로 하여 상기 비정질 실리콘층에서 결정질 실리콘이 생성되도록 열처리하는 결정화 단계;를 포함하는 것을 특징으로 하는 다결정 실리콘 박막의 제조방법.And a crystallization step of heat-treating the crystalline silicon in the amorphous silicon layer using the metal particles of the metal layer or the oxide film as a catalyst.
  2. 제1항에 있어서,The method of claim 1,
    상기 금속층의 두께는 5Å 내지 2000Å이며, 상기 산화막의 두께는 1Å 내지 1500Å인 것을 특징으로 하는 다결정 실리콘 박막의 제조방법.The metal layer has a thickness of 5 kPa to 2000 kPa, and the oxide film has a thickness of 1 kPa to 1500 kPa.
  3. 제2항에 있어서,The method of claim 2,
    상기 산화막 형성단계에서의 열처리 온도는 50℃ 내지 1000℃인 것을 특징으로 하는 다결정 실리콘 박막의 제조방법.The heat treatment temperature in the oxide film forming step is a method for producing a polycrystalline silicon thin film, characterized in that 50 ℃ to 1000 ℃.
  4. 제1항에 있어서,The method of claim 1,
    상기 금속층 형성단계에서 형성된 금속층의 일부분을 사진 식각 공정으로 제거하는 패터닝 단계;A patterning step of removing a portion of the metal layer formed in the metal layer forming step by a photolithography process;
    상기 패터닝 단계를 거친 금속층을 열처리하여 그 금속층의 표면에 금속 산화막을 형성하거나, 상기 금속층의 표면에 금속 산화막을 증착하여 금속 산화막을 형성하는 금속 산화막 형성단계;를 수행하는 것을 특징으로 하는 다결정 실리콘 박막의 제조방법.A metal oxide film forming step of forming a metal oxide film on the surface of the metal layer by heat-treating the patterned metal layer or by depositing a metal oxide film on the surface of the metal layer; Manufacturing method.
  5. 절연 기판상에 금속층을 형성시키면서 그 금속층이 금속과 그 금속의 산화물이 혼재된 상태로 형성되는 산화막 형성단계;Forming an metal layer on the insulating substrate and forming the metal layer in a state in which the metal and the oxide of the metal are mixed;
    상기 산화막 위에 비정질 실리콘층을 적층시키는 실리콘층 형성단계; 및A silicon layer forming step of laminating an amorphous silicon layer on the oxide film; And
    상기 산화막의 금속 입자를 촉매로 하여 상기 비정질 실리콘층에서 결정질 실리콘이 생성되도록 열처리하는 결정화 단계;를 포함하는 것을 특징으로 하는 다결정 실리콘 박막의 제조방법.And a crystallization step of heat-treating the crystalline silicon in the amorphous silicon layer using the metal particles of the oxide film as a catalyst.
  6. 절연 기판상에 금속층을 형성시키는 제1금속층 형성단계;Forming a first metal layer on the insulating substrate;
    상기 제1금속층을 열처리하여 그 제1금속층에 금속 산화막을 형성하거나, 상기 제1금속층의 표면에 금속 산화막을 증착하여 금속 산화막을 형성하는 제1산화막 형성단계;Heat-treating the first metal layer to form a metal oxide film on the first metal layer, or forming a metal oxide film by depositing a metal oxide film on the surface of the first metal layer to form a metal oxide film;
    상기 제1산화막 형성단계에서 형성된 금속 산화막 위에 제2금속층을 다시 형성하고 그 제2금속층을 열처리하여 그 제2금속층의 표면에 금속 산화막을 형성하거나 그 제2금속층의 표면에 금속 산화막을 증착하여 금속 산화막을 형성하는 제2산화막 형성단계;The second metal layer is formed on the metal oxide film formed in the first oxide film forming step, and the second metal layer is heat-treated to form a metal oxide film on the surface of the second metal layer or by depositing a metal oxide film on the surface of the second metal layer. A second oxide film forming step of forming an oxide film;
    상기 제2산화막 형성단계에서 형성된 산화막 위에 비정질 실리콘층을 적층시키는 실리콘층 형성단계; 및A silicon layer forming step of laminating an amorphous silicon layer on the oxide film formed in the second oxide film forming step; And
    상기 제1금속층과 상기 제2금속층 또는 상기 제1산화막 형성단계 및 상기 제2산화막 형성단계에서 형성된 금속 산화막의 금속 입자를 촉매로 하여 상기 비정질 실리콘층에서 결정질 실리콘이 생성되도록 열처리하는 결정화 단계;를 포함하는 것을 특징으로 하는 다결정 실리콘 박막의 제조방법.A crystallization step of heat-treating the crystalline silicon in the amorphous silicon layer using the metal particles of the first metal layer and the second metal layer or the metal oxide film formed in the first oxide film forming step and the second oxide film forming step as a catalyst; Method for producing a polycrystalline silicon thin film comprising a.
PCT/KR2010/004369 2010-07-06 2010-07-06 Method for manufacturing a polycrystalline silicon thin film WO2012005389A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/KR2010/004369 WO2012005389A1 (en) 2010-07-06 2010-07-06 Method for manufacturing a polycrystalline silicon thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/KR2010/004369 WO2012005389A1 (en) 2010-07-06 2010-07-06 Method for manufacturing a polycrystalline silicon thin film

Publications (1)

Publication Number Publication Date
WO2012005389A1 true WO2012005389A1 (en) 2012-01-12

Family

ID=45441352

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2010/004369 WO2012005389A1 (en) 2010-07-06 2010-07-06 Method for manufacturing a polycrystalline silicon thin film

Country Status (1)

Country Link
WO (1) WO2012005389A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101396489B1 (en) 2012-05-08 2014-05-19 세진이노테크(주) Method for manufacturing silicon based negative active material, negative active material for lithium recharable battery and lithium rechargable battery using the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050275019A1 (en) * 2004-06-09 2005-12-15 Jin-Wook Seo Thin film transistor and method of fabricating the same
KR100659581B1 (en) * 2005-12-08 2006-12-20 한국전자통신연구원 A method for crystallizing silicon and a thin film transistor manufactured by the crystallizing method and a method for manufacturing the same
KR100870111B1 (en) * 2007-03-15 2008-11-25 (주)실리콘화일 Crystal growth method of semiconductor
KR20100119362A (en) * 2009-04-30 2010-11-09 노코드 주식회사 Manufacturing method for thin film of poly-crystalline silicon

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050275019A1 (en) * 2004-06-09 2005-12-15 Jin-Wook Seo Thin film transistor and method of fabricating the same
KR100659581B1 (en) * 2005-12-08 2006-12-20 한국전자통신연구원 A method for crystallizing silicon and a thin film transistor manufactured by the crystallizing method and a method for manufacturing the same
KR100870111B1 (en) * 2007-03-15 2008-11-25 (주)실리콘화일 Crystal growth method of semiconductor
KR20100119362A (en) * 2009-04-30 2010-11-09 노코드 주식회사 Manufacturing method for thin film of poly-crystalline silicon

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101396489B1 (en) 2012-05-08 2014-05-19 세진이노테크(주) Method for manufacturing silicon based negative active material, negative active material for lithium recharable battery and lithium rechargable battery using the same
US9660254B2 (en) 2012-05-08 2017-05-23 Unist (Ulsan National Institute Of Science And Technology) Method for producing silicon-based negative electrode active material, negative electrode active material for lithium secondary battery, and lithium secondary battery comprising same

Similar Documents

Publication Publication Date Title
KR100437296B1 (en) Thin film transistor and its manufacturing method
KR20030060403A (en) crystallization method of amorphous silicon
WO2012097563A1 (en) Method of manufacturing thin film transistor
WO2010134691A2 (en) Method for manufacturing polycrystalline silicon thin film
CN102969250A (en) Preparation method of LTPS (Low Temperature Poly Silicon) thin film and thin film transistor, array substrate and display device
WO2016058151A1 (en) Excimer laser annealing device and method for using same
WO2011149215A2 (en) Method for preparing polycrystalline silicon thin film
WO2012005389A1 (en) Method for manufacturing a polycrystalline silicon thin film
KR100859761B1 (en) polycrystal silicon thin film and method for manufacturing thereof
KR101011806B1 (en) Manufacturing method for thin film of poly-crystalline silicon
KR101044415B1 (en) Manufacturing method for thin film of poly-crystalline silicon
KR101118275B1 (en) Manufacturing method for thin film of poly-crystalline silicon
WO2009131379A2 (en) Polycrystalline silicon film, a thin-film transistor comprising the same, and a production method thereof
KR20130060002A (en) Manufacturing method for thin film of poly-crystalline material
CN108231794B (en) Preparation method of array substrate and array substrate
KR101057147B1 (en) Manufacturing method for thin film of poly-crystalline silicon
WO2017043899A1 (en) Method for crystallizing amorphous silicon by means of plasma
WO2010030068A1 (en) Method for phase transition of amorphous material
KR101079302B1 (en) Manufacturing method for thin film of poly-crystalline silicon
KR101131216B1 (en) Manufacturing method for thin film of poly-crystalline silicon
KR101095621B1 (en) Manufacturing method for thin film of poly-crystalline silicon
KR101131217B1 (en) Manufacturing method for thin film of poly-crystalline silicon
KR101123373B1 (en) Manufacturing method for thin film of poly-crystalline silicon
KR101117291B1 (en) Manufacturing method for thin film of poly-crystalline silicon
KR101281132B1 (en) Manufacturing method for thin film of poly-crystalline material

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10854463

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 16/04/2013)

122 Ep: pct application non-entry in european phase

Ref document number: 10854463

Country of ref document: EP

Kind code of ref document: A1