KR100655138B1 - A fabrication method of semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a butting contact hole for connecting a gate together with an impurity region. SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device which can improve the reliability of an element by preventing shorting of wiring from a short circuit between the gates of adjacent transistors. The present invention provides a process of forming first and second gates on a semiconductor substrate and forming impurity regions in exposed portions, and a first etch stop layer and an interlayer insulating layer covering the first and second gates on the semiconductor substrate. Forming a second etch stop layer patterned on one side of the second gate on the interlayer insulating layer, and simultaneously exposing the impurity region and a predetermined portion of the first gate. Forming a contact hole, depositing polysilicon to cover the second etch stop layer and fill the contact hole on the interlayer insulating layer, and patterning the polysilicon to overlap with a portion corresponding to the contact hole. And forming a plug in contact with a wiring, such as the first and gate and impurity regions.

Butting contacts, polysilicon, plugs, etch stops

Description

A fabrication method of semiconductor device             

1A to 1C are manufacturing process diagrams of a semiconductor device according to the prior art.

2A to 2D are manufacturing process diagrams of a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 33 gate oxide film

35, 36: gate 37: side wall

39: impurity region 41: first etch stop layer

43: interlayer insulating layer 45: second etch stop layer

47: contact hole 49: plug

51: wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a butting contact hole for connecting a gate together with an impurity region.

Semiconductor memory devices can be classified into random access memory (RAM) and read only memory (ROM). In particular, the RAM is divided into a dynamic RAM (hereinafter referred to as DRAM) and a static RAM.

In the DRAM, one unit cell is composed of one transistor and one capacitor. The SRAM is composed of six transistors, or four transistors and two load resistors.

SRAMs have a larger number of contacts than DRAMs, and the transistors constituting the load resistors have butting contact holes to which gates and impurity regions are simultaneously connected.

1A to 1C are manufacturing process diagrams of a semiconductor device according to the prior art.

Referring to FIG. 1A, a gate oxide film 13 is formed on a semiconductor substrate 11. Then, polycrystalline silicon doped with impurities on the gate oxide layer 13 is deposited by chemical vapor deposition (hereinafter, referred to as CVD), and the photolithography (photolithograpy) method is used to expose the semiconductor substrate 11. Patterned to form gates 15 and 16.

N-type impurities are ion-implanted into the exposed portions of the semiconductor substrate 11 using the gates 15 and 16 as ion implantation masks to form impurity regions 19 used as source and drain regions.

Sidewalls 17 are formed on the sides of the gates 15 and 16. In the above, after the insulating material such as silicon oxide is deposited on the semiconductor substrate 11 to cover the gates 15 and 16 on the semiconductor substrate 11, a reactive ion etching (hereinafter referred to as RIE) method, etc. It is formed by etching back so that the impurity region 19 is exposed.

Referring to FIG. 1B, silicon nitride is deposited on the semiconductor substrate 11 to cover the gates 15 and 16 and the sidewalls 17 to form the first etch stop layer 21. In addition, a silicon oxide such as USG (Undoped Silicate Glass), PSG (Phospho Silicate Glass), BPSG (Borophospho Silicate Glass) or TEOS (Tetra Eethyl Ortho Silicate) is deposited on the first etch stop layer 21 or SOG (Sipn On). The interlayer insulating layer 23 is formed by coating with glass.

The interlayer insulating layer 23 and the first etch stop layer 21 are patterned by photolithography to form contact holes 25 exposing the impurity regions 19. In this case, the contact hole 25 exposes not only the impurity region 19 but also the gate 15.

Referring to FIG. 1C, polycrystalline silicon doped with impurities to fill the inside of the contact hole 25 on the interlayer insulating layer 23 is deposited by CVD. Then, the polysilicon is patterned by a photolithography method to form the wiring 29. At this time, the wiring 29 is formed to overlap the portion corresponding to the contact hole 25. Therefore, the polysilicon remains in the contact hole 23 to form the plug 27. In the above, the plug 27 is in contact with the exposed portion of the upper surface of the gate 15 as well as the impurity region 19 to make a butt contact. Since the plug 27 makes a butt contact with the impurity region 19 and the gate 15, the size of the cell can be reduced.                         

However, in the manufacturing method of the semiconductor device according to the prior art, as the design rule of the semiconductor device becomes strict, the gap between the gate and the gate of the adjacent transistor is reduced. Therefore, there is a problem in that the gates of adjacent transistors are also exposed and shorted by misalignment when forming contact holes for making butting contacts.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device which can improve the reliability of the device by preventing the butt contact plug from being shorted to the gates of adjacent transistors.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes forming a first and a second gate on a semiconductor substrate and forming an impurity region in an exposed portion, and forming the first and second gates on the semiconductor substrate. Continuously forming a first etch stop layer and an interlayer insulating layer covering the second gate, forming a second etch stop layer patterned to be unilateral with one edge of the second gate on the interlayer insulating layer, and the impurities Forming a contact hole for simultaneously exposing a region and a predetermined portion of the first gate, depositing polysilicon to cover the second etch stop layer and fill the contact hole on the interlayer insulating layer, and the polysilicon Pattern the wiring to overlap with the portion corresponding to the contact hole, and connect the wiring and the plug contacted with the first and gate and impurity regions. And a step of sex.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2A to 2D are manufacturing process diagrams of a semiconductor device according to a preferred embodiment of the present invention.

Referring to FIG. 2A, a gate oxide film 33 is formed on the semiconductor substrate 31 by a thermal oxidation method. Then, the gate 35 and 36 are formed by depositing and patterning polycrystalline silicon doped with impurities on the gate oxide film 33 by a CVD method. At this time, the gate oxide film 33 is also etched to expose the semiconductor substrate 31.

Using gates 35 and 36 as ion implantation masks, N-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into the exposed portions of the semiconductor substrate 31 to serve as source and drain regions. The impurity region 39 to be formed is formed. At this time, the impurity region 39 may be formed by implanting P-type impurities such as boron (B) or BF.

Sidewalls 37 are formed on the sides of the gates 35 and 36. In this case, an insulating material such as silicon oxide is deposited on the semiconductor substrate 31 to cover the gates 35 and 36, and then the impurity regions 39 and the gates 35 and 36 are formed by RIE. It is formed by etching back to expose the upper surface of the).

Referring to FIG. 2B, silicon nitride is deposited on the semiconductor substrate 31 to cover the gates 35 and 36 and the sidewalls 37 to form a first etch stop layer 41. Then, silicon oxide such as USG (Undoped Silicate Glass), PSG (Phospho Silicate Glass), BPSG (Borophospho Silicate Glass) or TEOS (Tetra Eethyl Ortho Silicate) is deposited on the first etching layer 41, or SOG (Sipn). The interlayer insulating layer 43 is formed by coating with On Glass.

The second etch stop layer 45 is formed by depositing polysilicon without doping impurities on the interlayer insulating layer 43 and patterning the photolithography method. In the above, the second etch stop layer 45 should be formed so as not to overlap the gate 35 but overlap one side edge and the sidewall 37 of the adjacent gate 36.

Referring to FIG. 2C, the contact hole 47 exposing not only the impurity region 39 but also a predetermined portion of the upper surface of the gate 35 is formed at the same time. The contact hole 47 is formed by successively patterning the interlayer insulating layer 43 and the first etch stop layer 41 by a photolithography method. Since the second etch stop layer 45 has an etch selectivity different from that of the interlayer insulating layer 43, when the contact hole 47 is formed, one edge of the gate 36 of an adjacent transistor is prevented from being exposed by misalignment. do. Therefore, the side wall 37 formed on one side edge side of the gate 36 is prevented from being damaged. The remaining second etch stop layer 45 is used as a high load resistance.

Referring to FIG. 2D, polycrystalline silicon doped with impurities to cover the second etch stop layer 45 on the interlayer insulating layer 43 and fill the inside of the contact hole 47 is deposited by CVD. The polysilicon is deposited in contact with the exposed portion of the gate 35 and the impurity region 39 by filling the contact hole 47.                     

The polysilicon is patterned by photolithography to form the wiring 51. At this time, the wiring 51 is formed to overlap the portion corresponding to the contact hole 47. Therefore, the polycrystalline silicon doped with impurities remains in the contact hole 47, thereby forming a plug 49. In the above, the plug 49 is in contact with the exposed portion of the upper surface of the gate 35 as well as the impurity region 39 to make a butt contact.

As described above, in the present invention, the second etch stop layer is formed of polycrystalline silicon that is not doped with the gate and overlaps with one side edge and the sidewall of the adjacent gate on the interlayer insulating layer. When the second etch stop layer forms contact holes for simultaneously exposing not only the impurity region but also a predetermined portion of the upper surface of the gate, the etching selectivity is different from that of the interlayer insulating layer, so that one edge of the gate of the adjacent transistor is exposed by misalignment. To prevent them.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Accordingly, the present invention has the advantage of preventing the gates of adjacent transistors from being exposed even when misaligned when forming a butting contact hole that exposes an impurity region and a predetermined portion of the gate, thereby improving the reliability of the device.

Claims (2)

Forming first and second gates on the semiconductor substrate and forming impurity regions in the exposed portions; Continuously forming a first etch stop layer and an interlayer insulating layer covering the first and second gates on the semiconductor substrate; Forming a second etch stop layer patterned on one side of the edge of the second gate on the interlayer insulating layer; Forming a contact hole for simultaneously exposing the impurity region and a predetermined portion of the first gate; Depositing polysilicon to cover the second etch stop layer and fill the contact hole on the interlayer insulating layer; And patterning the polysilicon to overlap the portion corresponding to the contact hole to form a wiring and a plug in contact with the first and gate and impurity regions. The method of claim 1, And forming the second etch stop layer from polycrystalline silicon that is not doped with impurities.

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