KR100647636B1 - Plasma display panel - Google Patents

Abstract

According to the present invention, a plasma display panel is disclosed. The plasma display panel includes: a partition wall disposed between the upper substrate and the lower substrate, the upper substrate, and the lower substrate disposed to face each other and defining a plurality of discharge cells together with the upper substrate and the lower substrate, and discharge cells continuously arranged in one direction. A plurality of sets of discharge sustaining electrodes arranged to form a pair of at least one pair of sustain electrodes extending across the spaces and spaced apart from each other in parallel with the scan electrodes and the scan electrodes interposed therebetween Address electrodes extending in a direction intersecting the sustain electrodes, upper dielectric layers and lower dielectric layers covering the address sustain electrodes and the address electrodes, a phosphor layer disposed in the discharge cells, and a discharge gas enclosed in the discharge cells. do. According to the plasma display panel, while the number of circuit boards for driving thereof is reduced, the variation in luminance and the resulting luminance difference are eliminated.

Description

Plasma Display Panel {Plasma display panel}

1 is a plan view schematically showing the structure of a plasma display panel according to the prior art;

2 is a view showing an example of a driving method of the plasma display panel shown in FIG.

3 is an exploded perspective view showing a plasma display panel according to a first embodiment of the present invention;

4 is a plan view schematically showing the structure of the plasma display panel shown in FIG.

FIG. 5 is a view showing a portion of a plasma display panel according to a comparative example of the present invention, illustrating a luminance difference according to a position in a discharge cell; FIG.

6 is a view showing a preferred example of the driving method of the plasma display panel shown in FIG.

7 is a plan view schematically showing the structure of a plasma display panel according to a second embodiment of the present invention;

<Description of the symbols for the main parts of the drawings>

110: upper panel 111: upper substrate

114: upper dielectric layer 115: protective layer

120: lower panel 121: lower substrate

123: lower dielectric layer 124: partition wall

125: phosphor layer 130: discharge cell

Y1, .., Ym: scan electrode X1, ..., Xm: sustain electrode

A1, ..., An: Address electrode Xa, Ya: Transparent electrode

Xb, Yb: bus electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a plasma display panel in which discharge unevenness and a resulting luminance difference are eliminated while reducing the number of circuit boards for driving the plasma display panel.

The plasma display panel is a flat panel display panel which displays an image by using gas discharge phenomenon, and is excellent in various display capabilities such as display capacity, brightness, contrast, afterimage, and viewing angle. In addition, it is being spotlighted as a next-generation flat panel display panel that can replace a CRT because it is thin and can display a large screen.

1 schematically shows a structure of a conventional plasma display panel. In the illustrated plasma display panel, a plurality of discharge cells 30 are divided by partitions 24 of a matrix pattern extending in a length and width direction, and the scan electrodes span the discharge cells 30 continuously arranged in one direction. Discharge sustaining electrode pairs consisting of a pair of (X1: Xm) and sustain electrodes (Y1: Ym) are arranged. For example, one scan electrode Y1 and one sustain electrode X1 form one discharge sustain electrode pair. . In addition, the address electrodes A are disposed over the discharge cells 30 continuously arranged in the direction crossing the discharge sustain electrode pair. The sustain electrodes X1: Xm and the scan electrodes Y1: Ym receive driving signals by the X driving unit and the Y driving unit, respectively, and the address electrodes A1: An intersecting these are electrically connected to the address driving unit. Connected to receive an address signal.

2 illustrates a driving method of the plasma display panel shown in FIG. 1. The plasma display panel is driven by dividing one frame period into several subfields SF having different emission counts for gray scale expression. One subfield SF is divided into a reset section PR, an address section PA, and a sustain section PS. In the reset period PR, after the ground voltage Vg is applied to all the scan electrodes Y1: Ym, the sustain discharge voltage Vs is rapidly applied, and the rising ramp signal is again applied to the sustain discharge voltage Vs. The maximum rising voltage (Vs + Vset) which rises by the predetermined voltage (Vset) is reached from. Thereafter, the sustain discharge voltage Vs is rapidly applied to the scan electrodes Y1: Ym from the highest rising voltage Vs + Vset, and a falling ramp signal is applied again to the scan electrodes Y1: Ym. The applied voltage drops to the lowest falling voltage V'nf. Meanwhile, while the ground voltage Vg is maintained at the sustain electrodes X1: Xm, while the sustain discharge voltage Vs is applied to the scan electrodes Y1: Ym having the highest rising voltage Vs + Vset, the discharge voltage Vs is constant. A bias voltage Vb of magnitude is applied. The ground voltage Vg is applied to the address electrodes A1: An during the reset period PR.

In the address period PA, scan pulses of the scan low voltage V ′ scl are sequentially applied to the scan electrodes Y1: Ym biased with the scan high voltage V′sch and at the same time, the address electrodes A1: An ) Is applied to the address signal. The address signal applied to each of the address electrodes A1: An is applied with the positive address voltage Va when the light emitting cell is selected, and the ground voltage Vg otherwise. Accordingly, when the address signal of the positive address voltage Va is applied while the scan pulse of the scan low voltage V'scl is applied, wall charges are formed by the address discharge in the corresponding light emitting cell.

In the sustain period PS, a predetermined sustaining pulse having a predetermined sustain discharge voltage Vs and a ground voltage Vg is applied to all the scan electrodes Y1: Ym and the sustain electrodes X1: Xm. As a result, the light emitting cells in which the wall voltage is formed in the address period PA cause sustain discharge.

As described above, according to the related art, since the sustain pulse should be applied to the scan electrodes Y1: Ym and the sustain electrodes X1: Xm, the Y driver for applying a drive signal to the scan electrodes Y1: Ym (See FIG. 1) and an X driver for applying a driving signal to the sustain electrodes X1: Xm, both of which are formed of a circuit board on which a plurality of circuit elements are mounted. This causes a problem that the manufacturing cost of the display device rises.

In addition, in the circuit board constituting the driving unit, high heat is generated according to its operation. If these are not removed quickly, the circuit elements are deteriorated due to accumulated heat, making it difficult to drive a smooth panel, requiring a separate heat dissipation design. In addition, noise or vibration is generated in the driving unit that generates a periodic signal, and when they are transmitted to the outside, the display quality is degraded, or a vibration damping design is required to block the display.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems and other problems, and provides an improved plasma display panel in which the luminance difference is eliminated by reducing the number of circuit boards for driving the same, and thus achieving uniform discharge. There is this.

In order to achieve the above object, the plasma display panel of the present invention,

An upper substrate and a lower substrate disposed to face each other;

A partition wall disposed between the upper substrate and the lower substrate to define a plurality of discharge cells together with the upper substrate and the lower substrate;

The discharge electrodes extend over the discharge cells continuously arranged in one direction, and are arranged such that scan electrodes spaced in parallel with each other and at least one pair of sustain electrodes arranged symmetrically with the scan electrodes interposed therebetween. A plurality of sets of discharge sustaining electrodes;

Address electrodes extending in a direction crossing the discharge sustain electrodes;

An upper dielectric layer and a lower dielectric layer covering the discharge sustain electrodes and the address electrodes, respectively;

A phosphor layer disposed in the discharge cells; And

It includes; the discharge gas enclosed in the discharge cells.

Here, each of the discharge sustaining electrodes may include one scan electrode and a pair of sustain electrodes symmetrically arranged to be paired with each other with the scan electrodes interposed therebetween, or one scan electrode and the scan electrode. It may include a first sustain electrode pair and a second sustain electrode pair symmetrically arranged to be paired with each other with the electrodes therebetween.

In the plasma display panel of the present invention, a series of driving cycles consisting of a reset period, an address period, and a sustain period is repeatedly performed, and a constant level of a constant voltage is preferably applied to the sustain electrodes through the driving period.

Next, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is an exploded perspective view of the plasma display panel according to the first embodiment of the present invention, and FIG. 4 is a diagram schematically showing the plasma display panel shown in FIG. 3 and shown in FIG. 3 for convenience of description. It is a top view which shows the arrangement order of electrodes by giving a subscript to an electrode. Referring to FIG. 3, the plasma display panel includes an upper panel 110 and a lower panel 120 bonded to the upper panel 110. The upper panel 110 includes an upper substrate 111, a plurality of discharge sustain electrodes S formed in a predetermined pattern on a lower surface of the upper substrate 111, and an upper dielectric layer 114 filling the discharge sustain electrodes S. And a protective layer 115 covering the upper dielectric layer 114.

The upper substrate 111 is generally formed of a transparent material based on glass. A plurality of discharge sustaining electrodes S is disposed under a predetermined pattern, for example, a stripe pattern extending in one direction, below the upper substrate 111. The discharge sustain electrodes S are arranged such that a scan electrode Y and a pair of sustain electrodes X and X` arranged in pairs with the scan electrode Y interposed therebetween form a pair. Here, the sustain electrode pairs X and X ′ include a first sustain electrode X and a second sustain electrode X ′. In the present invention, the sustain electrode pairs (X, X`) are preferably arranged symmetrically with the scan electrodes interposed therebetween. As shown in FIG. 4, one scan electrode (Y1) is located at the center of the discharge cell. Disposed across and equal to the distance L between the scan electrode Y1 and the first sustain electrode X1 and the distance L` between the scan electrode Y1 and the second sustain electrode X`1; It is desirable to remain.

In the driving of the plasma display panel of the present invention, unlike the conventional driving method shown in FIG. 2, the plasma display panel is fixed to the sustain electrodes X and X` through a series of driving periods including a reset period, an address period, and a sustain period. A level DC voltage, for example a ground voltage, is applied. That is, as shown in FIG. 4, in the plasma display panel of the present invention, the scan electrodes Y1: Ym are electrically connected to the Y driving unit to receive a driving signal, but the sustain electrode pairs ((X1, X`) are provided. 1) :( Xm, X`m)) is applied with a constant voltage of constant magnitude, for example, ground voltage Vg, and the sustain electrode pairs ((X1, X`1) :( Xm, X`m) There is no separate X driver for applying a controlled driving signal to the &lt; RTI ID = 0.0 &gt;

Therefore, in the sustain period in which the image is implemented, a sustain pulse made of a predetermined AC voltage is applied only to the scan electrodes Y1: Ym, and as a result, discharge is actively performed near the scan electrodes Y1: Ym, but is constant. In the vicinity of the sustain electrodes X1: Xm where the constant voltage is maintained, the discharge is relatively weak, so that the scan electrodes Y1: Ym are disposed in the discharge cells 130 and the sustain electrodes X1: Xm are disposed. The difference is shown in the light emission level. In FIG. 5, as a comparative example of the present invention, one discharge cell in a plasma display panel in which scan electrodes Yr and sustain electrodes Xr are opposed to each other is schematically illustrated, in which scan electrodes Yr are disposed. In the discharge cell portion, the emission level is about 825 cd / m ² , while in the discharge cell portion in which the sustain electrode Xr is disposed, the emission level is about 800 cd / m ² . As a result, the overall emission level is reduced, as well as the image quality is reduced due to image unevenness due to asymmetric emission and luminance difference. Accordingly, in the present invention, in order to solve such a problem, the sustain electrode pairs are arranged with the scan electrodes interposed therebetween, thereby increasing the discharge surface of the sustain electrode to promote discharge on the sustain electrode side, and the sustain electrodes are symmetrically with respect to the scan electrode. By disposing, the discharge in each discharge cell and the light emission accordingly are made symmetrically, thereby improving the sensitivity.

Meanwhile, each of the scan electrode Y, the first sustain electrode X, and the second sustain electrode X` shown in FIG. 3 is a transparent electrode Ya, Xa, X`a and a bus electrode Yb, Xb. , X`b). However, in some cases, the scan electrode and the sustain electrode may be formed of only the bus electrode without the transparent electrode. The transparent electrodes Ya, Xa, and X`a are formed of a transparent material that is a conductor capable of causing a discharge and does not prevent visible light emitted from the phosphor layer 125 from penetrating the upper substrate 111. Such materials include indium tin oxide (ITO). The bus electrodes Yb, Xb, and X`b are formed to improve the electrical resistance of the transparent electrodes Ya, Xa, and X`a, and are in contact with the transparent electrodes Ya, Xa, and X`a. . The bus electrodes Yb, Xb, and X`b may be formed of a metal material having high conductivity, for example, a single metal layer such as aluminum or silver, or a triple metal layer of chromium-copper-chrome.

An upper dielectric layer 114 is formed below the upper substrate 111 to fill the scan electrode Y and the sustain electrode X. The upper dielectric layer 114 is directly energized between the scan electrode (Y) and the sustain electrode pair (X, X`) adjacent to the kitchen discharge, and the positive and negative electrons directly collide with the discharge sustain electrodes (S) to maintain the discharge electrodes. (S) is prevented from being damaged and also serves to induce charge.

The protective layer 115 is not an essential component, but is preferably formed. The protective layer 115 prevents cations and electrons from colliding with the upper dielectric layer 114 during the discharge to damage the upper dielectric layer 114. In other words, it emits a lot of secondary electrons. As the protective layer 115, typically, MgO may be used.

The lower panel 120 includes a lower substrate 121, a plurality of address electrodes A formed in a predetermined pattern on the lower substrate 121, and a lower dielectric layer 123 filling the address electrodes A. And a partition wall 124 formed on the lower dielectric layer 123 and partitioning the plurality of discharge cells 130, and a phosphor layer 125 formed over the partition wall 124 on the lower dielectric layer 123.

The lower substrate 121 may be made of a glass material like the upper substrate 111. The address electrodes A are formed to extend substantially perpendicular to the discharge sustain electrodes S. As shown in the drawing, the address electrodes A may be formed in a stripe pattern. The lower dielectric layer 123 is formed on the lower substrate 121 to cover the address electrode A. FIG. The lower dielectric layer 123 protects the charged particles from colliding with the address electrode A and damaging the address electrode A. FIG.

The partition wall 124 formed on the lower dielectric layer 123 partitions a region in which the phosphor layer 125 is disposed, and prevents an erroneous discharge between discharge cells 130. A plurality of discharge cells 130 are partitioned by the partition wall 124. As shown in the drawing, the plurality of discharge cells 130 may extend in two directions crossing each other to form a matrix.

The phosphor layer 125 is formed in the discharge cells 130. The phosphor layer 125 is formed by coating a phosphor, and the phosphor includes three color phosphors of red, green, and blue. The discharge cells 130 are classified into a red discharge cell, a green discharge cell, and a blue discharge cell according to the type of phosphor coated therein. Although not shown in the drawing, discharge gas is filled in the discharge cells 130.

Hereinafter, a driving method of the plasma display panel illustrated in FIG. 4 will be described in detail with reference to FIG. 6. In the driving method basically applied to the plasma display panel, the reset period PR, the address period PA, and the sustain period PS are sequentially performed to form one subfield SF. First, the driving signal applied to the scan electrodes Y1: Ym in the reset period PR will be described. The sustain discharge voltages may be applied to the scan electrodes Y1: Ym with the ground voltage Vg applied thereto. Vs) is rapidly applied. Thereafter, a rising ramp signal is applied to the scan electrodes Y1: Ym by rising from the sustain discharge voltage Vs by a predetermined voltage Vset to reach the highest rising voltage Vs + Vset. The weak discharge is executed by this rising ramp signal, and as a result, negative charges start to accumulate in the vicinity of the scan electrodes Y1: Ym. Thereafter, the sustain discharge voltage Vs is rapidly applied to the scan electrodes Y1: Ym, and a falling ramp signal falling from the sustain discharge voltage Vs to the lowest fall voltage Vnf is applied. Here, as will be described later, in the method of driving the plasma display panel of the present invention, the ground voltage Vg is applied to the sustain electrode pairs ((X1, X`1) :( Xm, X`m)) to ground. As the state is maintained, it is necessary to compensate for the bias voltage Vb applied to the sustain electrode in the conventional driving method shown in FIG. Therefore, in the driving method of the present invention, the falling ramp signal applied to the scan electrodes Y1: Ym falls more sharply than in the prior art, and as a result, the lowest falling voltage Vnf reached is lower than in the prior art. .

As a result of the continuous drop of voltage applied to the scan electrodes Y1: Ym, a discharge occurs, and as a result, some of the negative charges accumulated in the scan electrodes Y1: Ym are emitted. This means that an appropriate level of negative charges remain in the vicinity of the scan electrodes Y1: Ym. Meanwhile, the sustain electrode pairs ((X1, X`1) :( Xm, X`m)) and the address electrodes A1: An have a constant level of constant voltage, for example, ground, during the reset period PR. Voltage Vg is applied. Through such a reset period PR, the charge states of all the discharge cells become uniform.

Next, a predetermined wall voltage is generated in the selected discharge cells in the address period PA. In more detail, the scan pulses of the scan low voltage Vscl are sequentially applied to the scan electrodes Y1: Ym biased with the scan high voltage Vsch, and the address electrodes A1: An are adapted to the scan pulses. ) Is applied to the address signal. The address signal applied to each address electrode A1: An is applied with an address voltage Va when the discharge cell is selected, and with a ground voltage Vg otherwise. On the other hand, the ground voltage Vg is continuously applied to the sustain electrode pairs (X1, X`1): (Xm, X`m) after the reset period PR. In the selected discharge cells, near the address voltage Va applied to the address electrodes A1: An, the scan low voltage Vscl applied to the scan electrodes Y1: Ym, and the scan electrodes Y1: Ym. The address discharge is performed by the wall voltage due to the accumulated negative charge and the wall voltage due to the positive charge accumulated near the address electrodes A1: An. As a result of the address discharge, positive charges are accumulated near the scan electrodes Y1: Ym, and negative charges are accumulated near the sustain electrodes X1: Xm.

In the sustain discharge period PS, a predetermined sustain pulse is applied to the scan electrodes Y1: Ym, whereby the discharge cells in which the wall voltage is accumulated cause a sustain discharge. That is, a sustain pulse having alternating positive sustain discharge voltage Vs and negative sustain discharge voltage (-Vs) is applied to the scan electrodes Y1: Ym. Here, when the sustain discharge voltage Vs applied to the scan electrodes Y1: Ym overlaps the wall voltage formed by the address discharge, and the discharge start voltage or more is applied, the discharge is performed. During the sustain period PS, the ground voltage Vg is applied to the sustain electrode pairs (X1, X`1): (Xm, X`m) and the address electrodes A1: An. Grounding status is maintained.

FIG. 7 is a modification of the first embodiment shown in FIG. 4 and schematically illustrates a plasma display panel according to a second embodiment of the present invention. The plasma display panel of the present invention also has a partition wall 224 partitioning the plurality of discharge cells 230, scan electrodes Y1: Ym extending over one row of discharge cells 230, and the scan electrodes Y1. The first sustain electrode pairs ((X1, X`1) :( Xm, X`m)) symmetrically arranged with Ym interposed therebetween, and the second sustain electrode pairs (W1, W`1). (Wm, W`m)). For example, one scan electrode Y1 is disposed across the center of the discharge cell 230, and the first sustain electrode pair X1, X`1 is symmetrically with the scan electrode Y1 interposed therebetween. The second storage electrode pairs W1 and W`1 which are symmetrical with respect to the scan electrode Y1 are further disposed outside the first storage electrode pairs X1 and X`1. In the present embodiment, similarly to the first embodiment, the first sustain electrode pairs X1 and X`1 are disposed symmetrically with respect to the scan electrode Y1, and the first sustain electrode pairs X1 and X are arranged. The second sustain electrode pairs W1 and W`1 are additionally disposed outside `1 ', so that the distance d and d` between the scan electrode Y1 and the sustain electrodes X1 and X`1 that cause discharge together. ) Is shortened. This means that the discharge can be quickly diffused into the entire discharge cell 230 region, which means that the luminance non-uniformity caused by the concentration of the discharge in the partial discharge cell 230 region can be prevented. In addition, since the discharge surface of the sustain electrode having a relatively weak discharge intensity is further increased, the discharge on the sustain electrode side can be promoted by strengthening the electric field, and as a result, the discharge unevenness and the resulting luminance difference can be reduced or eliminated. have. Although not shown in the drawings, the scan electrodes Y1: Ym, the first sustain electrode pair ((X1, X`1): (Xm, X`m)), and the second pre-suspension pole pair ( (W1, W`1): (Wm, W`m)) Each may include a transparent electrode and a bus electrode, or some or all of the electrodes may be composed of only a bus electrode without a transparent electrode.

According to the plasma display panel of the present invention, the following effects can be achieved.

First, the plasma display panel of the present invention can be driven with a small number of circuit boards. Accordingly, the manufacturing cost of the display device including the panel of the present invention can be significantly reduced, as well as the cost and process required for the heat radiation design or the vibration suppression design of the circuit board.

Second, the luminance difference due to the discharge unevenness is eliminated while achieving the above-described effect. By symmetrically arranging the sustain electrode pairs adjacent to the scan electrodes, the electric field of the sustain electrode having a relatively low discharge intensity is strengthened, and a symmetrical discharge structure can be provided, whereby the discharge unevenness and the resulting luminance difference can be eliminated.

Although the present invention has been described with reference to the embodiments illustrated in the accompanying drawings, it is merely exemplary, and various modifications and equivalent other embodiments are possible from those skilled in the art to which the present invention pertains. You will understand the point. Therefore, the true scope of protection of the present invention should be defined by the appended claims.

Claims (7)

An upper substrate and a lower substrate disposed to face each other; A partition wall disposed between the upper substrate and the lower substrate to define a plurality of discharge cells together with the upper substrate and the lower substrate; At least one pair of sustain electrodes extending over discharge cells continuously arranged in one direction, spaced apart from each other in parallel with each other, and at least one pair of sustain electrodes disposed symmetrically with the scan electrodes interposed therebetween, and having a constant level of a constant voltage applied thereto. A plurality of sets of discharge sustaining electrodes arranged to form a pair of electrodes; Address electrodes extending in a direction crossing the discharge sustain electrodes; An upper dielectric layer and a lower dielectric layer covering the discharge sustain electrodes and the address electrodes, respectively; A phosphor layer disposed in the discharge cells; And And a discharge gas encapsulated in the discharge cells. The method of claim 1, And a pair of sustain electrodes arranged symmetrically so as to be paired with each other with the scan electrodes interposed therebetween. The method of claim 1, Each set of discharge sustaining electrodes is symmetrically arranged to be paired with one scan electrode, a first sustain electrode pair symmetrically arranged to be paired with the scan electrode therebetween, and an outer side of the first sustain electrode pair. And a second sustain electrode pair. The method of claim 1, And the scan electrode is disposed across the center of each discharge cell. The method of claim 1, The discharge sustain electrodes are formed under the upper substrate, and a protective layer is formed to cover the upper dielectric layer. And the address electrode is formed above the lower substrate, and the phosphor layer is formed on the lower dielectric layer over the side of the partition wall. delete The method of claim 1, And said constant voltage is a ground voltage.

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