KR100647397B1 - Method for manufacturing device isolation film of semiconductor device - Google Patents

Method for manufacturing device isolation film of semiconductor device Download PDF

Info

Publication number
KR100647397B1
KR100647397B1 KR1020050073767A KR20050073767A KR100647397B1 KR 100647397 B1 KR100647397 B1 KR 100647397B1 KR 1020050073767 A KR1020050073767 A KR 1020050073767A KR 20050073767 A KR20050073767 A KR 20050073767A KR 100647397 B1 KR100647397 B1 KR 100647397B1
Authority
KR
South Korea
Prior art keywords
trench
liner
oxide film
film
layer
Prior art date
Application number
KR1020050073767A
Other languages
Korean (ko)
Inventor
곽병일
신민정
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020050073767A priority Critical patent/KR100647397B1/en
Application granted granted Critical
Publication of KR100647397B1 publication Critical patent/KR100647397B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H01L21/02326—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

A method for fabricating an isolation layer of a semiconductor device is provided to avoid a PMOS HEIP(hot electron induced punchthrough) phenomenon by eliminating a liner nitride layer on a trench. A pad oxide layer(4) and a pad nitride layer(6) are sequentially formed on a semiconductor substrate(2). The pad nitride layer, the pad oxide layer and a predetermined thickness of the semiconductor substrate in a reserved portion for an isolation region are etched to form a trench(8). A sidewall oxide layer(10) is formed on the surface of the trench, having a thickness of 20~200 angstroms. A liner nitride layer(12) and a liner oxide layer(14) are sequentially formed on the semiconductor substrate. A first gap-fill oxide layer(16) is formed in the lower part of the trench. The liner oxide layer exposed to the upper sidewall of the trench is removed to expose the liner nitride layer. The exposed part of the liner nitride layer is oxidized. A second gap-fill oxide layer is formed on the resultant structure to fill the trench. The liner nitride layer has a thickness of 20~100 angstroms.

Description

반도체 소자의 소자 분리막 제조 방법{METHOD FOR MANUFACTURING DEVICE ISOLATION FILM OF SEMICONDUCTOR DEVICE}METHODS FOR MANUFACTURING DEVICE ISOLATION FILM OF SEMICONDUCTOR DEVICE}

도 1a 내지 도 1f는 본 발명에 따른 반도체 소자의 소자 분리막 제조 방법을 도시한 단면도들.1A to 1F are cross-sectional views illustrating a method of manufacturing a device isolation film of a semiconductor device according to the present invention.

본 발명은 반도체 소자의 소자 분리막 제조 방법에 관한 것으로, 특히 트랜치 상부(trench top)의 라이너 질화막(nitride liner)을 제거하여 pMOS 트랜지스터의 HEIP(Hot Electron Induced Punchthrough) 현상을 방지하고, 트랜치 하부(trench bottom)의 라이너 질화막은 보존하여 리프레시 특성을 향상시키고 단층(dislocation)을 방지하는 반도체 소자의 소자 분리막 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a device isolation layer of a semiconductor device, and in particular, removes a line top nitride liner from a trench top to prevent hot electron induced punchthrough (HEIP) of a pMOS transistor, and to form a trench bottom. The bottom liner nitride film is related to a method of manufacturing a device isolation film of a semiconductor device that preserves to improve refresh characteristics and prevents dislocation.

종래 기술에 따른 반도체 소자의 소자 분리막 제조 방법은 라이너 질화막(nitride liner) 및 라이너 산화막(oxide liner)에 의해 누설 전류가 감소하며 소자의 리프레시 특성이 향상된다는 장점이 있다. The method of fabricating a device isolation layer of a semiconductor device according to the related art has an advantage of reducing leakage current and improving refresh characteristics of a device by a liner nitride liner and a liner oxide liner.

그러나 종래 기술에 의한 소자 분리막의 경우 pMOS 트랜지스터가 형성되는 영역의 산화막과 질화막의 경계면에 전자 트랩이 발생하게 되어 열전자(hot electron)가 트랩 된다. However, in the device isolation layer according to the related art, an electron trap is generated at an interface between an oxide film and a nitride film in a region where a pMOS transistor is formed, and hot electrons are trapped.

트랩 된 열전자는 pMOS 트랜지스터의 게이트에 전압이 인가되지 않은 경우에도 채널 영역에 전류가 흐르게 되는 HEIP(Hot electron Induced Punch-through) 현상을 유발시킨다. 여기서, HEIP 현상은 DRAM의 대기 전류(stand-by current)를 증가시킨다. 따라서, 반도체 소자의 불량을 유발하여 수율이 감소하는 문제점이 있다.The trapped hot electrons cause hot electron induced punch-through (HEIP), which causes current to flow in the channel region even when no voltage is applied to the gate of the pMOS transistor. Here, the HEIP phenomenon increases the stand-by current of the DRAM. Therefore, there is a problem that the yield is reduced by causing a defect of the semiconductor device.

이러한 문제점을 해결하기 위하여 측벽 산화막(wall oxide)의 두께를 증가시키는 방법이 제안되었다.In order to solve this problem, a method of increasing the thickness of the side wall oxide (wall oxide) has been proposed.

그러나, 측벽 산화막의 두께가 증가하면 ISO HDP(High Density Plasma) 갭 필(gap fill) 특성이 악화하고 활성 영역의 폭이 감소하여 트랜지스터의 구동 전류 감소, 문턱 전압 감소 및 리프레시 특성의 악화 등을 유발하는 문제가 있다.However, increasing the thickness of the sidewall oxide film deteriorates the ISO High Density Plasma (HDP) gap fill characteristics and decreases the width of the active region, resulting in a decrease in driving current of the transistor, a decrease in threshold voltage, and a deterioration in refresh characteristics. There is a problem.

본 발명이 이루고자 하는 기술적 과제는 HDP 증착 시 ISO 트랜치 상부의 라이너 질화막을 산화시켜 HEIP 특성을 개선하는 것이다.The technical problem to be achieved by the present invention is to improve the HEIP characteristics by oxidizing the liner nitride film on the top of the ISO trench during HDP deposition.

상기한 기술적 과제를 달성하기 위한 본 발명에 따른 반도체 소자의 소자 분리막 제조 방법은 반도체 기판 상부에 패드 산화막 및 패드 질화막을 순차적으로 형성하는 단계; 소자 분리 영역으로 예정된 부분의 상기 패드 질화막, 패드 산화막 및 소정 두께의 반도체 기판을 식각하여 트랜치를 형성하는 단계; 상기 트랜치의 표면에 측벽 산화막을 형성하는 단계; 상기 반도체 기판 전면에 라이너 질화막 및 라이너 산화막을 순차적으로 형성하는 단계; 상기 트랜치의 하부에 제 1 갭-필 산화막을 형성하는 단계; 상기 트랜치 상부의 측벽에 노출된 상기 라이너 산화막을 제거하여 상기 라이너 질화막을 노출시키는 단계; 상기 라이너 질화막의 노출된 부분을 산화시키는 단계; 및 전체 표면 상부에 상기 트랜치를 매립하는 제 2 갭-필 산화막을 형성하는 단계;를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of fabricating an isolation layer of a semiconductor device, the method comprising: sequentially forming a pad oxide film and a pad nitride film on a semiconductor substrate; Etching the pad nitride film, the pad oxide film, and the semiconductor substrate having a predetermined thickness to form a trench as a device isolation region; Forming a sidewall oxide film on a surface of the trench; Sequentially forming a liner nitride film and a liner oxide film on the entire surface of the semiconductor substrate; Forming a first gap-fill oxide layer under the trench; Removing the liner oxide layer exposed on the sidewalls of the trench to expose the liner nitride layer; Oxidizing an exposed portion of the liner nitride film; And forming a second gap-fill oxide layer filling the trench on the entire surface.

이하, 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 그러나, 본 발명은 여기서 설명되는 실시예에 한정되지 않고 다른 형태로 구체화될 수 있다. 오히려, 여기서 소개되는 실시예는 본 발명의 기술적 사상이 철저하고 완전하게 개시되고 당업자에게 본 발명의 사상이 충분히 전달되기 위해 제공되는 것이다. 또한, 명세서 전체에 걸쳐서 동일한 참조 번호들은 동일한 구성요소를 나타낸다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the spirit of the present invention is thoroughly and completely disclosed, and the spirit of the present invention to those skilled in the art will be fully delivered. Also, like reference numerals denote like elements throughout the specification.

도 1a 내지 도 1f는 본 발명에 따른 반도체 소자의 소자 분리막 제조 방법의 실시예를 도시한 단면도들이다.1A to 1F are cross-sectional views illustrating an example of a method of manufacturing a device isolation layer of a semiconductor device according to the present invention.

도 1a를 참조하면, 반도체 기판(2) 상부에 패드 산화막(4) 및 패드 질화막(6)이 순차적으로 형성된다.Referring to FIG. 1A, a pad oxide film 4 and a pad nitride film 6 are sequentially formed on the semiconductor substrate 2.

도 1b를 참조하면, 소자 분리 영역으로 예정된 부분의 패드 질화막(6), 패드 산화막(4) 및 소정 두께의 반도체 기판(2)이 식각되어 트랜치(8)가 형성된다.Referring to FIG. 1B, a trench 8 is formed by etching a pad nitride film 6, a pad oxide film 4, and a semiconductor substrate 2 having a predetermined thickness as a device isolation region.

도 1c를 참조하면, 트랜치(8)의 표면에 측벽 산화막(wall oxide)(10)이 형성된 후 반도체 기판(2)의 전면에 라이너 질화막(12) 및 라이너 산화막(14)이 순차적 으로 형성된다. 여기서, 측벽 산화막(10)은 20 내지 200Å의 두께로 형성되고 NH3, N2O 또는 NO 분위기에서 열처리하는 것이 바람직하고, 라이너 질화막(12)은 20 내지 100Å의 두께로 형성되고 H2 분위기에서 열처리하는 것이 바람직하고, 라이너 산화막(14)은 20 내지 200Å의 두께로 형성하는 것이 바람직하다.Referring to FIG. 1C, after the sidewall oxide layer 10 is formed on the surface of the trench 8, the liner nitride layer 12 and the liner oxide layer 14 are sequentially formed on the front surface of the semiconductor substrate 2. Here, the sidewall oxide film 10 is preferably formed in a thickness of 20 to 200 kPa and heat treated in an NH 3 , N 2 O or NO atmosphere, and the liner nitride film 12 is formed in a thickness of 20 to 100 kPa and in an H 2 atmosphere. It is preferable to heat-process, and it is preferable to form the liner oxide film 14 in thickness of 20-200 kPa.

도 1d를 참조하면, 갭-필 산화막(gap-fill oxide)(16)이 트랜치(8)의 하부에만 적정한 위치까지 증착된다. 여기서, 갭-필 산화막(16)은 HDP(High Density Plasma) 산화막인 것이 바람직하며, 그 형성되는 깊이(HDP depth)(D)는 400 내지 600Å로 형성하는 것이 바람직하다.Referring to FIG. 1D, a gap-fill oxide 16 is deposited to an appropriate location only below the trench 8. Here, the gap-fill oxide film 16 is preferably an HDP (High Density Plasma) oxide film, and the formed depth (HDP depth) D is preferably formed to be 400 to 600 kPa.

도 1e를 참조하면, 트랜치(8)의 상부에 노출된 라이너 산화막(14)이 습식 또는 건식 식각(wet/dry etch)을 통해 제거된다. 따라서, 트랜치(8)의 상부에 라이너 산화막(14)이 제거된 영역의 라이너 질화막(12)만 노출된다.Referring to FIG. 1E, the liner oxide layer 14 exposed on top of the trench 8 is removed through wet or dry etch. Therefore, only the liner nitride film 12 in the region where the liner oxide film 14 is removed is exposed on the trench 8.

도 1f를 참조하면, 갭-필 산화막 증착 시 라이너 질화막(12)의 노출된 부분이 산화된다. 또한, 전체 표면 상부에 트랜치(8)를 매립하는 갭-필 산화막(16)이 형성된다. 여기서, 갭-필 산화막(16)은 HDP(High Density Plasma) 산화막인 것이 바람직하며, 라이너 질화막(12)의 산화 공정은 HDP 산화막(16) 형성시 동시에 수행될 수 있다. 즉, 고밀도 플라즈마를 사용하여 갭-필 산화막(16)을 형성하는 공정에서 라이너 질화막(12)의 노출된 부분을 플라즈마를 이용하여 산화시킬 수도 있다.Referring to FIG. 1F, the exposed portion of the liner nitride film 12 is oxidized during gap-fill oxide deposition. In addition, a gap-fill oxide film 16 is formed to fill the trench 8 over the entire surface. Here, the gap-fill oxide film 16 is preferably an HDP (High Density Plasma) oxide film, and the oxidation process of the liner nitride film 12 may be simultaneously performed when the HDP oxide film 16 is formed. That is, in the process of forming the gap-fill oxide film 16 using a high density plasma, the exposed portion of the liner nitride film 12 may be oxidized using the plasma.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부각가 가능할 것이며, 이러한 수정, 변경 등은 이하의 특허 청구범위에 속하는 것으로 보아야 할 것이다.In addition, the preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, substitutions and highlights through the spirit and scope of the appended claims, such modifications, changes, etc. are claimed It should be seen as belonging to a range.

이상에서 살펴본 바와 같이, 본 발명에 따른 반도체 소자의 소자 분리막 제조 방법은 트랜치 상부(trench top)의 라이너 질화막(nitride liner)을 제거하여 pMOS HEIP(Hot Electron Induced Punchthrough) 현상을 방지하는 효과가 있다.As described above, the device isolation film manufacturing method of the semiconductor device according to the present invention has an effect of preventing a pMOS hot electron induced punching phenomenon by removing a liner nitride film of a trench top.

또한, 본 발명에 따른 반도체 소자의 소자 분리막 제조 방법은 트랜치 하부(trench bottom)의 라이너 질화막은 보존하여 리프레시 특성을 향상시키고 단층(dislocation)을 방지하는 효과가 있다.In addition, the device isolation film manufacturing method of the semiconductor device according to the present invention has the effect of preserving the trench bottom liner nitride film to improve the refresh characteristics and to prevent dislocation.

Claims (10)

반도체 기판 상부에 패드 산화막 및 패드 질화막을 순차적으로 형성하는 단계;Sequentially forming a pad oxide film and a pad nitride film on the semiconductor substrate; 소자 분리 영역으로 예정된 부분의 상기 패드 질화막, 패드 산화막 및 소정 두께의 반도체 기판을 식각하여 트랜치를 형성하는 단계;Etching the pad nitride film, the pad oxide film, and the semiconductor substrate having a predetermined thickness to form a trench as a device isolation region; 상기 트랜치의 표면에 측벽 산화막을 형성하는 단계;Forming a sidewall oxide film on a surface of the trench; 상기 반도체 기판 전면에 라이너 질화막 및 라이너 산화막을 순차적으로 형성하는 단계;Sequentially forming a liner nitride film and a liner oxide film on the entire surface of the semiconductor substrate; 상기 트랜치 하부에 제 1 갭-필 산화막을 형성하는 단계;Forming a first gap-fill oxide layer under the trench; 상기 트랜치 상부의 측벽에 노출된 상기 라이너 산화막을 제거하여 상기 라이너 질화막을 노출시키는 단계;Removing the liner oxide layer exposed on the sidewalls of the trench to expose the liner nitride layer; 상기 라이너 질화막의 노출된 부분을 산화시키는 단계; 및Oxidizing an exposed portion of the liner nitride film; And 전체 표면 상부에 상기 트랜치를 매립하는 제 2 갭-필 산화막을 형성하는 단계;Forming a second gap-fill oxide film filling the trench over the entire surface; 를 포함하는 것을 특징으로 하는 반도체 소자의 소자 분리막 제조 방법.Device isolation film manufacturing method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 측벽 산화막의 두께는 20 내지 200Å인 것을 특징으로 하는 반도체 소자의 소자 분리막 제조 방법.The thickness of the sidewall oxide film is 20 to 200 kHz, the device isolation film manufacturing method of a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 측벽 산화막을 NH3, N2O 또는 NO 분위기에서 열처리하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 소자 분리막 제조 방법.And heat-treating the sidewall oxide film in an NH 3 , N 2 O or NO atmosphere. 제 1 항에 있어서,The method of claim 1, 상기 라이너 질화막의 두께는 20 내지 100Å인 것을 특징으로 하는 반도체 소자의 소자 분리막 제조 방법.And a thickness of the liner nitride film is 20 to 100 GPa. 제 1 항에 있어서,The method of claim 1, 상기 라이너 질화막을 H2 분위기에서 열처리하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 소자 분리막 제조 방법.The method of claim 1 further comprising the step of heat-treating the liner nitride film in H 2 atmosphere. 제 1 항에 있어서,The method of claim 1, 상기 라이너 산화막의 두께는 20 내지 200Å인 것을 특징으로 하는 반도체 소자의 소자 분리막 제조 방법.The thickness of the liner oxide film is 20 to 200 GPa device isolation film manufacturing method of a semiconductor device, characterized in that. 제 1 항에 있어서,The method of claim 1, 상기 라이너 질화막의 노출된 부분을 산화시키는 단계는 플라즈마를 이용한 산화 공정인 것을 특징으로 하는 반도체 소자의 소자 분리막 제조 방법.And oxidizing the exposed portion of the liner nitride layer is an oxidation process using plasma. 제 1 항에 있어서,The method of claim 1, 상기 라이너 질화막의 노출된 부분을 산화시키는 단계는 상기 제 2 갭-필 산화막을 형성하는 단계와 동시에 수행되는 것을 특징으로 하는 반도체 소자의 소자 분리막 제조 방법.And oxidizing the exposed portion of the liner nitride layer at the same time as forming the second gap-fill oxide layer. 제 8 항에 있어서,The method of claim 8, 상기 제 2 갭-필 산화막은 HDP 산화막으로 형성하는 것을 특징으로 하는 반도체 소자의 소자 분리막 제조 방법.And the second gap-fill oxide film is formed of an HDP oxide film. 제 1 항에 있어서,The method of claim 1, 상기 제 1 갭-필 산화막은 상기 트랜치의 상단으로부터 400 내지 600Å 깊이까지 형성되는 것을 특징으로 하는 반도체 소자의 소자 분리막 제조 방법.And the first gap-fill oxide film is formed to a depth of 400 to 600 kHz from an upper end of the trench.
KR1020050073767A 2005-08-11 2005-08-11 Method for manufacturing device isolation film of semiconductor device KR100647397B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020050073767A KR100647397B1 (en) 2005-08-11 2005-08-11 Method for manufacturing device isolation film of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050073767A KR100647397B1 (en) 2005-08-11 2005-08-11 Method for manufacturing device isolation film of semiconductor device

Publications (1)

Publication Number Publication Date
KR100647397B1 true KR100647397B1 (en) 2006-11-23

Family

ID=37712851

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050073767A KR100647397B1 (en) 2005-08-11 2005-08-11 Method for manufacturing device isolation film of semiconductor device

Country Status (1)

Country Link
KR (1) KR100647397B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100884347B1 (en) 2007-10-29 2009-02-18 주식회사 하이닉스반도체 Method for fabricating isolation layer in semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11284063A (en) 1997-12-30 1999-10-15 Siemens Ag Shallow trench isolation structure in substrate and method for reducing problem of reliabilityl for hot carrier inside integrated circuit device on substrate
KR20010064324A (en) * 1999-12-29 2001-07-09 박종섭 Method for forming isolation layer of semiconductor device using trench technology

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11284063A (en) 1997-12-30 1999-10-15 Siemens Ag Shallow trench isolation structure in substrate and method for reducing problem of reliabilityl for hot carrier inside integrated circuit device on substrate
KR20010064324A (en) * 1999-12-29 2001-07-09 박종섭 Method for forming isolation layer of semiconductor device using trench technology

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100884347B1 (en) 2007-10-29 2009-02-18 주식회사 하이닉스반도체 Method for fabricating isolation layer in semiconductor device

Similar Documents

Publication Publication Date Title
US7601609B2 (en) Method for manufacturing device isolation film of semiconductor device
US6261921B1 (en) Method of forming shallow trench isolation structure
KR100607351B1 (en) Method for fabricating flash memory device
US6407005B2 (en) Method for forming semiconductor device to prevent electric field concentration from being generated at corner of active region
KR100683490B1 (en) Method for manufacturing field effect transistor having vertical channel
KR100647397B1 (en) Method for manufacturing device isolation film of semiconductor device
KR100506453B1 (en) Manufacturing method for semiconductor device
KR20010037467A (en) A method of forming a trench isolation in a semiconductor device
KR100967203B1 (en) Method for forming the Isolation Layer of Semiconductor Device
KR100642406B1 (en) Semiconductor Device and the Manufacturing Method thereof
KR100613459B1 (en) Method of fabricating the trench isolation layer for semiconductor device
KR100608375B1 (en) Method for forming gate in semiconductor device
KR100668837B1 (en) Method for forming isolation layer of semiconductor device
KR100734086B1 (en) Method of manufacturing semiconductor device
KR20000044658A (en) Method for forming isolation layer of semiconductor device
KR100898660B1 (en) Method of manufacturing a NAND flash memory device
KR20080097836A (en) Method of manufacturing semiconductor device
KR20050093160A (en) Method for manufacturing merged semiconductor device
KR20090067611A (en) Method for forming isolation film in semiconductor device
KR20050003057A (en) Fabricating method of trench isolation layer in semiconductor device
KR20080062561A (en) Method for forming isolation layer of semiconductor device
KR20030072106A (en) Method for fabricating semiconductor device
KR20080021389A (en) Method of manufacturing a semiconductor device
KR20070044931A (en) Method of fabricating the trench isolation layer in semiconductor device using self aligned side oxidation
KR20070036472A (en) Method for manufacturing recess gate in semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20101025

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee