KR100643873B1 - 데드락이 없는 컴퓨터 시스템 동작을 위한 가상 채널들 및 대응하는 버퍼 할당 - Google Patents

데드락이 없는 컴퓨터 시스템 동작을 위한 가상 채널들 및 대응하는 버퍼 할당 Download PDF

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KR100643873B1
KR100643873B1 KR1020027003545A KR20027003545A KR100643873B1 KR 100643873 B1 KR100643873 B1 KR 100643873B1 KR 1020027003545 A KR1020027003545 A KR 1020027003545A KR 20027003545 A KR20027003545 A KR 20027003545A KR 100643873 B1 KR100643873 B1 KR 100643873B1
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packet
node
data
packets
control
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KR20020030825A (ko
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켈러제임스비.
메이어데릭알.
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17381—Two dimensional, e.g. mesh, torus

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020027003545A 1999-09-17 2000-05-09 데드락이 없는 컴퓨터 시스템 동작을 위한 가상 채널들 및 대응하는 버퍼 할당 Expired - Lifetime KR100643873B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/399,281 1999-09-17
US09/399,281 US6938094B1 (en) 1999-09-17 1999-09-17 Virtual channels and corresponding buffer allocations for deadlock-free computer system operation

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KR20020030825A KR20020030825A (ko) 2002-04-25
KR100643873B1 true KR100643873B1 (ko) 2006-11-10

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KR1020027003545A Expired - Lifetime KR100643873B1 (ko) 1999-09-17 2000-05-09 데드락이 없는 컴퓨터 시스템 동작을 위한 가상 채널들 및 대응하는 버퍼 할당

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US (1) US6938094B1 (enExample)
EP (1) EP1222558B1 (enExample)
JP (1) JP4410967B2 (enExample)
KR (1) KR100643873B1 (enExample)
DE (1) DE60003834T2 (enExample)
WO (1) WO2001022247A1 (enExample)

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WO2012127619A1 (ja) * 2011-03-22 2012-09-27 富士通株式会社 並列計算機システム及び並列計算機システムの制御方法
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Also Published As

Publication number Publication date
WO2001022247A1 (en) 2001-03-29
US6938094B1 (en) 2005-08-30
DE60003834T2 (de) 2004-05-13
DE60003834D1 (de) 2003-08-14
KR20020030825A (ko) 2002-04-25
EP1222558B1 (en) 2003-07-09
EP1222558A1 (en) 2002-07-17
JP4410967B2 (ja) 2010-02-10
JP2003510686A (ja) 2003-03-18

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