DE60003834T2 - Vituelle kanäle und entsprechende pufferzuweisungen für einen blockierungfreien rechnersystem -betrieb - Google Patents

Vituelle kanäle und entsprechende pufferzuweisungen für einen blockierungfreien rechnersystem -betrieb Download PDF

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Publication number
DE60003834T2
DE60003834T2 DE60003834T DE60003834T DE60003834T2 DE 60003834 T2 DE60003834 T2 DE 60003834T2 DE 60003834 T DE60003834 T DE 60003834T DE 60003834 T DE60003834 T DE 60003834T DE 60003834 T2 DE60003834 T2 DE 60003834T2
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Germany
Prior art keywords
packet
node
data
packets
buffer
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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DE60003834T
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German (de)
English (en)
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DE60003834D1 (de
Inventor
B. James KELLER
R. Derrick MEYER
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication of DE60003834D1 publication Critical patent/DE60003834D1/de
Publication of DE60003834T2 publication Critical patent/DE60003834T2/de
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Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17381—Two dimensional, e.g. mesh, torus

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)
DE60003834T 1999-09-17 2000-05-09 Vituelle kanäle und entsprechende pufferzuweisungen für einen blockierungfreien rechnersystem -betrieb Expired - Lifetime DE60003834T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US399281 1999-09-17
US09/399,281 US6938094B1 (en) 1999-09-17 1999-09-17 Virtual channels and corresponding buffer allocations for deadlock-free computer system operation
PCT/US2000/012574 WO2001022247A1 (en) 1999-09-17 2000-05-09 Virtual channels and corresponding buffer allocations for deadlock-free computer system operation

Publications (2)

Publication Number Publication Date
DE60003834D1 DE60003834D1 (de) 2003-08-14
DE60003834T2 true DE60003834T2 (de) 2004-05-13

Family

ID=23578934

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60003834T Expired - Lifetime DE60003834T2 (de) 1999-09-17 2000-05-09 Vituelle kanäle und entsprechende pufferzuweisungen für einen blockierungfreien rechnersystem -betrieb

Country Status (6)

Country Link
US (1) US6938094B1 (enExample)
EP (1) EP1222558B1 (enExample)
JP (1) JP4410967B2 (enExample)
KR (1) KR100643873B1 (enExample)
DE (1) DE60003834T2 (enExample)
WO (1) WO2001022247A1 (enExample)

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US20040122973A1 (en) * 2002-12-19 2004-06-24 Advanced Micro Devices, Inc. System and method for programming hyper transport routing tables on multiprocessor systems
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US7386626B2 (en) * 2003-06-23 2008-06-10 Newisys, Inc. Bandwidth, framing and error detection in communications between multi-processor clusters of multi-cluster computer systems
US7395347B2 (en) * 2003-08-05 2008-07-01 Newisys, Inc, Communication between and within multi-processor clusters of multi-cluster computer systems
US7949782B2 (en) * 2003-11-06 2011-05-24 Qualcomm Incorporated Extended link monitoring channel for 10 Gb/s Ethernet
US7543131B2 (en) 2005-08-12 2009-06-02 Advanced Micro Devices, Inc. Controlling an I/O MMU
US7516247B2 (en) 2005-08-12 2009-04-07 Advanced Micro Devices, Inc. Avoiding silent data corruption and data leakage in a virtual environment with multiple guests
US7793067B2 (en) * 2005-08-12 2010-09-07 Globalfoundries Inc. Translation data prefetch in an IOMMU
US7480784B2 (en) 2005-08-12 2009-01-20 Advanced Micro Devices, Inc. Ensuring deadlock free operation for peer to peer traffic in an input/output memory management unit (IOMMU)
US9053072B2 (en) * 2007-01-25 2015-06-09 Hewlett-Packard Development Company, L.P. End node transactions at threshold-partial fullness of storage space
US7809006B2 (en) * 2007-08-16 2010-10-05 D. E. Shaw Research, Llc Routing with virtual channels
JP5119882B2 (ja) * 2007-11-21 2013-01-16 富士通株式会社 メモリクロック設定機能を有する情報処理装置およびメモリクロック設定方法
US7562168B1 (en) 2008-05-29 2009-07-14 International Business Machines Corporation Method of optimizing buffer usage of virtual channels of a physical communication link and apparatuses for performing the same
WO2010087002A1 (ja) * 2009-01-30 2010-08-05 富士通株式会社 情報処理システム、情報処理装置、情報処理装置の制御方法、情報処理装置の制御プログラム及びコンピュータ読み取り可能な記録媒体
JP5696779B2 (ja) * 2011-03-22 2015-04-08 富士通株式会社 並列計算機システム及び並列計算機システムの制御方法
US8631212B2 (en) 2011-09-25 2014-01-14 Advanced Micro Devices, Inc. Input/output memory management unit with protection mode for preventing memory access by I/O devices
US9007962B2 (en) 2013-01-24 2015-04-14 International Business Machines Corporation Deadlock-free routing using edge-disjoint sub-networks
JP6321194B2 (ja) * 2014-03-20 2018-05-09 インテル コーポレイション リンクインタフェースの使用されていないハードウェアの電力消費を制御するための方法、装置及びシステム
US20160188519A1 (en) * 2014-12-27 2016-06-30 Intel Corporation Method, apparatus, system for embedded stream lanes in a high-performance interconnect
US10075383B2 (en) 2016-03-30 2018-09-11 Advanced Micro Devices, Inc. Self-timed router with virtual channel control
US11238041B2 (en) * 2020-03-25 2022-02-01 Ocient Holdings LLC Facilitating query executions via dynamic data block routing

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Also Published As

Publication number Publication date
EP1222558A1 (en) 2002-07-17
KR100643873B1 (ko) 2006-11-10
US6938094B1 (en) 2005-08-30
JP2003510686A (ja) 2003-03-18
KR20020030825A (ko) 2002-04-25
WO2001022247A1 (en) 2001-03-29
EP1222558B1 (en) 2003-07-09
DE60003834D1 (de) 2003-08-14
JP4410967B2 (ja) 2010-02-10

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