JP4410967B2 - デッドロックのないコンピュータシステム動作のためのバーチャルチャネルおよび対応するバッファ割当て - Google Patents

デッドロックのないコンピュータシステム動作のためのバーチャルチャネルおよび対応するバッファ割当て Download PDF

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JP4410967B2
JP4410967B2 JP2001525542A JP2001525542A JP4410967B2 JP 4410967 B2 JP4410967 B2 JP 4410967B2 JP 2001525542 A JP2001525542 A JP 2001525542A JP 2001525542 A JP2001525542 A JP 2001525542A JP 4410967 B2 JP4410967 B2 JP 4410967B2
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node
packet
control packet
data
buffer
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JP2003510686A5 (enExample
JP2003510686A (ja
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ケラー，ジェイムス・ビィ
メイヤー，デリック・アール
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17381—Two dimensional, e.g. mesh, torus

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)
JP2001525542A 1999-09-17 2000-05-09 デッドロックのないコンピュータシステム動作のためのバーチャルチャネルおよび対応するバッファ割当て Expired - Lifetime JP4410967B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/399,281 1999-09-17
US09/399,281 US6938094B1 (en) 1999-09-17 1999-09-17 Virtual channels and corresponding buffer allocations for deadlock-free computer system operation
PCT/US2000/012574 WO2001022247A1 (en) 1999-09-17 2000-05-09 Virtual channels and corresponding buffer allocations for deadlock-free computer system operation

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JP2003510686A JP2003510686A (ja) 2003-03-18
JP2003510686A5 JP2003510686A5 (enExample) 2007-05-31
JP4410967B2 true JP4410967B2 (ja) 2010-02-10

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JP2001525542A Expired - Lifetime JP4410967B2 (ja) 1999-09-17 2000-05-09 デッドロックのないコンピュータシステム動作のためのバーチャルチャネルおよび対応するバッファ割当て

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US (1) US6938094B1 (enExample)
EP (1) EP1222558B1 (enExample)
JP (1) JP4410967B2 (enExample)
KR (1) KR100643873B1 (enExample)
DE (1) DE60003834T2 (enExample)
WO (1) WO2001022247A1 (enExample)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7230917B1 (en) * 2001-02-22 2007-06-12 Cisco Technology, Inc. Apparatus and technique for conveying per-channel flow control information to a forwarding engine of an intermediate network node
US9836424B2 (en) 2001-08-24 2017-12-05 Intel Corporation General input/output architecture, protocol and related methods to implement flow control
DE60222782D1 (de) 2001-08-24 2007-11-15 Intel Corp Eine allgemeine eingabe-/ausgabearchitektur und entsprechende verfahren zur unterstützung von bestehenden unterbrechungen
US7979573B2 (en) * 2002-05-15 2011-07-12 Broadcom Corporation Smart routing between peers in a point-to-point link based system
US7447872B2 (en) * 2002-05-30 2008-11-04 Cisco Technology, Inc. Inter-chip processor control plane communication
US20040122973A1 (en) * 2002-12-19 2004-06-24 Advanced Micro Devices, Inc. System and method for programming hyper transport routing tables on multiprocessor systems
JP4891521B2 (ja) 2003-03-28 2012-03-07 三洋電機株式会社 データ入出力方法、およびその方法を利用可能な記憶装置およびホスト装置
US7386626B2 (en) * 2003-06-23 2008-06-10 Newisys, Inc. Bandwidth, framing and error detection in communications between multi-processor clusters of multi-cluster computer systems
US7395347B2 (en) * 2003-08-05 2008-07-01 Newisys, Inc, Communication between and within multi-processor clusters of multi-cluster computer systems
US7949782B2 (en) * 2003-11-06 2011-05-24 Qualcomm Incorporated Extended link monitoring channel for 10 Gb/s Ethernet
US7543131B2 (en) 2005-08-12 2009-06-02 Advanced Micro Devices, Inc. Controlling an I/O MMU
US7516247B2 (en) 2005-08-12 2009-04-07 Advanced Micro Devices, Inc. Avoiding silent data corruption and data leakage in a virtual environment with multiple guests
US7793067B2 (en) * 2005-08-12 2010-09-07 Globalfoundries Inc. Translation data prefetch in an IOMMU
US7480784B2 (en) 2005-08-12 2009-01-20 Advanced Micro Devices, Inc. Ensuring deadlock free operation for peer to peer traffic in an input/output memory management unit (IOMMU)
US9053072B2 (en) * 2007-01-25 2015-06-09 Hewlett-Packard Development Company, L.P. End node transactions at threshold-partial fullness of storage space
US7809006B2 (en) * 2007-08-16 2010-10-05 D. E. Shaw Research, Llc Routing with virtual channels
JP5119882B2 (ja) * 2007-11-21 2013-01-16 富士通株式会社 メモリクロック設定機能を有する情報処理装置およびメモリクロック設定方法
US7562168B1 (en) 2008-05-29 2009-07-14 International Business Machines Corporation Method of optimizing buffer usage of virtual channels of a physical communication link and apparatuses for performing the same
WO2010087002A1 (ja) * 2009-01-30 2010-08-05 富士通株式会社 情報処理システム、情報処理装置、情報処理装置の制御方法、情報処理装置の制御プログラム及びコンピュータ読み取り可能な記録媒体
JP5696779B2 (ja) * 2011-03-22 2015-04-08 富士通株式会社 並列計算機システム及び並列計算機システムの制御方法
US8631212B2 (en) 2011-09-25 2014-01-14 Advanced Micro Devices, Inc. Input/output memory management unit with protection mode for preventing memory access by I/O devices
US9007962B2 (en) 2013-01-24 2015-04-14 International Business Machines Corporation Deadlock-free routing using edge-disjoint sub-networks
JP6321194B2 (ja) * 2014-03-20 2018-05-09 インテル コーポレイション リンクインタフェースの使用されていないハードウェアの電力消費を制御するための方法、装置及びシステム
US20160188519A1 (en) * 2014-12-27 2016-06-30 Intel Corporation Method, apparatus, system for embedded stream lanes in a high-performance interconnect
US10075383B2 (en) 2016-03-30 2018-09-11 Advanced Micro Devices, Inc. Self-timed router with virtual channel control
US11238041B2 (en) * 2020-03-25 2022-02-01 Ocient Holdings LLC Facilitating query executions via dynamic data block routing

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4905231A (en) 1988-05-03 1990-02-27 American Telephone And Telegraph Company, At&T Bell Laboratories Multi-media virtual circuit
GB8915136D0 (en) 1989-06-30 1989-08-23 Inmos Ltd Method for controlling communication between computers
WO1993023810A1 (en) 1992-05-12 1993-11-25 Seiko Epson Corporation Scalable coprocessor
US5533198A (en) 1992-11-30 1996-07-02 Cray Research, Inc. Direction order priority routing of packets between nodes in a networked system
US6157967A (en) 1992-12-17 2000-12-05 Tandem Computer Incorporated Method of data communication flow control in a data processing system using busy/ready commands
KR100304063B1 (ko) 1993-08-04 2001-11-22 썬 마이크로시스템즈, 인코포레이티드 2지점간상호접속통신유틸리티
US5583990A (en) 1993-12-10 1996-12-10 Cray Research, Inc. System for allocating messages between virtual channels to avoid deadlock and to optimize the amount of message traffic on each type of virtual channel
US5613129A (en) 1994-05-02 1997-03-18 Digital Equipment Corporation Adaptive mechanism for efficient interrupt processing
FI98774C (fi) * 1994-05-24 1997-08-11 Nokia Telecommunications Oy Menetelmä ja laitteisto liikenteen priorisoimiseksi ATM-verkossa
JPH08185380A (ja) * 1994-12-28 1996-07-16 Hitachi Ltd 並列計算機
US5659796A (en) * 1995-04-13 1997-08-19 Cray Research, Inc. System for randomly modifying virtual channel allocation and accepting the random modification based on the cost function
US5909427A (en) 1995-07-19 1999-06-01 Fujitsu Network Communications, Inc. Redundant switch system and method of operation
GB2304210B (en) * 1995-08-11 2000-02-16 Fujitsu Ltd Data receiving devices
US6055618A (en) * 1995-10-31 2000-04-25 Cray Research, Inc. Virtual maintenance network in multiprocessing system having a non-flow controlled virtual maintenance channel
US6094431A (en) * 1995-11-30 2000-07-25 Kabushiki Kaisha Toshiba Node device and network resource reservation method for data packet transfer using ATM networks
US5848068A (en) 1996-03-07 1998-12-08 Lsi Logic Corporation ATM communication system interconnect/termination unit
US5748900A (en) 1996-03-13 1998-05-05 Cray Research, Inc. Adaptive congestion control mechanism for modular computer networks
JPH09293015A (ja) 1996-04-24 1997-11-11 Mitsubishi Electric Corp メモリシステムおよびそれに用いられる半導体記憶装置
US5749095A (en) 1996-07-01 1998-05-05 Sun Microsystems, Inc. Multiprocessing system configured to perform efficient write operations
US5892970A (en) 1996-07-01 1999-04-06 Sun Microsystems, Inc. Multiprocessing system configured to perform efficient block copy operations
US5881316A (en) 1996-11-12 1999-03-09 Hewlett-Packard Company Dynamic allocation of queue space using counters
US5996013A (en) * 1997-04-30 1999-11-30 International Business Machines Corporation Method and apparatus for resource allocation with guarantees
US6122700A (en) 1997-06-26 2000-09-19 Ncr Corporation Apparatus and method for reducing interrupt density in computer systems by storing one or more interrupt events received at a first device in a memory and issuing an interrupt upon occurrence of a first predefined event
US6005851A (en) * 1997-10-10 1999-12-21 Nortel Networks Corporation Adaptive channel control for data service delivery
US6101420A (en) * 1997-10-24 2000-08-08 Compaq Computer Corporation Method and apparatus for disambiguating change-to-dirty commands in a switch based multi-processing system with coarse directories
US6094686A (en) * 1997-10-24 2000-07-25 Compaq Computer Corporation Multi-processor system for transferring data without incurring deadlock using hierarchical virtual channels
US6014690A (en) * 1997-10-24 2000-01-11 Digital Equipment Corporation Employing multiple channels for deadlock avoidance in a cache coherency protocol
US6279084B1 (en) 1997-10-24 2001-08-21 Compaq Computer Corporation Shadow commands to optimize sequencing of requests in a switch-based multi-processor system
GB9809183D0 (en) 1998-04-29 1998-07-01 Sgs Thomson Microelectronics Microcomputer with interrupt packets
US6370621B1 (en) 1998-12-21 2002-04-09 Advanced Micro Devices, Inc. Memory cancel response optionally cancelling memory controller's providing of data in response to a read operation
US6205508B1 (en) 1999-02-16 2001-03-20 Advanced Micro Devices, Inc. Method for distributing interrupts in a multi-processor system
US6449267B1 (en) * 1999-02-24 2002-09-10 Hughes Electronics Corporation Method and apparatus for medium access control from integrated services packet-switched satellite networks
US6370600B1 (en) 1999-05-25 2002-04-09 Advanced Micro Devices, Inc. Staging buffer for translating clock domains when source clock frequency exceeds target clock frequency
US6389526B1 (en) 1999-08-24 2002-05-14 Advanced Micro Devices, Inc. Circuit and method for selectively stalling interrupt requests initiated by devices coupled to a multiprocessor system
US6484220B1 (en) 1999-08-26 2002-11-19 International Business Machines Corporation Transfer of data between processors in a multi-processor system
GB2360168B (en) 2000-03-11 2003-07-16 3Com Corp Network switch including hysteresis in signalling fullness of transmit queues
US6715055B1 (en) 2001-10-15 2004-03-30 Advanced Micro Devices, Inc. Apparatus and method for allocating buffer space

Also Published As

Publication number Publication date
EP1222558A1 (en) 2002-07-17
KR100643873B1 (ko) 2006-11-10
US6938094B1 (en) 2005-08-30
JP2003510686A (ja) 2003-03-18
KR20020030825A (ko) 2002-04-25
DE60003834T2 (de) 2004-05-13
WO2001022247A1 (en) 2001-03-29
EP1222558B1 (en) 2003-07-09
DE60003834D1 (de) 2003-08-14

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