KR100639195B1 - Method for forming isolation layer in semiconductor device - Google Patents

Abstract

The present invention discloses a method of forming a device isolation film of a semiconductor device capable of preventing malfunction and deterioration of a device due to parasitic transistors and leakage currents caused by concentration of an electric field at an edge of an angled STI. Depositing a pad oxide film and a pad nitride film on a silicon substrate in turn, and performing an ISO mask and an etching process to define a shallow trench, and blanket etching the pad nitride film to obtain an edge of the top portion of the shallow trench. Opening the pad nitride film by blanket etching the pad nitride film, and performing an annealing process using a high temperature rapid heating method (RTP) under an atmosphere capable of moving and converting silicon atoms, thereby forming the top and bottom portions of the shallow trench. Forming the edges of the top and bottom portions of the shallow trenches; After depositing an oxide film on the resultant formed by the round formation, the trench is filled with a high concentration plasma (HDP) oxide film, followed by magnetization to densify, and after the oxide film is deposited and densified, chemical mechanical polishing ( And a stripping of the nitride film to complete a device isolation film having rounded shallow trench corners after the CMP process.

Description

METHODS FOR FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE}

1A and 1B are cross-sectional views illustrating a conventional STI device isolation method.

1C and 1D are process enlarged photographs of a conventional STI device separator.

2A to 2F are cross-sectional views illustrating a method of forming an STI device isolation film according to the present invention.

* Description of the symbols for the main parts of the drawings *

1, 11: silicon substrate 2, 12: silicon oxide film

3, 13: silicon nitride film 4: resist pattern

5 insulating film 14 liner oxide film

15: high concentration plasma oxide film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device, and more specifically, by rounding an edge portion of a shallow trench isolation film (hereinafter, referred to as 'STI'), The present invention relates to a device isolation film formation method of a semiconductor device which prevents malfunction and deterioration of a device due to parasitic transistors and leakage currents caused by concentration of an electric field at the edge of the binary STI.

In general, with the progress of semiconductor technology, the speed and the high integration of semiconductor devices are further progressed. As a result, the necessity of miniaturization of the pattern is increasing, and the dimension of the pattern is required to be highly precise. This also applies to device isolation regions that occupy a wide area in semiconductor devices.

LOCOS oxide films are mostly used as device isolation films of current semiconductor devices. This LOCOS device isolation film is obtained by selectively localizing a substrate.

However, the LOCOS isolation layer has a disadvantage in that a bird-shaped bird's beak is generated at an edge thereof, thereby generating a leakage current while increasing the area of the isolation layer.

Accordingly, a device isolation film having a shallow trench isolation (STI) method having a small width and excellent device isolation characteristics has been proposed. 1A and 1B, a conventional STI device isolation film forming method will be described.

First, as shown in FIG. 1A, a silicon oxide film 2 serving as a buffer and a silicon nitride film 3 that inhibits oxidation are sequentially formed on the silicon substrate 1. Next, a resist pattern 4 is formed on the silicon nitride film 3 to expose the device isolation region. In this case, the resist pattern 4 is formed using a deep ultra violet (DUV) light source having excellent resolution to form a thin device isolation layer. Thereafter, using the resist pattern 4 as a mask, the silicon nitride film 3, the silicon oxide film 2, and the semiconductor substrate 1 are etched by a predetermined depth to form a shallow trench ST. After the resist pattern 4 is removed by a known method, the insulating film 5 is embedded in the shallow trench ST. Subsequently, the silicon nitride film 3 and the silicon oxide film 2 on the surface of the semiconductor substrate 1 are removed by a known method to complete the STI device isolation film (FIG. 1B).

The conventional STI formation method is a furnace for improving the interfacial properties such as rounding of the STI edge or reducing the defect and trap charge of the Si interface after performing an ISO mask and etching. Si-recess scheme using a process such as wall SAC (Self Align Contact) oxidation (1100 ℃ dry oxidation) and wall oxidation (800 ℃ wet oxidation). Used. Here, there is a pretreatment cleaning process using hydrogen fluoride (HF) to remove the oxide film proceeded during the process, which leads to a loss of the pad oxide film.

At this time, the bottom edge (a) of the STI has a rounding corner secured to some extent, as shown in the enlarged process photograph of FIG. 1C, but is rounded at the top corner (b) adjacent to the pad nitride film. It can be seen that the effect is not so great (see FIGS. 1C and 1D).

At the top corner (b) of the STI, the oxidation proceeds too much toward the pad oxide layer due to the continuous oxidation, so that the void after high density plasma (HDP) oxide filling and densification proceeds. Will be present. This causes a problem that adversely affects the device characteristics such as when the electric field is applied to the device is concentrated on this unstable STI edge causing leakage current.

Accordingly, the present invention has been made to solve the above problems, and the present invention is a rounding process of the edge portion of the STI, the malfunction of the device due to parasitic transistor and leakage current caused by the concentration of the electric field on the edge of the angled STI and SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a device isolation film of a semiconductor device which prevents deterioration of characteristics.

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In order to achieve the above object, the present invention is a step of depositing a pad oxide film and a pad nitride film on a silicon substrate in order to define a shallow trench by performing an ISO mask and etching process, and by etching the pad nitride film by the blanket etching Opening the edge of the top portion of the low trench about 100 ~ 200Å, and after the blanket etching the pad nitride film, the annealing process by a high temperature rapid heating method (RTP) is carried out in an atmosphere that can move and convert the silicon atoms Forming an edge of the top and bottom portions of the shallow trenches in a round shape; Trench filling is performed, and then magnetization is performed to densify and deposit the oxide film. Performing a chemical mechanical polishing (CMP) process on the densified product after quenching, and stripping the nitride film to complete a device isolation film having a rounded shallow trench corner. It provides a formation method.
In the device isolation film forming method of the semiconductor device according to the present invention, the annealing process by the high temperature rapid heating method (RTP) is carried out loading and unloading to 350 ~ 500 ℃, the main annealing process is 900 ~ 1000 ℃ temperature It is characterized by advancing in the range.
In the method of forming a device isolation film of a semiconductor device according to the present invention, the annealing process by the high temperature rapid heating method (RTP) is characterized in that it is carried out at a low pressure of 0.1 to 2 Torr.
In the device isolation film forming method of the semiconductor device according to the present invention, the annealing process time by the high temperature rapid heating method (RTP) is characterized in that about 0.5 to 5 seconds under the above process conditions.

(Example)
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
In addition, in all the drawings for demonstrating an embodiment, the thing which has the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

2A to 2F are cross-sectional views for explaining a device isolation film formation method of a semiconductor device according to the present invention.                     

First, a silicon oxide film 12 serving as a buffer on the silicon substrate 11 is formed to have a thickness of 50 to 100 으로 by an oxidation process, and then a silicon nitride film (Si ₃ N ₄ ) that suppresses oxidation on the silicon oxide film 12. (13) is deposited to a thickness of 900 to 1500 kPa. Next, a resist pattern (not shown) is formed on the silicon nitride film 13 to expose the device isolation region. In this case, the resist pattern is formed using a deep ultra violet (DUV) light source having excellent resolution to form a thin device isolation layer. Thereafter, using the resist pattern as a mask, the silicon nitride film 13, the silicon oxide film 12, and the semiconductor substrate 11 are etched by a predetermined depth to form a shallow trench ST. Thereafter, removing the resist pattern by a known method, an STI trench is formed as shown in FIG. 2A. At this time, the bottom corner portion (a) and the top corner portion (b) of the STI trench are formed in an angled form as in the conventional case.

The following process will be explained with reference to FIG. 2B.

After the process, the silicon nitride film 13 is blanket-etched to a thickness of about 100 to about 200 Å so that the top corner portion b of the STI is opened. In this case, the caution in the blanket etching process should be maintained at an appropriate level because the active area is reduced if too much etching.

After the above process, an annealing process is performed by a rapid thermal process (RTP) for a predetermined pressure and a predetermined time in a temperature range of 900 to 1000 ° C. in a hydrogen (H ₂ ) atmosphere. At this time, the movement of silicon (Si) atoms is induced, and as shown in FIG. 2C, rounding is performed on both the bottom corner a 'and the top corner b' of the STI.

By adjusting the annealing time in the above process, it is possible to secure a rounding edge having a radius of curvature of several tens to hundreds of microseconds.

A liner oxide film 14 is deposited on the STI trench structure thus formed at about 50 to 150 microseconds (FIG. 2D) to remove Si interface defects and reduce trap charge.

After the process, the trench is filled with a high density plasma (HDP) oxide film 15 having a very high deposition rate, and then densification using a furnace is formed as shown in FIG. 2E. That is, the shape of the trench portion of the HDP oxide film 15 is formed like the shape of the trench in which the top corner portion has a rounded shape.

Thereafter, if the silicon nitride film 13 is removed after two chemical & mechanical polishing (CMP) processes, the silicon nitride film 13 is formed at the top corner of the trench. An STI structure having a shape with a groove formed therein is completed.

As described above, according to the device isolation film forming method of the semiconductor device of the present invention, if the Si interface stabilization is achieved while the STI edge is rounded by RTP annealing, an unnecessary process (wall SAC oxidation (1100 ° C. dry oxidation) is performed. ) And wall oxidation (800 ° C wet oxidation) can be omitted, as well as a stable STI structure without voids. In addition, it is possible to improve the yield by suppressing the generation of parasitic transistors that seriously affect the device characteristics, reducing the leakage current, and improving the device characteristics such as I _d -V _G characteristics. You can expect

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (5)

Depositing a pad oxide film and a pad nitride film on a silicon substrate in turn, and performing an ISO mask and etching process to define a shallow trench; Blanket etching the pad nitride layer to open the edge of the top portion of the shallow trench by about 100 to about 200 microseconds; After etching the pad nitride film, the annealing process is performed by high temperature rapid heating (RTP) in an atmosphere in which silicon atoms can be moved and converted to form edges of the top and bottom portions of the shallow trenches in a round shape. Steps, Depositing an oxide film on a result of rounding the edges of the top and bottom portions of the shallow trench to form a trench filling with a high density plasma (HDP) oxide film and then densifying by magnetizing; Performing a chemical mechanical polishing (CMP) process on the densified product after depositing the oxide film, and then stripping the nitride film to complete a device isolation film having rounded shallow trench corners. A device isolation film formation method of a device. The method of claim 1, The annealing process by the high temperature rapid heating method (RTP) is a device isolation film forming method of a semiconductor device, characterized in that the progress in the hydrogen (H ₂ ) atmosphere. The method of claim 1, The annealing process by the high temperature rapid heating method (RTP) is a device isolation film of a semiconductor device, characterized in that the loading and unloading proceeds to 350 ~ 500 ℃, the main annealing process proceeds in a temperature range of 900 ~ 1000 ℃ Formation method. The method of claim 1, The annealing process by the high temperature rapid heating method (RTP) is performed in a low pressure condition of 0.1 to 2 Torr. The method of claim 1, And an annealing process time by the high temperature rapid heating method (RTP) is about 0.5 to 5 seconds under the process conditions.

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