KR20020056266A - Method for manufacturing isolation layer in semiconductor device - Google Patents
Method for manufacturing isolation layer in semiconductor device Download PDFInfo
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- KR20020056266A KR20020056266A KR1020000085588A KR20000085588A KR20020056266A KR 20020056266 A KR20020056266 A KR 20020056266A KR 1020000085588 A KR1020000085588 A KR 1020000085588A KR 20000085588 A KR20000085588 A KR 20000085588A KR 20020056266 A KR20020056266 A KR 20020056266A
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- 238000002955 isolation Methods 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 26
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims description 19
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 2
- 238000000280 densification Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 238000011049 filling Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 238000001035 drying Methods 0.000 claims 1
- 239000010408 film Substances 0.000 description 56
- 238000007796 conventional method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Computer Hardware Design (AREA)
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Abstract
Description
본 발명은 반도체 소자의 소자분리막 제조방법에 관한 것으로, 보다 구체적으로는, 소자분리막 모서리를 라운딩 할 수 있는 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a device isolation film of a semiconductor device, and more particularly, to a manufacturing method that can round the corners of the device isolation film.
일반적으로 실리콘 웨이퍼에 형성되는 반도체 장치는 개개의 회로 패턴들을전기적으로 분리하기 위한 소자 분리 영역을 포함한다. 특히 반도체 장치가 고집적화 되고 미세화 되어감에 따라 각 개별 소자의 크기를 축소시키는 것뿐만 아니라 소자 분리 영역의 축소에 대한 연구가 활발히 진행되고 있다. 그 이유는 소자 분리 영역의 형성은 모든 제조 단계에 있어서 초기 단계의 공정으로서, 활성영역의 크기 및 후공정 단계의 공정마진을 좌우하게 되기 때문이다.In general, semiconductor devices formed on silicon wafers include device isolation regions for electrically separating individual circuit patterns. In particular, as semiconductor devices have been highly integrated and miniaturized, research into not only the size of each individual device but also the device isolation region has been actively conducted. The reason for this is that the formation of the device isolation region is an initial step in all the manufacturing steps, and depends on the size of the active area and the process margin of the post-process step.
일반적으로 반도체 장치의 제조에 널리 이용되는 로코스 소자분리 방법은 공정이 간단하다는 이점이 있지만 256M DRAM급 이상의 고집적화되는 반도체 소자에 있어서는 소자 분리 영역의 폭이 감소함에 따라 버즈비크(Bird' Beak)에 의한 펀 치쓰루(Punch-Through)와 소자 분리막의 두께 감소로 인하여 그 한계점에 이르고 있다.In general, the Locos device isolation method widely used in the manufacture of semiconductor devices has the advantage of simple process, but in the case of highly integrated semiconductor devices of 256M DRAM level or more, the width of the device isolation region decreases in the bird's beak. Due to the punch-through and thickness reduction of the device isolation layer, the limit point is reached.
이에따라, 고집적화된 반도체 장치의 소자 분리에 적합한 기술로 트랜치를 이용한 소자 분리 방법, 예컨대 샬로우 트랜치 분리방법(Shallow Trench Isolation: 이하, STI)이 제안되었다.Accordingly, a device isolation method using a trench, such as a shallow trench isolation method (STI), has been proposed as a technique suitable for device isolation of highly integrated semiconductor devices.
먼저, 도 1a를 참조하면, 실리콘 기판(1)상에 버퍼 역할을 하는 패드 산화막(2)과 산화를 억제하는 실리콘 질화막(3)을 순차적으로 형성한다. 다음, 실리콘 질화막(3) 상부에 소자 분리 예정 영역을 형성시키기 위한 감광막 패턴(4)을 형성한다. 이때, 감광막 패턴(4)은 얇은 폭의 소자 분리막을 형성하기 위하여 해상도가 우수한 DUV(deep ultra violet)광원을 이용하여 형성한다.First, referring to FIG. 1A, a pad oxide film 2 serving as a buffer and a silicon nitride film 3 inhibiting oxidation are sequentially formed on the silicon substrate 1. Next, a photosensitive film pattern 4 for forming a device isolation region is formed on the silicon nitride film 3. In this case, the photoresist pattern 4 is formed using a deep ultra violet (DUV) light source having excellent resolution in order to form a thin device isolation layer.
그 다음 도 1b를 참조하면, 상기 감광막 패턴(4)을 마스크로 하여, 실리콘 질화막(3), 패드 산화막(2) 및 실리콘 기판(1)을 소정 깊이만큼 식각하여, 샬로우트랜치(ST)를 형성한다.Next, referring to FIG. 1B, the shallow trench ST is etched by etching the silicon nitride film 3, the pad oxide film 2, and the silicon substrate 1 by a predetermined depth using the photosensitive film pattern 4 as a mask. Form.
그 다음, 상기 감광막 패턴을 제거하고, 트랜치 식각시 유발되는 스트레스를 제거하기 위해 트랜치(ST)가 형성된 실리콘 기판(1)상에 희생산화막(도시되지않음) 형성 및 제거함으로써 식각 데미지를 완화하고, 이어서 사이드 월 산화(side wall oxidation)공정을 수행하여 트랜치내에 박막의 산화막(5)을 형성한다.Then, the etching damage is alleviated by removing and removing the photoresist pattern and forming and removing a sacrificial oxide film (not shown) on the silicon substrate 1 on which the trench ST is formed to remove stress caused during trench etching. Subsequently, a side wall oxidation process is performed to form a thin film oxide film 5 in the trench.
이어서, 상기 박막의 산화막(5)이 형성된 트랜치(ST)내를 매립하는 갭필옥사드막(6), 예컨대, 고밀도 플라즈마(이하, HDP) 산화막을 형성하고 상기 갭필옥사이드막(6)을 화학기계연마하여 실리콘 질화막(3)이 노출되도록 평탄화한 후, 상기 실리콘 질화막(3) 및 패드산화막(2)을 차례로 제거하여 반도체 소자의 소자분리막을 형성한다.Subsequently, a gap fill oxide film 6 filling the inside of the trench ST in which the thin film oxide film 5 is formed, for example, a high-density plasma (hereinafter referred to as HDP) oxide film is formed and the gap fill oxide film 6 is subjected to chemical mechanical polishing. After the silicon nitride film 3 is planarized to be exposed, the silicon nitride film 3 and the pad oxide film 2 are sequentially removed to form a device isolation film of a semiconductor device.
그러나, 종래 기술에 따른 반도체 소자의 소자분리막은 다음과 같은 문제점이 있다.However, the device isolation film of the semiconductor device according to the prior art has the following problems.
소자분리막을 구현하는 종래의 방법에서는 STI 식각을 수행한 다음, HDP 산화막을 매립하고 후속 열공정과 산화막 식각 공정을 거쳐 최종형태의 STI를 형성하게 되는데, STI 구조적 특성에 의해 전류(Id)와 전압(Vg)간에 험프(hump) 특성이 나타날 개연성이 아주 크다.In the conventional method of implementing a device isolation film, after performing STI etching, the HDP oxide is buried, and the final STI is formed through a subsequent thermal process and an oxide etching process. There is a high probability that the hump characteristic will appear between (Vg).
상기 험프 특성은 리프레쉬(refresh) 특성에 악영향을 미치는 것으로 알려져 있으며 이를 억제하기 위한 시도들이 현재에도 진행중이다. 그 일반적인 방법중에 한가지가 STI의 상부 모서리를 라운딩(rounding)하여 전계집중현상(Electric fieldcrowding)을 줄여주는 것인데, 종래의 방법을 통해서는 험프 특성을 완전히 제어할 수 있을 정도의 라운딩이 형성되지 못하는 것이 현실이다.The hump characteristic is known to adversely affect the refresh (refresh) characteristics and attempts to suppress it are still ongoing. One common method is to round the top edge of the STI to reduce the electric fieldcrowding.However, conventional methods do not provide enough rounding to fully control the hump characteristics. It is a reality.
특히, STI에 채워진 HDP 산화막의 식각량이 과다하여 후속 게이트 산화시 STI의 상부 모서리가 노출이 심하게 되면 STI 상부 모서리의 면방향 차이에 의한 산화량 차이로 STI상부 모서리와 소자의 액티브영역 사이에 이중 경사(slope)가 발생한다.In particular, if the etching amount of the HDP oxide film filled in the STI becomes excessive and the upper edge of the STI is exposed during the subsequent gate oxidation, the difference in oxidation amount due to the surface direction difference of the upper edge of the STI causes a double slope between the upper edge of the STI and the active region of the device. (slope) occurs.
결과적으로 STI 상부 모서리가 뾰족해져 전계집중현상에 의한 험프(hump) 특성의 개연성이 커지게 되는 것이다.As a result, the top edge of the STI is sharpened to increase the probability of the hump characteristic caused by the field concentration phenomenon.
따라서, 상기와 같은 문제점을 해결하기 위한 본 발명의 목적은, 상기 트랜치 상단을 종래의 방법과는 다른 공정을 통하여 라운딩함으로써, 트랜치 형성의 안정성을 확보할 수 있는 반도체 소자의 소자분리막 형성방법을 제공하는 것이다.Accordingly, an object of the present invention for solving the above problems is to provide a device isolation film forming method of a semiconductor device that can ensure the stability of the trench formation by rounding the upper end of the trench through a process different from the conventional method. It is.
도 1a 및 도 1b는 종래 기술에 따른 반도체 소자의 소자분리막 제조방법을 설명하기 위한 제조공정도.1A and 1B are manufacturing process diagrams for explaining a device isolation film manufacturing method of a semiconductor device according to the prior art.
도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 소자분리막 제조방법을 설명하기 위한 제조공정도.Figure 2a to 2d is a manufacturing process diagram for explaining a device isolation film manufacturing method of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호설명 ** Explanation of Signs of Major Parts of Drawings *
11 : 실리콘 기판 12 : 패드산화막11 silicon substrate 12 pad oxide film
13 : 실리콘 질화막 13a : 잔류된 실리콘 질화막13: silicon nitride film 13a: remaining silicon nitride film
14 : 감광막 패턴 15 : 트랜치14 photosensitive film pattern 15 trench
16 : 배리어막 17 : 갭필옥사이드막16 barrier film 17 gap fill oxide film
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 소자분리막 형성 방법은, 실리콘 기판상에 패드산화막과 실리콘 질화막을 차례로 증착하는 단계; 상기 실리콘 질화막과 패드산화막 소정부분을 제1 식각하여 상기 실리콘 기판에 트랜치를 형성하는 단계; 상기 트랜치 내부에 소정의 배리어막을 형성하는 단계; 상기 배리어막이 형성된 결과물을 제2 식각하여 상기 트랜치 모서리 상부에 있는 실리콘 질화막 소정부분을 제거하는 단계; 및 상기 단계까지의 결과물상에 갭필 옥사이드막을 매립시키는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a device isolation film of a semiconductor device, comprising sequentially depositing a pad oxide film and a silicon nitride film on a silicon substrate; Forming a trench in the silicon substrate by first etching the silicon nitride layer and a predetermined portion of the pad oxide layer; Forming a barrier layer in the trench; Second etching the resultant material on which the barrier layer is formed to remove a predetermined portion of the silicon nitride layer on the trench edge; And embedding a gapfill oxide film on the resultant up to this step.
이하, 본 발명의 바람직한 실시예를 첨부한 도면에 의거하여 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위한 제조공정도이다.2A to 2D are manufacturing process diagrams for explaining a method of forming an isolation layer in a semiconductor device according to the present invention.
먼저, 도 2a에 도시된 바와같이, 실리콘 기판(11)상에 버퍼 역할을 하는 100Å 두께의 패드 산화막(12)과 산화를 억제하는 실리콘 질화막(13)을 순차적으로 형성한다. 그 다음, 상기 실리콘 질화막(13) 상부에 소자 분리 예정 영역을 형성시키기 위한 감광막 패턴(14)을 형성한다. 이 때, 감광막 패턴(14)은 얇은 폭의 소자 분리막을 형성하기 위하여 해상도가 우수한 DUV(deep ultra violet)광원을 이용하여 형성한다.First, as shown in FIG. 2A, a pad oxide film 12 having a thickness of 100 하는 serving as a buffer and a silicon nitride film 13 that inhibits oxidation are sequentially formed on the silicon substrate 11. Next, a photosensitive film pattern 14 for forming a device isolation region is formed on the silicon nitride film 13. At this time, the photosensitive film pattern 14 is formed using a deep ultra violet (DUV) light source having excellent resolution in order to form a thin device isolation layer.
그 다음, 도 2b에 도시된 바와같이, 상기 감광막 패턴(14)을 식각장벽으로, 상기 실리콘 질화막(13), 패드 산화막(12) 및 반도체 기판(11)을 소정 깊이만큼 제1 식각공정을 수행하여 트랜치(15)를 형성한다.Next, as shown in FIG. 2B, a first etching process is performed on the silicon nitride film 13, the pad oxide film 12, and the semiconductor substrate 11 by a predetermined depth with the photoresist pattern 14 as an etch barrier. To form the trench 15.
그 다음, 상기 감광막 패턴(14)을 제거한 다음, 전처리 공정으로 세정공정을 실시한다. 이어서, 상기 트랜치(15) 식각시 유발되는 스트레스를 제거하고 상기 실리콘 기판(11)을 보호하기 위해, 트랜치(15)가 형성된 실리콘 기판(11)상에 희생 산화막(미도시) 형성 및 제거공정을 수행하며, 트랜치(15) 내부에 배리어막(16)을 형성한다.Then, the photosensitive film pattern 14 is removed, and then a cleaning step is performed by a pretreatment step. Subsequently, in order to remove stress caused during etching of the trench 15 and to protect the silicon substrate 11, a sacrificial oxide film (not shown) is formed and removed on the silicon substrate 11 on which the trench 15 is formed. The barrier layer 16 is formed in the trench 15.
이 때, 상기 배리어막(16)은 박막의 산화막으로 온도 1050℃에서 건식산화 방식으로 바람직하게는 적어도 100Å 두게로 형성한다.At this time, the barrier film 16 is a thin film oxide film is formed at a dry oxidation method at a temperature of 1050 ℃, preferably at least 100 Å thick.
그 다음, 도 2c에 도시된 바와같이, 상기 배리어막(16)이 형성된 결과물을제2 식각하여 상기 실리콘 질화막 상부면이 소정부분 식각하면서, 상기 트랜치(15) 모서리 상부에 있는 실리콘 질화막(13)을 제거한다.Next, as illustrated in FIG. 2C, the silicon nitride layer 13 disposed on the corners of the trench 15 may be etched by etching a second portion of the product on which the barrier layer 16 is formed to etch the upper portion of the silicon nitride layer. Remove it.
이 때, 상기 제2 식각은 습식식각 또는 건식식각을 이용할 수 있는데, 상기 습식식각은 온도 100 ~ 170℃ 하에서 인산(H3PO4)을 이용하여 등방성 식각을 진행하고, 상기 건식식각은 c1계 가스를 이용하여 진행할 수 있다.In this case, the second etching may use wet etching or dry etching, wherein the wet etching isotropically etched using phosphoric acid (H 3 PO 4 ) under a temperature of 100 to 170 ° C., and the dry etching is based on c1 system. Proceed with gas.
상기 제2 식각후 잔류된 실리콘 질화막(13a)의 두께는 바람직하게 100 ~ 3000Å정도이다.The thickness of the silicon nitride film 13a remaining after the second etching is preferably about 100 to 3000 mm 3.
그 다음, 도 2d에 도시된 바와같이, 상기 단계까지의 결과물상에 트랜치(15)내를 매립하는 갭필옥사이드막(17), 예컨대, HDP(High Density Plasma) 산화막을 형성한다. 이 때, 상기 트랜치(15) 상부 모서리가 노출되어있기 때문에 갭필되는 DHP 산화막의 밀도는 종래의 기술에 비하여 상대적으로 밀도가 크다.Then, as shown in FIG. 2D, a gap fill oxide film 17, for example, an HDP (High Density Plasma) oxide film, is formed on the resultant up to this step. At this time, since the upper edge of the trench 15 is exposed, the density of the gap-filled DHP oxide film is relatively higher than that of the prior art.
그 다음, 상기 갭필옥사이드막(17)상에 치밀화(densification) 공정을 수행한 다음, 고온, 예컨대, 1150℃에서 건식방식으로 산화공정을 수행하여 트랜치 모서리를 라운딩시킨다.Next, a densification process is performed on the gap fill oxide layer 17, and then a trench edge is rounded by performing an oxidation process at a high temperature, for example, at 1150 ° C. in a dry manner.
그 다음. 도면에는 도시하지 않았지만, 상기 잔류된 실리콘 질화막(13a)이 노출될 때까지 상기 갭필옥사이드막(17)을 화학기계연마(CMP)하여 평탄화시키고 이어서, 상기 잔류된 실리콘 질화막(13a) 및 패드 산화막(12)을 제거하여 반도체 소자의 소자분리막을 형성한다.next. Although not shown in the drawing, the gap fill oxide film 17 is planarized by chemical mechanical polishing (CMP) until the remaining silicon nitride film 13a is exposed, and then the remaining silicon nitride film 13a and the pad oxide film ( 12) is removed to form a device isolation film of the semiconductor device.
상기한 바와같은 반도체 소자의 소자분리막 제조방법은 다음과 같은 효과가 있다.The device isolation film manufacturing method of the semiconductor device as described above has the following effects.
상기 트랜치 상부 모서리 상부에 있는 실리콘 질화막을 식각하여 모서리 부분을 노출시킴으로써, 이후 공정에서 트랜치 상부 모서리의 HDP 산화막 밀도 증가와 라운딩 효과를 증가시킬 수 있다. 또한, 호(Moat)의 최소화를 통한 험프(Hump) 특성을 개선하여 반도체 소자의 특성을 향상시킬 수 있다.By etching the silicon nitride layer on the upper corner of the trench to expose the corner portion, it is possible to increase the HDP oxide density and the rounding effect of the upper corner of the trench in a subsequent process. In addition, it is possible to improve the characteristics of the semiconductor device by improving the hump (Hump) characteristics by minimizing the (Moat).
한편, 본 발명의 요지를 벗어나지 않는 범위내에서 다양하게 변경하여 실시 할 수 있다.On the other hand, various changes can be made without departing from the spirit of the invention.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100541707B1 (en) * | 2002-12-09 | 2006-01-11 | 매그나칩 반도체 유한회사 | Method for forming isolation layer of semiconductor device |
| KR100935191B1 (en) * | 2002-12-20 | 2010-01-06 | 매그나칩 반도체 유한회사 | Method for forming element isolation of semiconductor device |
| KR101127033B1 (en) * | 2004-12-07 | 2012-03-26 | 매그나칩 반도체 유한회사 | Semiconductor Device and Method for Forming STI Type Device Isolation Film of Semiconductor Device |
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2000
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100541707B1 (en) * | 2002-12-09 | 2006-01-11 | 매그나칩 반도체 유한회사 | Method for forming isolation layer of semiconductor device |
| KR100935191B1 (en) * | 2002-12-20 | 2010-01-06 | 매그나칩 반도체 유한회사 | Method for forming element isolation of semiconductor device |
| KR101127033B1 (en) * | 2004-12-07 | 2012-03-26 | 매그나칩 반도체 유한회사 | Semiconductor Device and Method for Forming STI Type Device Isolation Film of Semiconductor Device |
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