KR100638750B1 - Method for fabricating capacitor in semiconductor device - Google Patents

Abstract

A method for fabricating a capacitor in a semiconductor device is provided to improve step coverage in forming a metal layer made of a three-dimensional lower electrode by more reliably forming a lower electrode of a capacitor in a high-integrated semiconductor device having a size of 60 nanometers or so. A sacrificial layer is formed on a substrate. The sacrificial layer is selectively removed to form a hole for a capacitor. A metal seed layer is formed on the inner surface of the hole by using plasma. A metal layer is formed as a lower electrode on the metal seed layer by an ALD method. The sacrificial layer is removed. A dielectric thin film and an upper electrode are formed on the lower electrode. The process for forming the metal seed layer includes the following steps. Source gas is injected to a region for forming the metal seed layer. The unreacted source gas is purged. Reaction gas is injected. The unreacted reaction gas is purged. A plasma treatment is performed on a region for forming the metal seed layer.

Description

METHODS FOR FABRICATING CAPACITOR IN SEMICONDUCTOR DEVICE}

1 is a process cross-sectional view showing a problem in a capacitor manufacturing method of a semiconductor device according to the prior art.

2A to 2E are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with a preferred embodiment of the present invention.

3 is a graph showing an atomic layer deposition method for manufacturing a capacitor of a semiconductor device according to the present invention.

4 is a graph showing an atomic layer deposition method for manufacturing a capacitor of a semiconductor device according to the second embodiment of the present invention.

FIG. 5 is a graph showing the characteristics of a film deposited according to the atomic layer deposition method of FIG.

Explanation of symbols on the main parts of the drawings

30 substrate 31 etching stop film

32: capacitor sacrificial film 33: seed layer

34: lower electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method of manufacturing a capacitor of a semiconductor device having a three-dimensional structure.

As the degree of integration of semiconductor memory devices, in particular DRAM (Dynamic Random Access Memory), increases, the area of memory cells, which are basic units for information storage, has been rapidly reduced.

Such a reduction in the memory cell area is accompanied by a reduction in the area of the cell capacitor, thereby lowering the sensing margin and the sensing speed, and causes a problem that the durability against soft errors caused by α-particles is degraded. Accordingly, there is a need for a method capable of securing sufficient capacitance in a limited cell area.

The capacitance C of the capacitor is defined as in Equation 1 below.

C = εAs / d

Is the dielectric constant, As is the effective surface area of the electrode, and d is the distance between the electrodes. Therefore, in order to increase the capacitance of the capacitor, it is necessary to increase the surface area of the electrode, reduce the thickness of the dielectric thin film, or increase the dielectric constant.

Among them, a method of increasing the effective surface area of the electrode in a limited layout area by first making a three-dimensional form of the electrode structure of the capacitor, such as a concave structure and a cylinder structure, was first considered.

The concave structure forms a hole in which an electrode of a capacitor is to be formed in an insulating film, a lower electrode of a capacitor is formed on an inner surface of the hole, and a dielectric thin film and an upper electrode are formed thereon. The cylinder structure forms a hole in which the electrode of the capacitor is to be formed in the insulating film, forms a lower electrode of the capacitor in the hole, removes the insulating film used as a formwork, and then removes the dielectric thin film and the upper electrode along the remaining lower electrode surface. It is a form laminated in order.

Therefore, the cylinder structure can use both the inner and outer surfaces of the lower electrode as the effective surface area of the capacitor, thereby forming a capacitor having a larger capacitance in a limited area than the concave structure.

1 is a process cross-sectional view showing a problem in a capacitor manufacturing method of a semiconductor device according to the prior art.

As shown in FIG. 1, a contact plug 11 is formed on the substrate 10, an insulating film 13 is formed, and then a hole is formed to expose the contact plug 11.

Subsequently, a conductive film is formed on the inner surface of the hole, and then an insulating film is removed to form a lower electrode. For reference, membrane 12 is an etch stop membrane.

As described above, as the memory devices are highly integrated, the area for manufacturing capacitors is gradually decreasing. However, since the required capacitance of the capacitor is more than a certain size, in order to secure more capacitance in a limited area, the lower electrode of the capacitor is formed in three dimensions, and the lower electrode also uses a metal film.

Therefore, as shown in FIG. 1, the holes for forming the capacitor are narrower in width and deeper in depth, making it difficult to stably form the lower electrode.

In detail, if the lower electrode of the capacitor is to be used as a metal, the density of the film must be increased so that no agglomeration occurs in a subsequent process and the step coverage must be 80% or more.

In the case of forming a lower electrode by using a Ru film by the conventional CVD method, a lot of impurities (carbon, hydrogen, oxygen, etc.) in the film are included, and the density is low (~ 7g / cm3, 12.2 for bulk Ru, 12.2 for PVC Ru). 11.9) There is a problem that a lumping phenomenon occurs in a subsequent process and cannot maintain a stable form.

In terms of step coverage, it is expected that a hole for forming a capacitor lower electrode is CD 100 nm or less and an aspect ratio of 20: 1 or more is difficult to form a lower electrode in a device of 60 nm or less.

It is essential to use atomic layer deposition to form a metal film containing few impurities in such a high aspect ratio hole.

However, at present, the atomic layer deposition process forms on the oxide wing during the lower electrode lower electrode deposition process, which hardly deposits for several hundred cycles (incubation time), and after several hundred cycles, the oxide surface is covered and then at normal speed (~ 0.8 A / cycle) deposition takes place.

Such a problem is that the source has a low probability of reaching the lower electrode portion having a high aspect ratio, and thus, the lower electrode portion has a longer time to substantially cover the Ru film, and as a result, a desired step coverage cannot be obtained.

In addition, 250 cycles are required to obtain a lower electrode of Ru ~ 200 μs. Incubation time is a serious problem because the actual deposition time takes more than twice.

It takes a long time that the lower electrode metal film is covered at the lower end of the hole where the lower electrode is to be formed, and thus, even during normal deposition on the upper part, the lower part is not deposited, resulting in poor step coverage.

An object of the present invention is to provide a method for manufacturing a capacitor of a semiconductor device which can improve step coverage when forming a metal film as a three-dimensional lower electrode.

The present invention comprises the steps of forming a sacrificial film on a substrate; Selectively removing the sacrificial layer to form a hole in which a capacitor is to be formed; forming a metal seed layer using plasma on an inner surface of the hole; Forming a metal film as a lower electrode on the metal seed layer by using atomic layer deposition; Removing the sacrificial layer; And forming a dielectric thin film / top electrode on the bottom electrode.

The present invention is to improve the step coverage of the deposition process for forming a metal film as the lower electrode. To this end, a metal film (Ru, Ir, Pt, Pd) deposition process is carried out in two steps. For the first layer, a process can be used to minimize the incubation time even on the oxide film. The application process uses PEALD process using plasma as reaction energy by adding reactant in atomic layer deposition process, or plasma processing step in addition to source injection / purge injection / reactant injection / purge injection process in conventional atomic layer deposition process Using a process to add, or to the plasma treatment instead of the actual deposition.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2A to 2E are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to a preferred embodiment of the present invention.

As shown in FIG. 2A, in the method of manufacturing a capacitor of a semiconductor device according to the present embodiment, first, a contact plug is formed on a substrate 30, an etch stop layer 31 and an interlayer insulating layer 32 are formed, and then etched. The stop layer 31 and the interlayer insulating layer 32 are patterned to form holes for forming the lower electrode of the capacitor to which the contact plug is exposed. At this time, the etch stop layer 31 serves to stop the etching process when the interlayer insulating layer 32 is patterned.

Subsequently, as shown in FIG. 2B, the seed layer 33 is formed by adding a plasma treatment step after the PEALD or atomic layer deposition process using plasma as a method of minimizing incubation time and depositing a seed layer having excellent step coverage. .

Subsequently, as shown in FIG. 2C, an ALD method and a CVD method are mixed on the seed layer 33 to form a lower electrode.

At this time, the entire surface of the hole for forming the lower electrode already covers the seed layer, so that the lower electrode can be formed without deterioration of step coverage due to the incubation timing.

In this case, the first method of forming the lower electrode may be deposited using a general atomic layer deposition method.

In the second method, the source gas and the reaction gas may be injected at the same time, and the CVD reaction may be performed for a short time, and after the purge, only the reaction gas may be flowed to expect an annealing effect (reaction byproduct removal and densification).

In the step of flowing only the reaction gas, a plasma treatment process may be additionally applied.

The third method is to reduce the purge time to zero in a typical ALD process, allowing CVD to occur at the end of each step, or to reduce the cycle time and continue to increase the deposition rate with the CVD method. have.

Fourth, while the reaction gas continues to flow and the source gas is intermittently supplied, the source is deposited by CVD when the source is supplied, and when only the reaction gas enters, the process of obtaining the densification effect of the film is used.

Fifthly, it is possible to use a process of depositing by the CVD method when the source gas is continuously flowed, the reaction gas is intermittently supplied, and the reaction gas and the source gas are simultaneously supplied as opposed to the fourth case.

In the second and fifth methods described above, a plasma treatment process may be used when the reaction gas enters, and a cycle time is reduced compared to the conventional ALD (or PEALD) method, and the deposition is performed by CVD method periodically, thereby obtaining a fast deposition rate. . Thin film properties are also superior to pure CVD thin films because there are steps to remove reactants within the cycle.

In this case, NH ₃ , N ₂ O, H ₂ H ₄ , ME ₂ N ₂ H ₂ (dimethylhydrazine), H _2, and a mixed film thereof are used in the plasma treatment step.

3 and 4 illustrate a process cycle for the lower electrode deposition method applied in the present invention. As shown in FIG. 3A, the plasma is turned on in a cycle of adding the reaction gas in the PEALD process, or as shown in FIG. 3B. When the reaction gas and the source gas are not reactive, the reaction gas flows instead of the purge gas, and only the plasma is turned on at the time to react to shorten the time for entering the purge.

FIG. 5 is a graph showing thicknesses deposited for each cycle during the process of performing atomic layer deposition and plasma treatment.

As shown in Fig. 5, it can be seen that a fast deposition rate can be obtained without incubation time. MPALD represents the formation of a seed layer by an ALD + plasma treatment process, and ALDonSeed represents the rate of deposition on the seed layer.

Subsequently, as shown in FIG. 2D, the lower electrode film 34 on the insulating film is removed using a chemical mechanical polishing process or the like.

Subsequently, as shown in FIG. 2E, when the insulating film is removed, the lower electrode of a cylindrical shape is completed.

Subsequently, a dielectric thin film is formed on the cylindrical lower electrode. As the dielectric thin film, a single layer such as HFO2, Al2O3, Ta2O5, La2O3, ZrO2, TiO2, STO, BST, PZT, BLT, SBT, etc. may be used, or a laminated structure or a composite film of these layers may be used.

Subsequently, an upper electrode is formed on the dielectric thin film. The upper electrode uses a conductive silicon film or a TiN film doped with As, P, or the like. In the case of a metal film, the above-described two steps may be used.

In the above-described process, as the lower electrode metal film, Ru, Pt, Rh, Pd, Hf, Ti, W, Ta, and a nitride film or a conductive oxide film synthesized therewith are used.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, it can be applied to the lower electrode forming process when manufacturing a capacitor of FeRAM device having a design rule of 150nm or less.

According to the present invention, the lower electrode of the capacitor can be formed more reliably in a high-density semiconductor device of about 60 nm, and therefore, the reliability improvement and operational reliability can be expected in the manufacturing process of the semiconductor device.

Claims (9)

Forming a sacrificial film on the substrate; Selectively removing the sacrificial layer to form a hole in which a capacitor is to be formed; Forming a metal seed layer using plasma on an inner surface of the hole; Forming a metal film as a lower electrode on the metal seed layer by using atomic layer deposition; Removing the sacrificial layer; And Forming a dielectric thin film / top electrode on the bottom electrode; Capacitor manufacturing method of a semiconductor device comprising a. The method of claim 1, Forming the metal seed layer A capacitor manufacturing method of a semiconductor device, characterized by progressing to a PEALD process. The method of claim 1, Forming the metal seed layer Spraying a source gas into a region where a metal seed layer is to be formed; Purging the source gas not reacting; Spraying a reaction gas; Purging the reaction gas that does not react; And And performing a plasma treatment on a region where the metal seed layer is to be formed. The method of claim 1, Forming the metal seed layer Spraying the source gas to a region where a metal seed layer is to be formed, purging the non-reacting source gas, and spraying the reaction gas in one cycle, and repeatedly performing the cycle a plurality of times. And the plasma treatment is performed every cycle. The method of claim 1, The metal film is At least one selected from Ru, Pt, Rh, Pd, Hf, Ti, W or Ta, or a nitride film synthesized with these or a conductive oxide film synthesized with these films. The method of claim 1, Forming the metal film as a lower electrode Simultaneously injecting a source gas and a reaction gas to perform a CVD reaction for a short time; Purging the unreacted source gas and reaction gas; And Capacitor manufacturing method of a semiconductor device comprising the step of flowing the reaction gas. The method of claim 1, Forming the metal film as a lower electrode A method of manufacturing a capacitor for a semiconductor device, characterized in that the ALD process proceeds by reducing the purge time to zero. The method of claim 1, Forming the metal film as a lower electrode Capacitor of the semiconductor device characterized by using a process that continues to flow the reaction gas and supply the source gas intermittently, when the source is supplied by the CVD method, and when the reaction gas only enters to obtain the densification effect of the film Manufacturing method. The method of claim 1, Forming the metal film as a lower electrode A method of manufacturing a capacitor of a semiconductor device, characterized by using a process of depositing by a CVD method when the source gas is continuously flowed, the reaction gas is intermittently supplied, and the reaction gas and the source gas are simultaneously supplied.

Images