KR100636508B1 - Charge pump circuit and direct current conversion apparatus for using the same - Google Patents

Abstract

The present invention relates to a charge pump circuit insensitive to a change in the threshold voltage of a transistor and a DC converter using the same.

According to an embodiment of the present invention, a charge pump circuit includes a source transistor for outputting an input voltage according to a first clock signal, a driver for driving the source transistor using the input voltage and the first clock signal, and the first clock signal; And a voltage pumping unit for gradually increasing a voltage output from the source transistor according to a second clock signal different from the first clock signal.

With this configuration, the present invention pumps and outputs the input voltage step by step according to the first and second clock signals without the influence of the threshold voltage of the source transistor. Accordingly, the present invention can provide a charge pump circuit insensitive to a threshold voltage of a transistor, and by applying such a charge pump circuit to a DC converter, a DC converter insensitive to a threshold voltage of a transistor is provided.

Description

CHARGGE PUMP CIRCUIT AND DIRECT CURRENT CONVERSION APPARATUS FOR USING THE SAME}             

1 is a view showing a general charge pump circuit.

2 is a view showing a charge pump circuit according to an embodiment of the present invention.

3 is a waveform diagram illustrating a clock signal for driving the charge pump circuit shown in FIG. 2.

4 is a view showing a DC converter using a charge pump circuit according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 110: charge pump circuit 12, 112: voltage pumping unit

114: driver 120: voltage divider

130: comparison unit 140: clock signal generation unit

142: reference clock generator 144: clock buffer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit, and more particularly, to a charge pump circuit insensitive to a change in a threshold voltage of a transistor and a direct current converter using the same.

In general, the charge pump circuit (Charge Pump Circuit) outputs a voltage higher than the voltage supplied from the power source. For example, a back-bias voltage generator of a semiconductor device, such as a DRAM, and a cell of an EPROM, EEPROM, or Flash Memory device, may be used. It is used for a voltage generator that generates a voltage for writing / writing a program.

1 is a circuit diagram illustrating a general charge pump circuit 10.

Referring to FIG. 1, a general charge pump circuit 10 includes a source transistor MS and a voltage pumping unit 12.

The source transistor MS is connected to the input terminal Vin in the form of a diode and supplies the input voltage Vdd input to the input terminal Vin to the voltage pumping unit 12.

The voltage pumping unit 12 includes first to fourth transfer transistors M1 to M4 and first to fourth capacitors C1 to C4.

The first to fourth transfer transistors M1 to M4 are connected in series to the output terminal of the source transistor MS in a plurality of stages. Here, the source transistor MS and the first to fourth transfer transistors M1 to M4 are N-type metal oxide semiconductor field effect transistors (MOSFETs).

The first electrode of the first capacitor C1 is electrically connected to the first node N1 between the source transistor MS and the first transfer transistor M1, and the second electrode is connected to the first clock signal CLK1. Is electrically connected to the first clock signal line CL1 to which is supplied.

The first electrode of the second capacitor C2 is electrically connected to the second node N2, which is between the first transfer transistor M1 and the second transfer transistor M2, and the second electrode is connected to the second clock signal ( CLK2 is electrically connected to a second clock signal line CL2 supplied thereto.

The first electrode of the third capacitor C3 is electrically connected to the third node N3 which is between the second transfer transistor M2 and the third transfer transistor M3, and the second electrode is connected to the first clock signal ( CLK1 is electrically connected to the first clock signal line CL1 supplied thereto.

The first electrode of the fourth capacitor C4 is electrically connected to the fourth node N4, which is between the third transfer transistor M3 and the fourth transfer transistor M4, and the second electrode is connected to the second clock signal ( CLK2 is electrically connected to a second clock signal line CL2 supplied thereto.

Two-Phase having a phase difference of 180 ° between the first clock signal CLK1 supplied to the first clock signal line CL1 and the second clock signal CLK2 supplied to the second clock signal line CL2. Clock signal.

On the other hand, the gate electrodes of each of the first to fourth transfer transistors M1 to M4 connected in series are electrically connected to their source electrodes and connected in the form of a diode. In other words, the gate electrode of the first transfer transistor M1 is electrically connected to the first node N1, and the gate electrode of the second transfer transistor M2 is electrically connected to the second node N2. The gate electrode of the third transfer transistor M3 is electrically connected to the third node N3, and the gate electrode of the fourth transfer transistor M4 is electrically connected to the fourth node N4.

As such, the voltage pumping unit 12 uses the first to fourth transfer transistors M1 to M4 according to the first and second clock signals CLK1 and CLK2 to output an input voltage (output) from the source transistor MS. Vdd) is pumped in steps to output to the final output terminal (Vout).

Therefore, the input voltage Vdd supplied to the general charge pump circuit 10 is pumped to a higher voltage toward the final output terminal Vout as the pumping time by the first and second clock signals CLK1 and CLK2 increases. do.

Since the input voltage Vdd is charged to the first node N1 of the charge pump circuit 10 operated as described above through the source transistor MS connected to the input terminal Vin in the form of a diode, Equation 1 below. Is fixed at the same voltage as

In Equation 1, V _N1 is a voltage of the first node N1, Vdd is an input voltage, Vth is a threshold voltage of the source transistor MS, and V _CLK1 is a voltage of the first clock signal CLK1. .

As a result, since the general charge pump circuit 10 is sensitive to the threshold voltage Vth of the source transistor MS, the pumping efficiency is lowered.

Accordingly, it is an object of the present invention to provide a charge pump circuit insensitive to variation in threshold voltage of a transistor and a direct current converter using the same.

As a technical means for achieving the above object, the first aspect of the present invention is a source transistor for outputting an input voltage in accordance with a first clock signal, and the input voltage, the first clock signal and the first clock signal and other A charge pump circuit includes a driver for driving the source transistor using two clock signals and a voltage pumping unit for gradually increasing a voltage output from the source transistor according to the first and second clock signals.

Preferably, the driver is electrically connected between the gate and the source of the source transistor in accordance with the first clock signal, and the voltage obtained by adding the voltage of the input voltage and the second clock signal according to the second clock signal; Supply to the gate of the source transistor. The driving part is controlled by the first clock signal and is connected to a gate-source of the source transistor, a first electrode is electrically connected to a gate of the source transistor, and a second electrode is connected to the first clock. And a source capacitor to which a signal is supplied. The voltage pumping unit is electrically connected to a plurality of transfer transistors connected to the output terminal of the source transistor in multiple stages, and electrically connected to each node between the source transistor and the plurality of transfer transistors and according to the first and second clock signals. A plurality of capacitors for charging and discharging are provided.

According to a second aspect of the present invention, a source transistor outputs an input voltage according to its gate-source voltage, a plurality of transfer transistors connected in multiple stages to an output terminal of the source transistor, and a first clock signal. A switching transistor controlled and electrically connected between the gate-source of the source transistor, a plurality of capacitors electrically connected to respective nodes between the plurality of transfer transistors, and the first clock signal supplied with the plurality of capacitors A first clock signal line electrically connected to an even-numbered capacitor, a second clock signal line supplied with a second clock signal different from the first clock signal, and electrically connected to an odd-numbered capacitor among the plurality of capacitors, and the source; A source electrically connected between the gate of the transistor and the first clock signal line Providing a charge pump circuit having an L-seater.

The third aspect of the present invention is the charge pump circuit for increasing the input voltage step by step according to the first and second clock signal, a comparison unit for comparing the reference voltage and the output voltage of the charge pump circuit and outputs a comparison signal; Provided is a DC converter using a charge pump circuit having a clock signal generator for generating the first and second clock signals using the comparison signal from the comparison unit.

Preferably, the DC converter using the charge pump circuit further includes a voltage divider which divides the output voltage and supplies the comparator. The clock signal generator generates a reference clock using a feedback signal from its output terminal and the comparison signal, and generates the first and second clock signals based on the reference clock. And a clock buffer buffered and supplied to the charge pump circuit.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 2 to 4 which can be easily implemented by those skilled in the art.

2 is a circuit diagram illustrating a charge pump circuit 110 according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the charge pump circuit 110 according to an exemplary embodiment of the present invention includes a source transistor MS, a voltage pumping unit 112, and a driving unit 114.

The source electrode of the source transistor MS is electrically connected to the input terminal Vin, and the drain electrode is electrically connected to the voltage pumping unit 112. The gate electrode of the source transistor MS is electrically connected to the driver 114. The source transistor MS is driven by the driver 114 to supply the input voltage Vdd input to the input terminal Vin to the voltage pumping unit 112.

The driver 114 includes a switching transistor PS and a source capacitor Cs.

The source electrode of the switching transistor PS is electrically connected to the input terminal Vin, and the drain electrode is electrically connected to the gate electrode of the source transistor MS. The gate electrode of the switching transistor PS is electrically connected to the first clock signal line CL1. In this case, the switching transistor PS is a transistor of a type different from that of the source transistor MS. Hereinafter, the switching transistor PS is assumed to be a P type transistor. The switching transistor PS applies the input voltage Vdd supplied to the input terminal Vin to the gate electrode of the source transistor MS according to the first clock signal CLK1 supplied to the first clock signal line CL1. Supply.

The first electrode of the source capacitor Cs is electrically connected to the gate electrode of the source transistor MS, and the second electrode is electrically connected to the first clock signal line CL1. The source capacitor Cs charges or charges the input voltage Vdd supplied to the first electrode through the switching transistor PS according to the first clock signal CLK1 supplied to the first clock signal line CL1. The supplied voltage is supplied to the gate electrode of the source transistor MS.

The driver 114 drives the source transistor MS according to the first clock signal CLK1. Specifically, the driving unit 114 turns on the switching transistor PS according to the low state of the first clock signal CLK1 to charge the input voltage Vdd to the source capacitor Cs, and then to high. The switching transistor PS is turned off according to the first clock signal CLK1 in the high state. Accordingly, the driver 114 turns on the source transistor MS by using the voltage charged in the first clock signal CLK1 and the source capacitor Cs in the high state.

The voltage pumping unit 112 includes first to fourth transfer transistors M1 to M4 and first to fourth capacitors C1 to C4.

The first to fourth transfer transistors M1 to M4 are connected in series to the output terminal of the source transistor MS in a plurality of stages. The source transistor MS and the first to fourth transfer transistors M1 to M4 may be N-type or P-type metal oxide semiconductor field effect transistors (MOSFETs). Hereinafter, the source transistor MS and the first to fourth transfer transistors M1 to M4 are assumed to be N-type transistors.

The first electrode of the first capacitor C1 is electrically connected to the first node N1 between the source transistor MS and the first transfer transistor M1, and the second electrode is connected to the second clock signal CLK2. Is electrically connected to the second clock signal line CL2 to which is supplied.

The first electrode of the second capacitor C2 is electrically connected to the second node N2 which is between the first transfer transistor M1 and the second transfer transistor M2, and the second electrode is connected to the first clock signal line ( It is electrically connected to CL1).

The first electrode of the third capacitor C3 is electrically connected to the third node N3, which is between the second transfer transistor M2 and the third transfer transistor M3, and the second electrode is connected to the second clock signal line ( Is electrically connected to CL2).

The first electrode of the fourth capacitor C4 is electrically connected to the fourth node N4, which is between the third transfer transistor M3 and the fourth transfer transistor M4, and the second electrode is connected to the first clock signal line ( It is electrically connected to CL1).

The first clock signal CLK1 and the second clock signal CLK2 are two-phase clock signals having a phase difference of 180 °.

On the other hand, the gate electrodes of each of the first to fourth transfer transistors M1 to M4 connected in series are electrically connected to their source electrodes and connected in the form of a diode. In other words, the gate electrode of the first transfer transistor M1 is electrically connected to the first node N1, the gate electrode of the second transfer transistor M2 is electrically connected to the second node N2, The gate electrode of the third transfer transistor M3 is electrically connected to the third node N3, and the gate electrode of the fourth transfer transistor M4 is electrically connected to the fourth node N4.

As such, the voltage pumping unit 112 outputs an input voltage (output) from the source transistor MS according to the first and second clock signals CLK1 and CLK2 using the first to fourth transfer transistors M1 to M4. Vdd) is pumped in steps to output to the final output terminal (Vout). In other words, the voltage pumping unit 112 is configured to charge and discharge the first and fourth capacitors according to the first and second clock signals CLK1 and CLK2 using the first to fourth transfer transistors M1 to M4. C1 to C4) are pumped step by step to output to the final output terminal (Vout).

As such, since the charge pump circuit 110 according to the embodiment of the present invention drives the source transistor MS by using the driver 114, the first node is not affected by the threshold voltage Vth of the source transistor MS. It is charged to (N1). In addition, the charge pump circuit 110 according to the embodiment of the present invention uses the voltage pumping unit 112 to input the input voltage Vdd output from the source transistor MS to the first and second clock signals CLK1 and CLK2. Raise step by step and output to final output terminal (Vout).

As a result, the input voltage Vdd supplied to the charge pump circuit 110 according to the exemplary embodiment of the present invention is the first and second clock signals CLK1 and CLK2 without affecting the threshold voltage Vth of the source transistor MS. As the pumping time increases by), it is pumped to a higher voltage toward the final output terminal (Vout).

FIG. 3 is a waveform diagram illustrating first and second clock signals CLK1 and CLK2 for driving the charge pump circuit 110 shown in FIG. 2.

Referring to FIG. 3 and FIG. 2, driving of another charge pump circuit 100 according to an exemplary embodiment of the present invention is as follows.

The switching transistor PS is applied to the first clock signal CLK1 in the low state during the T1 period in which the first clock signal CLK1 in the low state and the second clock signal CLK2 in the high state are supplied. Is turned on. The input voltage Vdd is supplied to the gate electrode of the source transistor MS through the switching transistor PS during the T1 period. Accordingly, the input voltage Vdd is supplied to the gate electrode and the source electrode of the source transistor MS during the T1 period so that the source transistor MS is turned off. At this time, the source capacitor Cs charges the input voltage Vdd during the T1 period.

Meanwhile, the first and third capacitors C1 and C2 charge the second clock signal CLK2 in the high state during the T1 period, while the second and fourth capacitors C2 and C4 are the first clock in the low state. The voltage charged by the signal CLK1 is discharged.

Accordingly, the voltage pumping unit 112 may perform the first to fourth transfer transistors due to the charging and discharging of the first to fourth capacitors C1 to C4 according to the first and second clock signals CLK1 and CLK2. The voltage of the first node N1 is gradually pumped using the driving of the M1 to M4 to be output to the final output terminal Vout.

Subsequently, the switching transistor PS is turned off by the first clock signal CLK1 in the high state during the T2 period in which the first clock signal CLK1 in the high state and the second clock signal CLK2 in the low state are supplied. do. The first clock signal CLK1 in the high state is supplied to the source capacitor Cs during the T2 period, so that the source transistor MS is connected to the voltage of the first clock signal CLK1 in the high state and the voltage stored in the source capacitor Cs. It is turned on by the sum. Accordingly, during the period T2, the source transistor MS supplies the input voltage Vin to the first node N1 without being affected by its threshold voltage Vth.

Meanwhile, during the period T2, the first and third capacitors C1 and C2 discharge the voltage charged by the second clock signal CLK2 in a low state, while the second and fourth capacitors C2 and C4 are high. The first clock signal CLK1 in the state is charged.

Accordingly, the voltage pumping unit 112 may perform the first to fourth transfer transistors due to the charging and discharging of the first to fourth capacitors C1 to C4 according to the first and second clock signals CLK1 and CLK2. The voltage of the first node N1 is gradually pumped using the driving of the M1 to M4 to be output to the final output terminal Vout. As a result, the charge pump circuit 110 according to the exemplary embodiment of the present invention uses the driving unit 114 to input the input voltage Vdd without the influence of the threshold voltage Vth of the source transistor MS. The voltage is supplied to N1, and the voltage of the first node N1 is gradually pumped to the final output terminal Vout according to the first and second clock signals CLK1 and CLK2 using the voltage pumping unit 112. Will print.

As such, the charge pump circuit 110 according to the embodiment of the present invention performs the input voltage Vdd step by step according to the first and second clock signals CLK1 and CLK2 while repeatedly performing the above-described T1 and T2 periods. Pumped output.

4 is a block diagram illustrating a DC converter using a charge pump circuit according to an exemplary embodiment of the present invention.

4, a DC converter using a charge pump circuit according to an embodiment of the present invention may include a charge pump circuit 110, a voltage divider 120, a comparator 130, and a clock signal generator 140. Equipped.

The charge pump circuit 110 pumps and outputs the input voltage Vdd in accordance with the first and second clock signals CLK1 and CLK2 supplied from the clock signal generator 140. Since the charge pump circuit 110 has the same configuration and operation as the charge pump circuit 110 according to the exemplary embodiment of the present invention illustrated in FIG. 2, a detailed description thereof will be replaced with the description of FIG. 2. Shall be.

The voltage divider 120 divides the output voltage Vout output from the output terminal of the charge pump circuit 110 and supplies the divider voltage Vd to the comparator 130.

The comparator 130 receives the divided voltage Vd and the reference voltage Vr from the reference voltage source Vref. The comparison unit 130 compares the reference voltage Vr with the divided voltage Vd supplied from the voltage divider 120, and compares the comparison signal Vc corresponding to the comparison result with the clock signal generator 140. Supplies).

The clock signal generator 140 includes a reference clock generator 142 and a clock buffer 144.

The reference clock generator 142 generates the reference clock RS by using the feedback signal FB from its output terminal and the comparison signal Vc from the comparator 130. The clock buffer 144 generates the first and second clock signals CLK1 and CLK2 based on the reference clock RS supplied from the reference clock generator 142 and generates the generated first and second clock signals. CLK1 and CLK2 are buffered and supplied to the charge pump circuit 110. In this case, the first and second clock signals CLK1 and CLK2 are two-phase clock signals having a phase difference of 180 °.

As described above, the DC converter using the charge pump circuit according to the embodiment of the present invention generates an output voltage Vout of a desired voltage using the charge pump circuit 110, and outputs the output voltage of the charge pump circuit 110. The first and second clock signals CLK1 and CLK2 for driving the charge pump circuit 110 are generated using the distribution voltage Vd and the reference voltage Vr of Vout. Accordingly, the present invention provides a charge pump circuit insensitive to a change in the threshold voltage of a transistor and a direct current converter using the same.

The above detailed description and drawings are merely exemplary of the present invention, which are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Accordingly, those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. As a result, the technical protection scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

As described above, in the charge pump circuit according to the embodiment of the present invention, the threshold voltage of the source transistor is increased by greatly increasing the voltage supplied to the gate electrode of the source transistor which outputs the input voltage to the next stage by using the input voltage and the clock signal. The input voltage can be supplied to the next stage without the effect of. Accordingly, the charge pump circuit according to the embodiment of the present invention pumps and outputs the input voltage step by step according to the first and second clock signals without the influence of the threshold voltage of the source transistor.

Accordingly, the present invention can provide a charge pump circuit insensitive to a threshold voltage of a transistor, and by applying such a charge pump circuit to a DC converter, a DC converter insensitive to a threshold voltage of a transistor is provided.

Claims (16)

A source transistor for outputting an input voltage according to the first clock signal; A driver configured to drive the source transistor using the input voltage and the first clock signal; And a voltage pumping unit for gradually increasing a voltage output from the source transistor according to the first clock signal and a second clock signal different from the first clock signal. The method of claim 1, The driving unit, Charging the input voltage according to the first clock signal in a first state, And a charge pump circuit for supplying a gate voltage of the source transistor to the gate of the source transistor according to the first clock signal having a second state different from the first state. The method of claim 1, The driving unit, A switching transistor controlled by the first clock signal and connected between a gate and a source of the source transistor; And a source capacitor having a first electrode electrically connected to a gate of the source transistor, and a second capacitor supplied with the first clock signal. The method of claim 1, The voltage pumping unit, A plurality of transfer transistors connected in multiple stages to an output terminal of the source transistor, And a plurality of capacitors electrically connected to each node between the source transistor and the plurality of transfer transistors and charged and discharged according to the first and second clock signals. The method of claim 4, wherein The first pump signal is supplied to even-numbered capacitors of the plurality of capacitors, and the second clock signal is supplied to odd-numbered capacitors. The method of claim 4, wherein Each of the plurality of transfer transistors is connected in the form of a diode. The method of claim 1, And the first and second clock signals have a phase difference of 180 degrees. The method of claim 3, wherein And the source and switching transistors are transistors of different types. The method of claim 4, wherein And the source transistor and the plurality of transfer transistors are transistors of the same type. A source transistor for outputting an input voltage according to its gate-source voltage, A plurality of transfer transistors connected in multiple stages to an output terminal of the source transistor, A switching transistor controlled by a first clock signal and electrically connected between a gate and a source of the source transistor; A plurality of capacitors electrically connected to each node between the plurality of transfer transistors; A first clock signal line supplied with the first clock signal and electrically connected to an even numbered capacitor among the plurality of capacitors; A second clock signal line supplied with a second clock signal different from the first clock signal and electrically connected to an odd number of the plurality of capacitors; And a source capacitor electrically connected between the gate of the source transistor and the first clock signal line. The method of claim 10, Each of the plurality of transfer transistors is connected in the form of a diode, the charge pump circuit. The method of claim 10, And the first and second clock signals have a phase difference of 180 degrees. The method of claim 10, And the switching transistor is a transistor of a different type from the source transistor. A charge pump circuit according to any one of claims 1 to 12, which gradually increases an input voltage according to the first and second clock signals; A comparator for comparing a reference voltage with an output voltage of the charge pump circuit and outputting a comparison signal; A DC converter using a charge pump circuit having a clock signal generator for generating the first and second clock signals using the comparison signal from the comparison unit. The method of claim 14, And a voltage divider configured to divide the output voltage and supply the voltage to the comparison unit. The method of claim 14, The clock signal generator, A reference clock generator for generating a reference clock by using a feedback signal from its output terminal and the comparison signal; And a charge buffer circuit for generating and buffering the first and second clock signals based on the reference clock and supplying the buffered signal to the charge pump circuit.

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