KR100634433B1 - Non-volatile semiconductor memory device and multi-block erase method thereof - Google Patents

Abstract

An erase method of a nonvolatile semiconductor memory device disclosed herein includes selecting memory blocks and simultaneously erasing the selected memory blocks, and erasing each of the erased memory blocks according to an erase verify command and a block address provided from an external device. Performing a verify operation. The nonvolatile semiconductor memory device is configured to stop an erase operation and perform another operation when a suspend command is input while the selected memory blocks are erased, and to erase a previously selected memory block when a resume command is input.

Description

Nonvolatile semiconductor memory device and multi-block erase method thereof Non-volatile semiconductor memory device and its multi-block erase method

1 is a block diagram schematically showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a block diagram schematically illustrating a row decoder circuit, a block decoder circuit, and a page buffer circuit related to the memory block shown in FIG. 1;

3 is a circuit diagram showing an exemplary embodiment of the block decoder shown in FIG. 2;

4 is a timing diagram of control signals applied to the block decoder shown in FIG. 3;

5 is a flowchart for explaining a multi-block erasing method of a nonvolatile semiconductor memory device according to the first embodiment of the present invention;

6 is a timing diagram for explaining a multi-block erase operation of a nonvolatile semiconductor memory device according to the first embodiment of the present invention;

7 is a block diagram schematically illustrating a nonvolatile semiconductor memory device according to a second embodiment of the present invention; And

8 is a timing diagram illustrating a suspend mode of a nonvolatile memory device according to the present invention.

Explanation of symbols on the main parts of the drawings

100 nonvolatile semiconductor memory device 110 memory cell array

120: address buffer circuit 130: pre-decoder circuit

140: block decoder circuit 150: row decoder circuit

160: erase control circuit 170: page buffer circuit

180: column decoder circuit 190: column gate circuit

200: input / output buffer circuit 210: pass / fail check circuit

220: high voltage generator circuit 230: flag generator circuit

240: counter

The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device supporting a multi-block erase operation.

Semiconductor memories are generally the most essential microelectronic devices of digital logic designs, such as computers and applications based on microprocessors, which range from satellite to consumer electronics technology. Therefore, advances in the manufacturing technology of semiconductor memories, including process improvement and technology development, achieved through scaling for high integration and high speed, help to establish performance criteria for other digital logic families.

The semiconductor memory device is largely divided into a volatile semiconductor memory device and a nonvolatile semiconductor memory device. In a volatile semiconductor memory device, logic information is stored by setting a logic state of a bistable flip-flop in the case of static random access memory or through charging of a capacitor in the case of dynamic random access memory. In the case of a volatile semiconductor memory device, data is stored and read while power is applied, and data is lost when power is cut off.

Nonvolatile semiconductor memory devices such as MROM, PROM, EPROM, and EEPROM can store data even when the power is cut off. The nonvolatile memory data storage state is either permanent or reprogrammable, depending on the manufacturing technique used. Nonvolatile semiconductor memory devices are used for the storage of programs and microcode in a wide range of applications such as the computer, avionics, telecommunications, and consumer electronics industries. The combination of volatile and nonvolatile memory storage modes on a single chip is also available for devices such as nonvolatile SRAM (nvRAM) in systems that require fast and reprogrammable nonvolatile memory. In addition, specific memory structures have been developed that include some additional logic circuitry to optimize performance for application-oriented tasks.

In the nonvolatile semiconductor memory device, the MROM, PROM and EPROM are not free to erase and write in the system itself, so that it is not easy for ordinary users to update the storage contents. On the other hand, since EEPROMs can be electrically erased and written, applications to system programming or auxiliary storage devices requiring continuous updating are expanding. In particular, the flash EEPROM (hereinafter referred to as a flash memory device) has a high degree of integration compared to a conventional EEPROM, which is very advantageous for application to a large capacity auxiliary storage device. Among flash memory devices, NAND-type flash memory devices have a higher degree of integration than NOR flash memory devices.

As is well known, a flash memory device includes a memory cell array composed of a plurality of memory blocks, and read / erase / program operations of each memory block are performed independently. In particular, the time taken to erase the memory blocks is a factor that limits not only the performance of the flash memory device but also the performance of the system including the flash memory device. In order to solve this disadvantage, a technique of simultaneously erasing a plurality of memory blocks has been proposed. The technique of erasing memory blocks simultaneously is described in U.S. Patent No. 5,841,721 entitled "MULTI-BLOCK ERASE AND VERIFICATION CIRCUIT IN A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND A METHOD THEREOF" and U.S. Patent No. 5,999,446, entitled "MULTI-STATE FLASH EEPROM SYSTEM WITH SELECTIVE MULTI-SECTOR ERASE," respectively.

An erase verify operation to check whether the erased memory blocks are normally erased should be performed after simultaneously erasing the memory blocks. Such an erase verify operation should be performed for each of the erased memory blocks. According to the above-mentioned documents, address information of memory blocks to be erased is stored therein, and an erase verify operation is performed with reference to the stored address information. This means that separate control logic and associated control signal lines for controlling the multi-block erase verify operation are needed. Therefore, the erase verification operation of each of the erased memory blocks also acts as a limiting factor for the performance and area of the flash memory device.

Therefore, there is a need for an improved erase verification method capable of improving the performance of a flash memory device.

An object of the present invention is to provide a nonvolatile semiconductor memory device and an erase method thereof that can improve an erase verify operation in a multi-block erase method.

Another object of the present invention is to provide a nonvolatile semiconductor memory device capable of varying erase time in a multi-block erase method and an erase method thereof.

It is still another object of the present invention to provide a nonvolatile semiconductor memory device capable of pausing a multi-block erase operation and performing a read / write operation.

According to one aspect of the present invention for achieving the above object, there is provided a method for erasing a nonvolatile memory device. According to the erase method, first, memory blocks are selected and the selected memory blocks are simultaneously erased. An erase verify operation of each of the erased memory blocks is performed according to an erase verify command and a block address provided from the outside. In order to simultaneously erase the selected memory blocks, first, a block address is input in response to a multi-block selection command, the input block address is stored in a block decoder of a memory block to be erased, and all memory blocks to be erased are selected. The input and store steps are repeated until Finally, memory blocks of the block addresses input in response to the multi-block erase command are simultaneously erased.

In an exemplary embodiment, the time required to erase the memory blocks to be erased varies with the number of memory blocks to be erased.

In an exemplary embodiment, the block decoder of the memory block to be erased includes a register for storing a corresponding block address.

In an exemplary embodiment, the registers of the block decoders corresponding to the memory blocks to be erased are initialized when the first multi-block select command is input.

In an exemplary embodiment, the result of the erase verify operation is stored in a status register, and the information stored in the status register is output externally before the next erase verify command is input.

According to another aspect of the present invention, a method of erasing a nonvolatile memory device includes: accepting a block address in response to a multi-block select command; Storing the input block address in a block decoder of a memory block to be erased; Repeating the input and store steps until all the memory blocks to be erased are selected; Simultaneously erasing memory blocks of the block addresses input in response to the multi-block erase command; Selecting an erased memory block corresponding to a block address from an outside of the erased memory blocks in response to an erase verify command; Verifying whether the selected memory block has been erased normally; And repeating the selecting and verifying steps until all the simultaneously erased memory blocks are selected.

According to another feature of the invention, the nonvolatile memory device comprises a plurality of memory blocks; And an erase controller configured to control a multi-block erase operation in which at least two memory blocks are simultaneously erased, wherein after the multi-block erase operation, the erase controller is responsive to an erase verify command and a block address provided from the outside. An erase verify operation of each of the erased memory blocks is controlled.

In an exemplary embodiment, the erase controller includes a status register that stores a result of the erase verify operation, and the erase verify result stored in the status register is output externally before a next erase verify command is input.

In an exemplary embodiment, a plurality of block decoders respectively corresponding to the memory blocks are further provided, and the erase controller is configured to block decoders of the memory blocks to which block addresses are to be erased in the multi-block erase operation. Control the block decoders to be stored. Each of the block decoders includes a register that stores a corresponding block address, and the erase controller initializes registers in the block decoders when a first multi-block select command is input.

According to another feature of the invention, the nonvolatile memory device comprises a plurality of memory blocks; Discrimination circuitry for determining the number of memory blocks to be erased; And an erase controller configured to control a multi-block erase operation in which at least two memory blocks are erased simultaneously, wherein the erase controller varies the time required for the multi-block erase operation according to a determination result of the determination circuit; After the multi-block erase operation, the erase controller controls an erase verify operation of each of the erased memory blocks in response to an erase verify command and a block address provided from the outside.

In an exemplary embodiment, the determination circuit comprises: a flag signal generator for generating a flag signal in pulse form whenever a block address for selecting a memory block to be erased is input; And a counter for counting the number of pulses of the flag signal and outputting a counted value to the erase controller, wherein the erase controller controls the time required for the multi-block erase operation in response to the counted value.

Exemplary embodiments of the invention will be described in detail below on the basis of reference drawings. The nonvolatile semiconductor memory device according to the present invention supports a novel erase verification method performed after simultaneously erasing a plurality of memory blocks. According to the novel erase verify method of the present invention, after simultaneously erasing the memory blocks, an erase verify operation of each of the erased memory blocks is performed according to an erase verify command and a block address supplied from the outside. For example, to select N erased memory blocks, a block address and an erase verify command are input externally N times. An erase verify operation is performed according to a block address and an erase verify command input each time, which will be described in detail below. In addition, in the case of the nonvolatile semiconductor memory device according to the present invention, the time taken to simultaneously erase the memory blocks is automatically changed according to the number of memory blocks to be erased, which will be described in detail below.

1 is a block diagram schematically illustrating a nonvolatile semiconductor memory device according to a first embodiment of the present invention. The nonvolatile semiconductor memory device according to the first embodiment of the present invention is a NAND type flash memory device. However, it will be apparent to those skilled in the art that the present invention can be applied to other memory devices (eg, MROM, PROM, FRAM, NOR type flash memory devices, etc.).

Referring to FIG. 1, the nonvolatile semiconductor memory device 100 includes a memory cell array 110 for storing data information, and the memory cell array 110 includes a plurality of memory blocks BLK0 to BLKn. . The nonvolatile semiconductor memory device 100 of the present invention includes an address buffer circuit 120, a pre-decoder circuit 130, a block decoder circuit 140, a row decoder circuit 150, an erase control circuit 160, and a page buffer. The circuit 170 further includes a column decoder circuit 180, a column gate circuit 190, an input / output buffer circuit 200, a pass / fail check circuit 210, and a high voltage generator circuit 220.

The address buffer circuit 120 is controlled by the erase control circuit 160 and receives a column / row address input through input / output pins I / Oi. The pre-decoder circuit 130 decodes the row address output from the address buffer circuit 120 and outputs the decoded address signals to the block decoder circuit 140 and the row decoder circuit 150. The decoded address signals include block address information for selecting a memory block and page address information for selecting pages (or word lines) of the selected memory block. The block decoder circuit 140 is controlled by the erase control circuit 160 and selects memory blocks in response to the block address information output from the pre-decoder circuit 130. In particular, the block decoder circuit 140 is configured to store block address information of memory blocks to be erased under the control of the erase control circuit 160 in a multi-block erase mode, which will be described in detail later. The row decoder circuit 150 drives the pages of the memory block selected according to the operation mode with word line voltages from the high voltage generation circuit 220.

The page buffer circuit 170 includes a plurality of page buffers each connected to bit lines (shared by all memory blocks) and operate as a sense amplifier and as a write driver depending on the mode of operation. For example, the page buffer circuit 170 senses page data from a selected memory block through bit lines during a read operation. In the program operation, the page buffer circuit 170 latches data to be programmed and drives bit lines to a ground voltage or a power supply voltage according to the latched data, respectively. The column decoder circuit 180 decodes the column address output from the address buffer circuit 120, and the column gate circuit 190 responds to the decoded address signals output from the column decoder circuit 180 in response to the page buffer circuit ( The page buffers of 170) are selected in bit structure units. In a read operation, data read by the page buffer circuit 170 is output to the outside through the column gate circuit 190 and the input / output buffer circuit 200. In a program operation, data to be programmed is transferred to the page buffer circuit 170 through the column gate circuit 190 and the input / output buffer circuit 200.

Although not shown in the figure, the column decoder circuit 180 includes an address counter, which increments the initial column address sequentially to generate column addresses sequentially. This means that the page data to be programmed / read is sequentially transmitted through the column gate circuit 190 in bit structure units.

Subsequently, the pass / fail check circuit 210 receives the page data bits read by the page buffer circuit 170 in the erase verify operation, and determines whether the input page data bits have the same value (that is, the pass data value). Determine whether or not. The determination result of the pass / fail check circuit 210 is transferred to the erase control circuit 160. The high voltage generator circuit 220 is controlled by the erase control circuit 160 to generate word line voltages and bulk voltages required for the multi-block erase operation and the erase verify operation. The word line voltages are transferred through the row decoder circuit 150 to the pages (ie word lines) of the selected memory block (s), and the bulk voltage is supplied to the bulk of the selected memory block (s).

The erase control circuit 160 according to the present invention is configured to control a multi-block erase mode divided into a multi-block erase interval and an erase verify interval. The erase control circuit 160 determines an address, command, or data input timing in response to control signals (eg, CLE, ALE, / CE, / RE, / WE). The erase control circuit 160 multi-stores the block addresses of the memory blocks to be erased in the multi-block erase period, and are sequentially stored in the block decoder circuit 140 through the address buffer circuit 120 and the pre-decoder circuit 130. The block decoder circuit 140 is controlled in response to the block select command. The erase control circuit 160 controls the multi-block erase operation in response to the multi-block erase command so that the memory blocks of the input block addresses are simultaneously erased. In a multi-block erase operation, the pages of the selected memory block are set to ground voltage and its bulk is set to high voltage (eg, 20V). For example, in a multi-block erase operation, the erase control circuit 160 allows memory blocks to be selected in accordance with stored block addresses and pages of each of the selected memory blocks to ground voltage and their bulk to a high voltage (e.g., For example, the block selection circuit 140 and the high voltage generation circuit 220 are controlled to be set to 20V, respectively. After the multi-block erase operation is performed, the erase control circuit 160 controls the erase verify operation on the erased memory blocks in response to an erase verify command and a block address applied from the outside. That is, an erase verify operation of each of the erased memory blocks may be performed by an erase verify command and a block address applied from the outside. This will be explained in detail later.

As described above, the erase verify operation of the nonvolatile semiconductor memory device 100 according to the present invention is performed by an erase verify command and a block address provided externally. In other words, to select N erased memory blocks, a block address and an erase verify command are input externally N times.

FIG. 2 is a block diagram schematically illustrating a row decoder circuit, a block decoder circuit, and a page buffer circuit related to the memory block shown in FIG. 1.

Referring to FIG. 2, the memory block BLK0 includes a plurality of strings 111, and each string 111 includes a string select transistor SST, a ground select transistor GST, and select transistors SST, And a plurality of memory cells (or memory cell transistors) MC0 to MCm connected in series between the GSTs. The strings 111 are electrically connected to the corresponding bit lines BL0 to BLk, respectively. The bit lines BLO to BLK are arranged to be shared by the memory blocks BLK0 to BLKn of the memory cell array 110. In each string 111, the string select transistor SST is connected to the string select line SSL, the ground select transistor GST is connected to the ground select line GSL, and the memory cell transistors MCm to MC0 is connected to the corresponding word lines WLm to WL0, respectively.

The string select line SSL, the word lines WLm to WL0, and the ground select line GSL are connected to the corresponding select lines S0 to Si through the select transistors ST0 to STi, respectively. In the multi-block erase period, for example, the select lines SO and Si are kept floating and the select lines S1 to Si-1 are set to the ground voltage. The select transistors ST0 to STi constitute a row decoder circuit 150, and the row decoder circuit 150 corresponds to voltages corresponding to the select lines in response to the page address information from the pre-decoder circuit 130. And a decoder circuit 151 for delivering from the high voltage generating circuit of FIG.

Gates of the select transistors ST0 to STi are commonly connected to the block select line BSC, and the block select line BSC is controlled by the block decoder 141. The block decoder 141 is controlled by the erase control circuit 160 to activate or deactivate the block select line BSC in response to the block address information. The page buffer circuit 170 includes page buffers PB respectively connected to the bit lines BL0 to BLk, and each page buffer PB shows data values nWD0 to nWDk read during an erase verify operation. To the pass / fail check circuit 210. The data values nWD0 to nWDk are used to determine whether the erase operation of the memory block has been normally performed. Exemplary page buffers and pass / fail check circuits are described in U.S. Patent No. 5,299,162, entitled "NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND AN OPTIMIZING PROGRAMMING METHOD THEREOF," incorporated by reference herein.

3 is a circuit diagram illustrating an exemplary embodiment of the block decoder illustrated in FIG. 2, and FIG. 4 is a timing diagram of control signals applied to the block decoder illustrated in FIG. 3.

Referring first to FIG. 3, the block decoder 141 corresponds to one memory block, and block decoders corresponding to the remaining memory blocks, respectively, will also be implemented as shown in FIG. 3. The block decoder 141 includes a latch (or register) LAT composed of a NAND gate G1, PMOS transistors MP1 and MP2, an NMOS transistor MN1, inverters INV1 and INV2, and transfer gates ( TG1, TG2), and the level shifter LS. Decoded block address signals Pm, Qm, and Rm output from the pre-decoder circuit 130 of FIG. 1 are applied to the NAND gate G1. PMOS transistors MP1 and MP2 are connected in series between the power supply voltage and the input node ND1 of the latch LAT. The gate of the PMOS transistor MP1 is connected to the output terminal of the NAND gate G1, and the gate of the PMOS transistor MP2 is connected to receive the control signal nBLK_IN. The NMOS transistor MN1 is connected between the input node ND1 of the latch LAT and the ground voltage, and is controlled by the control signal BLK_RST. The transfer gate TG1 is controlled by the control signal MLT_EN and transfers the output of the latch to the level shifter LS. The transfer gate TG2 is controlled by the control signal NOR_EN and transfers the output of the NAND gate G1 to the level shifter LS. The level shifter LS activates the block select line BSC in response to the input signal. The voltage level of the activated block select line BSC will be set differently depending on the operation mode. For example, the voltage level of the block select line BSC may be set such that the voltages of the select lines S0 to Si are transferred to the corresponding lines through the select transistors ST0 to STi of FIG. 2 without a voltage drop. will be. The voltage supplied to the block select line BSC through the level shifter LS is provided by the high voltage generation circuit 220 of FIG. 1.

In this embodiment, the control signals nBLK_IN, BLK_RST, NOR_EN, MLT_EN are generated by the erase control circuit 160.

In circuit operation, when the multi-block selection command is input for the first time, the erase control circuit 160 activates the control signal BLK_RST. According to the activation of the control signal BLK_RST, the NMOS transistor MN1 is turned on, and as a result, the latch LAT is initialized. At this time, the control signals MLT_EN and NOR_EN are maintained at a low level. This means that the transfer gates TG1, TG2 are deactivated. Then, a block address for selecting an erased memory block is input. The input block address is decoded by the pre-decoder circuit 130, and the decoded block address signals Pm, Qm, and Rm are input to the NAND gate G1. When the block address is input, the erase control circuit 160 activates the control signal nBLK_IN. If the decoded block address signals Pm, Qm, and Rm are all '1', the output of the NAND gate G1 becomes low so that the PMOS transistor MP1 is turned on. Therefore, when the control signal nBLK_IN is activated, the input node ND1 of the latch LAT transitions from a low level to a high level. At this time, since the transfer gates TG1 and TG2 are inactivated, the block select line BSC is not driven by the level shifter LS.

According to the foregoing description, when a block address is input after the multi-block selection command, the input block address is stored in the latch LAT of the corresponding block decoder 141 under the control of the erase control circuit 160. This operation is performed repeatedly until the block addresses of the memory blocks to be erased are all stored in the corresponding block decoders.

If the block addresses of the memory blocks to be erased are all stored in the corresponding block decoders, the erase control circuit 160 activates the control signal MLT_EN in response to the multi-block erase command. As the control signal MLT_EN is activated, the value stored in the latch LAT is transferred to the level shifter LS through the transfer gate TG1. The level shifter LS activates the block select line BSC in response to the input signal, at which time only the block select lines BSC of the selected memory blocks will be activated. Cleared, the R / nB signal goes low during the erase time.

In FIG. 3, the control signal NOR_EN is activated and the control signal MLT_EN is deactivated in the erase verification period to be described later. Accordingly, in the erase verify period, the block select line BSC may be activated according to the input block address without storing the block address.

5 is a flowchart illustrating a multi-block erasing method of a nonvolatile semiconductor memory device according to a first embodiment of the present invention, and FIG. 6 is a multi-block of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. A timing diagram for explaining a block erase operation. Hereinafter, the multi-block erasing method of the nonvolatile semiconductor memory device according to the first embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, when the multi-block selection command CMD1 is input for the first time (S401), the erase control circuit 160 activates the control signal BLK_RST so that the latches of the block decoders 141 are initialized. At this time, the control signals MLT_EN and NOR_EN are kept low so that the block select line BSC is not driven by the block address to be input. When a block address BA1 for selecting a memory block to be erased is input (S402), the pre-decoder circuit 130 decodes the input block address BA1 and decodes the block address signals Pm, Qm, Rm) is applied to the NAND gate G1 of the block decoder 141. When the decoded block address signals Pm, Qm, and Rm are all high, the output of the NAND gate G1 goes low, and as a result, the PMOS transistor MP1 of the block decoder 141 is turned on. At the same time, the erase control circuit 160 activates the control signal nBLK_IN, and the input node ND1 of the latch LAT goes high through the PMOS transistors MP1 and MP2. This means that the memory block of the currently input block address is selected.

Steps S401 and S402 described above will be repeatedly performed until all block addresses of memory blocks to be erased are input (S403). If the block addresses of the memory blocks to be erased are all input, the multi-block erase command CMD2 is input (S404). The erase control circuit 160 activates the control signal MLT_EN in response to the multi-block erase command CMD2. As the control signal MLT_EN is activated, the values stored in the latches LAT of the block decoders 141 are transferred to the corresponding level shifters LS through the corresponding transfer gates TG1. Each of the level shifters LS activates a corresponding block select line BSC when the input signal has a low level. Thus, only the block select lines BSC of the memory blocks to be erased are activated. The erase control circuit 160 then sets the row decoder circuit 150 and the high voltage generator circuit 220 such that the word lines (or pages) of each of the selected memory blocks are set to ground voltage and their bulks are set to high voltage. To control. The multi-block erase operation will be performed for a predetermined time (S405). At this time, the erase control circuit 160 activates the R / nB signal low while the multi-block erase operation is performed.

When the multi-block erase operation ends, the erase control circuit 160 deactivates the R / nB signal high. After the R / nB signal is deactivated, the erase verify command CMD3 is provided to the nonvolatile semiconductor memory device 100 (S406). As the erase verify command CMD3 is input, the erase control circuit 160 activates the control signal NOR_EN high. This causes the output of the NAND gate G1 in the block decoder 141 to be delivered directly to the level shifter LS via the transfer gate TG2. Then, when a block address BA1 for selecting one of the memory blocks to be erased is input, the pre-decoder circuit 130 decodes the input block address BA1 and inputs the block address RA1. The block select line BSC of the erased memory block corresponding to is activated by the level shifter LS according to the decoded result. Thereafter, the erase control circuit 160 controls the row decoder circuit 150 and the high voltage generation circuit 220 so that the word lines of the selected memory block are set to the ground voltage.

As the word lines of the selected memory block are set to the ground voltage, the bit lines have a ground voltage or a power supply voltage depending on whether the memory cells of the corresponding string have been normally erased. For example, the bit line has a ground voltage when all string memory cells are erased. In contrast, when at least one of the memory cells of any string is not normally erased, the bit line has a voltage precharged by the corresponding page buffer. Page buffers PB of page buffer circuit 170 latch the voltage levels of corresponding bit lines. The latched values nWD0 to nWDk are passed to the pass / fail check circuit 210. The pass / fail check circuit 210 determines whether or not the values nWD0 to nWDk output from the page buffer circuit 170 have the same value (eg, a pass data value). The result determined by the pass / fail check circuit 210 is stored in the status register 161 of the erase control circuit 160. The result stored in the status register 161 is output to the outside through the status read operation (S408), and it is determined whether the erase operation of the selected memory block is normally performed according to the read result (S409). When the read result indicates that the erase operation of the selected memory block is not normally performed, the currently selected memory block is processed as a bad block (S410). Steps S406 to S410 described above are repeated until an erase verify operation of each of the erased memory blocks is performed (S411).

As can be seen from the above description, according to the nonvolatile semiconductor memory device of the present invention, after simultaneously erasing the memory blocks, an erase verify operation of each of the erased memory blocks is performed according to an externally supplied block address and an erase verify command. Is performed. For example, to select N erased memory blocks, a block address and an erase verify command are input externally N times. An erase verify operation will be performed according to a block address and an erase verify command input each time.

7 is a block diagram schematically illustrating a nonvolatile semiconductor memory device according to a second embodiment of the present invention. In FIG. 7, components that perform the same function as the components shown in FIG. 6 are denoted by the same reference numerals, and description thereof is therefore omitted. The memory device shown in FIG. 7 is substantially the same as that shown in FIG. 1 except that a flag generation circuit 230 and a counter 240 are added.

The flag generating circuit 230 and the counter 240 constitute a discriminating circuit for determining the number of memory blocks to be erased, and the erasing control circuit 160 varies the time required for the multi-block erasing operation according to the determined result. . The flag generation circuit 230 generates a pulse signal flag signal FADD_IN informing of input of a block address in response to control signals (eg, CLE, ALE, / CE, / RE, / WE). For example, when the ALE and / RE signals are held high and the CLE and / CE signals are held low, the flag signal generation circuit 230 is synchronized with the high-low transition of the / WE signal to form a flag signal in the form of a pulse. Generates (FADD_IN). The counter 240 counts the number of pulses of the flag signal FADD_IN and outputs the counted value to the erasure control circuit 160. The counter 240 is initialized by the erase control circuit 160 when the multi-block select command is first input. The erase control circuit 160 controls the time required for the multi-block erase operation according to the counted value. For example, the erasing control circuit 160 controls the high voltage generating circuit 220 according to the discriminating result of the discriminating circuits 230 and 240, and as a result, the application time of the voltages required for the erasing operation may be adjusted.

The time taken for the erase operation differs depending on the number of memory blocks to be erased. In other words, as the number of memory blocks to be erased increases, the time taken for the erase operation becomes longer. Compared to the case where the erase time is set to be constant regardless of the number of memory blocks to be erased, therefore, the time required for the multi-block erase operation is optimized by variably controlling the erase time according to the number of memory blocks to be erased. can do.

The nonvolatile memory device according to the present invention supports a suspend mode. In suspend mode, the multi-block erase operation is temporarily stopped and another operation (eg, a read operation) is performed. More specifically, as shown in FIG. 8, during the multi-block erase operation, a suspend command is provided to the nonvolatile memory device 100. When a suspend command (e.g., B0h) is input to the nonvolatile memory device 100, the erase control circuit 160 of FIG. 1 stops the multi-block erase operation and the recovery operation (voltages used for the erase operation) occurs. Initialized). After the recovery operation is performed for a predetermined time (eg, about 300 ms), another operation (eg, a read operation) will be performed under the control of the erase control circuit 160. Although the multi-block erase operation is stopped, the block selection information stored in the block decoder circuit 150 is maintained. To this end, the erase control circuit 160 turns off the transfer gate TG1 of the block decoder 141 and turns on the transfer gate TG2 when another operation is performed. That is, when the multi-block erase operation is stopped, the block selection information of the memory block to be selected in the read operation is transferred to the level shifter LS through the NAND gate G1 and the transfer gate TG2. Thereafter, the read operation is performed in a manner well known in the art, and a description thereof is therefore omitted.

Once another operation ends, a reset command (eg, 30h) is provided to the nonvolatile memory device 100, and the erase control circuit 160 resumes the multi-block erase operation in response to the reset command. The resumed multi-block erase operation is performed by previously stored block selection information, which is achieved by turning on the transfer gate TG1 of each block decoder 141. The multi-block erase operation is resumed under the control of the erase control circuit 160. Even if a read command for performing a read operation is input, the erase control circuit 160 controls the block decoder circuit 140 so that the information stored in the latch LAT of each block decoder 141 is not initialized.

Although the configuration and operation of the circuit according to the present invention have been shown in accordance with the above description and drawings, this is merely an example and various changes and modifications are possible without departing from the spirit and scope of the present invention. .

As described above, an erase verification operation performed after simultaneously erasing the memory blocks is performed according to an externally supplied block address. In addition, it is possible to optimize the time required for the multi-block erase operation by determining the number of memory blocks to be erased and controlling the erase time according to the determined result.

Claims (42)

A method of erasing a nonvolatile memory device, comprising: Selecting memory blocks and erasing the selected memory blocks simultaneously; And And performing an erase verify operation of each of the erased memory blocks according to an erase verify command and a block address provided from an external device. The method of claim 1, Simultaneously erasing the selected memory blocks Accepting a block address in response to a multi-block selection command; Storing the input block address in a block decoder of a memory block to be erased; Repeating the input and store steps until all the memory blocks to be erased are selected; And Simultaneously erasing memory blocks of block addresses input in response to a multi-block erase command. The method of claim 2, And the time required to erase the memory blocks to be erased is varied according to the number of memory blocks to be erased. The method of claim 2, And the block decoder of the memory block to be erased comprises a register for storing a corresponding block address. The method of claim 4, wherein And registers of block decoders corresponding to the memory blocks to be erased are initialized when a first multi-block select command is input. The method of claim 1, The result of the erase verify operation is stored in a status register. The method of claim 6, And the information stored in the status register is externally output before the next erase verify command is input. A method of erasing a nonvolatile memory device, comprising: Simultaneously erasing the memory blocks; Selecting an erased memory block corresponding to a block address from an outside of the erased memory blocks in response to an erase verify command; Verifying whether the selected memory block has been erased normally; And Repeating the selecting and verifying steps until all the simultaneously erased memory blocks are selected. The method of claim 8, Simultaneously erasing the selected memory blocks Accepting a block address in response to a multi-block selection command; Storing the input block address in a block decoder of a memory block to be erased; Repeating the input and store steps until all the memory blocks to be erased are selected; And Simultaneously erasing memory blocks of block addresses input in response to a multi-block erase command. The method of claim 9, And the block decoder of the memory block to be erased comprises a register for storing a corresponding block address. The method of claim 10, And registers of block decoders corresponding to the memory blocks to be erased are initialized when a first multi-block select command is input. The method of claim 8, And information indicating whether the selected memory block is normally erased is stored in a status register. The method of claim 12, And the information stored in the status register is externally output before the next erase verify command is input. The method of claim 9, And the time required to erase the memory blocks to be erased is varied according to the number of memory blocks to be erased. A method of erasing a nonvolatile memory device, comprising: Accepting a block address in response to a multi-block selection command; Storing the input block address in a block decoder of a memory block to be erased; Repeating the input and store steps until all the memory blocks to be erased are selected; Simultaneously erasing memory blocks of the block addresses input in response to the multi-block erase command; Selecting an erased memory block corresponding to a block address from an outside of the erased memory blocks in response to an erase verify command; Verifying whether the selected memory block has been erased normally; And Repeating the selecting and verifying steps until all the simultaneously erased memory blocks are selected. The method of claim 15, And the block decoder of the memory block to be erased comprises a register for storing a corresponding block address. The method of claim 16, And registers of block decoders corresponding to the memory blocks to be erased are initialized when a first multi-block select command is input. The method of claim 17, And information indicating whether the selected memory block is normally erased is stored in a status register. The method of claim 18, And the information stored in the status register is externally output before the next erase verify command is input. The method of claim 15, And the time required to erase the memory blocks to be erased is varied according to the number of memory blocks to be erased. A plurality of memory blocks; And An erase controller configured to control a multi-block erase operation in which at least two memory blocks are erased simultaneously; And after the multi-block erase operation, the erase controller controls an erase verify operation of each of the erased memory blocks in response to an erase verify command and a block address provided from the outside. The method of claim 21, And the erase controller includes a status register to store a result of the erase verify operation. The method of claim 22, The erase verification result stored in the status register is externally output before the next erase verify command is input. The method of claim 21, And a plurality of block decoders respectively corresponding to the memory blocks. The method of claim 24, And the erasing controller controls the block decoders so that, in the multi-block erase operation, block addresses are respectively stored in block decoders of memory blocks to be erased. The method of claim 25, Each of the block decoders comprises a register for storing a corresponding block address. The method of claim 26, And the erase controller initializes registers in the block decoders when a first multi-block select command is input. The method of claim 27, And the erase controller controls the block decoders such that memory blocks to be erased are selected without storing block addresses during the erase verify operation. A plurality of memory blocks; Discrimination circuitry for determining the number of memory blocks to be erased; And An erase controller configured to control a multi-block erase operation in which at least two memory blocks are erased simultaneously; The erasing controller varies the time required for the multi-block erasing operation according to the discrimination result of the discriminating circuit; And after the multi-block erase operation, the erase controller controls an erase verify operation of each of the erased memory blocks in response to an erase verify command and a block address provided from the outside. The method of claim 29, The determination circuit A flag signal generator for generating a flag signal in pulse form whenever a block address for selecting a memory block to be erased is input; And And a counter for counting the number of pulses of the flag signal and outputting a counted value to the erase controller, wherein the erase controller controls a time required for the multi-block erase operation in response to the counted value. Device. The method of claim 29, And the erase controller includes a status register to store a result of the erase verify operation. The method of claim 31, wherein The data stored in the status register is output to the outside before the next erase verify command is input. The method of claim 29, And a plurality of block decoders respectively corresponding to the memory blocks. The method of claim 33, wherein And the erasing controller controls the block decoders so that, in the multi-block erase operation, block addresses are respectively stored in block decoders of memory blocks to be erased. The method of claim 34, wherein Each of the block decoders comprises a register for storing a corresponding block address. 36. The method of claim 35 wherein And the erase controller initializes registers in the block decoders when a first multi-block select command is input. The method of claim 29, And the erase controller controls the block decoders such that memory blocks to be erased are selected without storing block addresses during the erase verify operation. In a decoder circuit of a nonvolatile memory device comprising a plurality of memory blocks: A decoding unit for decoding address signals for selecting a memory block; A latch unit configured to latch the decoded address signal; And And a switch configured to output one of the outputs of the decoding unit and the latch unit as a block selection signal according to an operation mode. The method of claim 38, And the latch portion is configured to latch the decoded address signal during a multi-block erase operation. The method of claim 38, And the switch selects an output of the latch unit in a multi-block erase operation and an output of the decoding unit in another operation. The method of claim 38, And when a suspend command is input during the multi-block erase operation, the switch is configured to block the output of the latch section and select the output of the decoding section. 42. The method of claim 41 wherein And when a resume command for resuming the multi-block erase operation is input, the switch is configured to select an output of the latch section and to block an output of the decoding section.

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