JP4578133B2 - Flash memory device capable of preventing program disturb due to partial program - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a flash memory device.

  There is an increasing demand for semiconductor memory devices that do not require refresh of data stored in the semiconductor memory devices and that can be electrically erased and programmed. In addition, the current trend is to increase the storage capacity and integration of memory devices. An example of a non-volatile semiconductor memory device that provides a large capacity and a high degree of integration without needing to refresh stored data is a NAND flash memory device. Since the flash memory device maintains the data as it is even when the power is turned off, the flash memory device is widely used in electronic devices (for example, portable terminals, portable computers, etc.) whose power supply may be suddenly cut off.

  FIG. 1 is a block diagram showing a general NAND flash memory device. Referring to FIG. 1, a NAND flash memory device 10 includes a memory cell array 20, a row selection circuit (denoted as “X-SEL” in the drawing) 40, and sensing and latching. A circuit 60 includes a sense and latch circuit (also called a page buffer circuit) 60. The memory cell array 20 includes a plurality of cell strings (or NAND strings) 21 connected to the bit lines BL0 to BLm, respectively. The cell strings 21 in each column are connected in series between a string selection transistor SST as a first selection transistor, a ground selection transistor GST as a second selection transistor, and selection transistors SST and GST. The plurality of flash EEPROM cells MCn (n = 0 to 15). Each column string select transistor SST has a drain connected to a corresponding bit line and a gate connected to a string selection line SSL. The ground selection transistor GST has a source connected to a common source line CSL and a gate connected to a ground selection line GSL. Flash EEPROM cells MC15 to MC0 are connected in series between the source of the string selection transistor SST and the drain of the ground selection transistor GST. The cells of each cell string are composed of floating gate transistors, and the control gates of the transistors are connected to the corresponding word lines WL15 to WL0, respectively.

  The string selection line SSL, the word lines WL0 to WL15, and the ground selection line GSL are electrically connected to the row selection circuit 40. The row selection circuit 40 selects one of the word lines according to the row address information, and supplies a word line voltage according to each operation mode to the selected word line and the non-selected word line. For example, in the program operation mode, the row selection circuit 40 supplies a program voltage (for example, 15V to 20V) to a selected word line, and passes a pass voltage (for example, a non-selected word line). 10V). In the read operation mode, the row selection circuit 40 supplies the ground voltage GND to the selected word line and supplies the read voltage (for example, 4.5 V) to the unselected word line. The program voltage, pass voltage, and read voltage are higher than the power supply voltage. Bit lines BL0 to BLm arranged through the memory cell array 20 are electrically connected to the sensing and latch circuit 60. The sensing and latch circuit 60 senses data from the flash EEPROM cells of the selected word line through the bit lines BL0 to BLm in the read operation mode, and supplies a power supply voltage (or to the bit lines BL0 to BLm according to the data programmed in the program operation mode. A program-inhibited voltage (program-inhibited voltage) or a ground voltage (or program voltage) is supplied.

  In a NAND flash memory device, as is well known, a cell that should not be programmed due to cell structure characteristics (hereinafter referred to as a program inhibit cell) may be soft-programmed with a program voltage. It is called program distribution. Program disturb of the program-inhibited cell is prevented by increasing the channel voltage of the cell string to which the program-inhibited cell belongs, which is called a self-boosting scheme. The channel voltage of the cell string depends on the pass voltage supplied to each non-selected word line. The higher the pass voltage is, the less the program-prohibited cell is soft programmed. On the other hand, if the pass voltage increases, the memory cells connected to each of the non-selected word lines may be soft-programmed with the pass voltage, which is called a pass disturbance. Therefore, the pass voltage is determined in consideration of the above conditions.

  The program prohibition method using the self-boosting scheme described above is disclosed in U.S. Pat. S. Patent No. No. 5,677,873, “METHOD OF PROGRAMMING FLASH EEPROM INTEGRATED CIRCUIT MEMORY DEVICES TO PREVENT INADVERTENTED PROGRAMMING OF NONDESIGNED NAND MEMORY S. Patent No. No. 5,991,202 is disclosed under the title of “METHOD FOR REDUCING PROGRAM DISTORB DURING SELF-BOOSTING IN A NAND FLASH MEMORY”.

  In the case of a NAND flash memory device, memory cells in one word line can be programmed simultaneously. Alternatively, the memory cells in one word line can be programmed in several times, which is called a partial program scheme. In the former case, the influence of the program disturb received by the memory cells of the same word line is small, but in the latter case, the memory cells of the same word line are greatly affected by the program disturb. For example, assume that only the data programmed in the memory area of the bit lines BL0 to BLi has been loaded into the sensing and latch circuit 60, as shown in the hatched portion of FIG. In this case, the memory cells in the area where data is loaded and the memory cells in the area where data is not loaded (bit lines BLi + 1 to BLm) are all connected to the same word line, so regardless of the data loading position. A program voltage is supplied to the memory cells of the same word line. Accordingly, an increase in the number of partial programs NOP increases the possibility that a program-inhibited memory cell is soft-programmed.

  Such a partial program method is often used when a user manages data in units smaller than the page size in a state where the page size is wide. For example, a user who executes a program in units of 528 (512 + 16) bytes must execute four partial programs for a device having a page size of 2112 (2K + 64) bytes. At this time, 16 bytes out of 528 bytes are stored in the spare field memory area (see FIG. 2), and 512 bytes are stored in the main field memory area.

Therefore, if the number of partial programs that must be executed increases, the NAND flash memory device becomes vulnerable to program disturb.
U. S. Patent No. 5,677,873 U. S. Patent No. 5,991,202 U. S. Patent No. 5,861,772

  An object of the present invention is to provide a NAND flash memory device that can alleviate program voltage disturbance caused by a partial program.

  According to a feature of the present invention, a NAND flash memory device is an array of memory cells arranged in rows and columns, wherein the columns are separated into at least two column regions and each row is arranged in each column region. An array separated into two electrically isolated word lines, a register that latches data programmed into the array, a gate circuit that transmits data programmed in response to column address information to the register, and a program operation During which the column address information is configured to determine whether the data loaded in the register belongs to which column area and to select one of the rows in response to the row address information. Selection means for driving one or all of the word lines of the row selected according to the discrimination result to the program voltage.

  In this embodiment, when the data loaded into the register belongs to all of the column regions, the selection means drives all the word lines of the selected row to the program voltage. Alternatively, when the data loaded into the register belongs to any one of the column regions, the selection unit drives one of the word lines of the selected row to the program voltage, and the word driven to the program voltage. The line corresponds to the column area of the loaded data.

  Preferably, the selection unit drives one of the word lines of the selected row to the program voltage, and the word line driven to the program voltage is selected with the first selection circuit belonging to one of the column regions. One of the word lines in the row is driven to a program voltage, and the word line driven to the program voltage includes a second selection circuit belonging to the other one of the column regions. Further, the discriminating means detects a column area to which the data loaded in the register belongs in response to a column address for selecting a column area, and generates a selection signal as a detection result, and responds to the selection signal. And a switch circuit for selectively transmitting a program voltage to the first and second selection circuits.

  According to another aspect of the invention, the flash memory device is an array separated into a first memory block and a second memory block, each of the first and second memory blocks having a plurality of NAND strings, Each NAND string selects one of the array of memory cells connected to the corresponding word line and the word line of the first memory block, sets the selected word line to the program voltage, and the unselected word. The first row decoder circuit for driving the line to the pass voltage and one of the word lines of the second memory block are selected, the selected word line is driven to the program voltage, and the non-selected word line is driven to the pass voltage A second row decoder circuit for latching, a page buffer circuit for latching data programmed into the array, and a column array A gate circuit that transmits data to be programmed in response to the memory to the page buffer circuit, and a data loaded in the page buffer circuit in response to a column address for selecting the first and second memory blocks. A determination circuit that determines whether or not the memory block is programmed and generates a selection signal as a determination result, and a drive signal that is supplied to each corresponding word line of each of the first and second memory blocks, and a program During operation, one of the driving signals has a program voltage, and the remaining driving signals are a driving signal generating circuit having a pass voltage, and the first and second row decoder circuits in response to a selection signal from the discrimination circuit. And a switch circuit that switches the drive signal to all or any one of them.

  Preferably, the discrimination circuit sets the first and second flip-flops to be reset by a reset signal and the first flip-flop in response to an address signal input for designating the first memory block during a program operation. A first set circuit to be output, a first selection signal among the selection signals is output by receiving the output signal of the first flip-flop, the first selection signal having a high voltage when activated, and a program operation A second set circuit for setting a second flip-flop in response to an input of an address signal for designating a second memory block, and an output signal of the second flip-flop is inputted as a second selection signal among the selection signals And the second selection signal includes a second high voltage switch having a high voltage when activated. The reset signal is activated when a sequential data input command is input. The switch circuit operates in response to the first and second selection signals and includes a switch corresponding to each of the drive signals, and each of the switches transmits the drive signal corresponding to the first row decoder circuit in response to the first selection signal. And a second depletion type MOS transistor for transmitting a driving signal corresponding to the second row decoder circuit in response to the second selection signal.

  According to still another aspect of the present invention, the array additionally includes a spare field memory area, and the spare field memory area is separated into spare memory blocks corresponding to the first and second memory blocks, respectively. Are arranged with corresponding memory blocks. Memory blocks and spare memory blocks arranged in the same area are controlled by the same row decoder circuit.

  According to the present invention, since a program voltage and a pass voltage are not applied to a word line of a memory block corresponding to a sensing and latch circuit in which data to be programmed is not loaded, program voltage disturbance due to a partial program scheme can be prevented. (Or can be relaxed).

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 3 is a block diagram illustrating a NAND flash memory device according to an embodiment of the present invention. Referring to FIG. 3, the NAND flash memory device 100 includes an array of memory cells arranged in rows and columns. According to the present invention, the columns of the array are separated into two column regions, and each row is separated into two electrically isolated word lines respectively arranged in each column region. For convenience of explanation, one column region is referred to as a first memory block 110R constituting a first mat (or first memory cell array), and the other one column region constitutes a second mat (or second memory cell array). This is referred to as a second memory block 110L. Each of the first and second memory blocks 110R and 110L includes a plurality of cell strings, and each cell string has the same configuration as that shown in FIG. A row selection circuit is disposed between the first and second memory blocks 110R and 110L, and the row selection circuit includes first and second word line switch blocks 120R and 120L and a block decoder 130. The row selection circuit is shared by the first and second memory blocks 110R and 110L.

  As another example, as shown in FIG. 4, the row selection circuit may be composed of two row decoder circuits 120R, 130R and 120L, 130L corresponding to the first and second memory blocks 110R, 110L, respectively. In this case, each row decoder circuit includes a block decoder 130R or 130L and a word line switch block 120R or 120L. Although not shown in the figure, as shown in FIG. 2, the first and second memory blocks 110R and 110L additionally include a spare field memory area in addition to the main field memory area.

  Referring to FIG. 3 again, the string selection line SSL, the word lines WL15 to WL0, and the ground selection line GSL arranged along the row direction of the first memory block 110R are electrically connected to the first word line switch block 120R. Has been. The first word line switch block 120R receives the drive signals SiR (i = 0 to 15) from the switch circuit 160 and the drive signals SS and GS from the drive signal generation circuit 140 according to the signals on the block word line BLKWL. The signals are transmitted to the corresponding signal lines SSL, WL0 to WL15, and GSL, respectively. The string selection line SSL, the word lines WL15 to WL0, and the ground selection line GSL arranged along the row direction of the second memory block 110L are electrically connected to the second word line switch block 120L. The second word line switch block 120L receives the drive signal SiL (i = 0 to 15) from the switch circuit 160 and the drive signals SS and GS from the drive signal generation circuit 140 according to the signal on the block word line BLKWL. The signals are transmitted to the corresponding signal lines SSL, WL0 to WL15, and GSL, respectively. The block decoder 130 activates / deactivates the block word line BLKWL according to row address information for designating a memory block.

  The drive signal generation circuit 140 outputs drive signals SS, S0 to S15, and GS in response to row address information for selecting one of the word lines arranged in each memory block. During the read operation, the drive signals SS and GS each have a power supply voltage VCC, one drive signal among the drive signals S0 to S15 has a ground voltage, and the remaining drive signals have a read voltage. During the program operation, the drive signal SS has a power supply voltage, and the drive signal GS has a ground voltage. At this time, one of the drive signals S0 to S15 has a program voltage, and the remaining drive signal has a pass voltage. The drive signal generation circuit 140 is supplied with a program voltage, a pass voltage, and a read voltage from the high voltage generation circuit 180 according to an operation mode in order to transmit a high voltage to each drive signal Si (i = 0 to 15) line.

  Referring to FIG. 3, the bit lines BL0 to BLm arranged along the column direction of the first and second memory blocks 110R and 110L are electrically connected to the corresponding sensing and latch circuits 170R and 170L. Yes. Each of the sensing and latch circuits 170R and 170L senses data from the flash EEPROM cell of the selected word line through the bit lines BL0 to BLm in the read operation mode. Each of the sensing and latch circuits 170R and 170L latches programmed data transmitted through the gate circuits 190R and 190L in a program operation mode, and supplies a power supply voltage or a ground voltage to the bit lines BL0 to BLm according to the latched data. . The switch circuit 160 receives the drive signals S0 to S15 from the drive signal generation circuit 140, and receives the first drive signals S0R to S15R and / or the second drive signals S0L to S15L in response to the selection signals VM1 and VM2 from the determination circuit 150. Output. The output signal of switch circuit 160 has the same voltage as its input signal. The determination circuit 150 outputs selection signals VM1 and VM2 in response to column address information for designating a memory block. Here, the selection signals VM1 and VM2 are activated exclusively or simultaneously. For example, the selection signals VM1 and VM2 are activated at the same time during the read and erase operations, and are activated at the same time or exclusively during the program operation. This will be described in detail later.

  FIG. 5 is a preferred embodiment of the block decoder 130 and the first and second word line switch blocks 120R and 120L shown in FIG. The first word line switch block 120R includes pass transistors SW27 to SW20 corresponding to the drive signals SS, S15R to S0R, and GS, respectively. The gates of the pass transistors SW27 to SW20 are commonly connected to the block word line BLKWL. The drive signals SS, S15R to S0R, and GS are transmitted to the string selection line SSL, the word lines WL15 to WL0, and the ground selection line GSL through the pass transistors SW27 to SW20, respectively. When the read operation is performed, one of the drive signals S15R to S0R has a ground voltage, and the remaining drive signals have a read voltage. When the program operation is performed, one of the drive signals S15R to S0R has a program voltage, and the remaining drive signals have a pass voltage. The pass transistors SW20 to SW27 of the first word line switch block 120R are composed of high voltage NMOS transistors.

  The second word line switch block 120L includes pass transistors SW27 to SW20 corresponding to the drive signals SS, S15L to S0L, and GS, respectively. The gates of the pass transistors SW27 to SW20 are commonly connected to the block word line BLKWL. The drive signals SS, S15L to S0L, and GS are transmitted to the string selection line SSL, the word lines WL15 to WL0, and the ground selection line GSL through the pass transistors SW27 to SW20, respectively. When the read operation is performed, one of the drive signals S15L to S0L has a ground voltage, and the remaining drive signals have a read voltage. When the program operation is performed, one of the drive signals S15L to S0L has a program voltage, and the remaining drive signals have a pass voltage. The pass transistors SW20 to SW27 of the second word line switch block 120L are composed of high voltage NMOS transistors.

  Next, referring to FIG. 5, the block decoder 130 includes NAND gates G1, G2, and G3 and NMOS transistors M1, M2, M3, and M4, which are connected as shown in the figure. The NMOS transistors M2 and M4 are controlled by the output signal of the NAND gate G3, and the NMOS transistors M1 and M3 are controlled by the control signals ERSen and VPRE, respectively. The control signal ERSen has a low level during a program and read operation, and has a high level during an erase operation. The NMOS transistor M2 is used to discharge the block word line BLKWL and is turned on when the control signal BLKWLdis is at a low level. The NMOS transistor M4 is shared by the first and second memory blocks 110R and 110L, and is connected between the string selection line SSL and the SSLGND node of the first and second memory blocks 110R and 110L. Here, the SSLGND node has a ground voltage during program and read operations, and has a power supply voltage during erase operations. The control signals XDECdis and BLKWLdis are maintained at a high level during a period in which data is programmed in the memory cell.

  FIG. 6 is a circuit diagram illustrating the determination circuit 150 of FIG. 3 according to a preferred embodiment of the present invention.

  Referring to FIG. 6, the determination circuit 150 according to the present invention includes inverters INV1 and INV2, AND gates G4 and G5, NOR gates G6 and G7, SR flip-flops FF1 and FF2, and high voltage switches 151 and 152. Are connected as shown in The high voltage switches 151 and 152 are composed of a switch pump circuit, and the switch pump circuit has a title of “CHARGE PUMP CIRCUIT OF NONVOLATILE SEMICONDUCTOR MEMORY”. S. Patent No. 5,861,772. As is well known, each of the high voltage switches 151 and 152 converts the voltage level of the input signal to a high voltage (eg, a program voltage).

  The determination circuit 150 receives the program plug signal nPGM, the address signal CAi, the reset signal RST, and the clock signal CLK. The determination circuit 150 determines which sensing and latch circuits are loaded with programmed data, and activates the selection signals VM1 and VM2 simultaneously or exclusively according to the determination result. In FIG. 5, the program plug signal nPGM is activated to a low level during a program operation and deactivated to a high level during an erase and read operation. The address signal CAi is an address signal for selecting the memory blocks 110R and 110L. For example, the first memory block 110R is selected when the address signal CAi is “0”, and the second when the address signal CAi is “1”. Memory block 110L is selected. The clock signal CLK is a signal used for loading data to be programmed, and the reset signal RST is a pulse signal activated when a sequential data input command is input.

  In the circuit operation, the reset signal RST is activated by inputting a sequential data input command. At this time, the program plug signal nPGM is maintained at a low level. As the reset signal RST is activated, the outputs of the flip-flops FF1 and FF2 become low. That is, the selection signals VM1 and VM2 are initialized to a low level, respectively. Thereafter, the data to be programmed is sequentially loaded into the sensing and latch circuit as the column address increases. When the column address signal CAi is maintained at “0” during the data loading period, the output signal S of the NOR gate G6 transitions from the high level to the low level in synchronization with the low-high transition of the clock signal CLK. That is, the output of the flip-flop FF1 is activated from the low level to the high level. At this time, the output of the flip-flop FF2 is continuously maintained at a low level. If the address signal CAi continues to be “0” until all the data is loaded, the data to be programmed is loaded only into the sensing and latch circuit 170R of the first memory block 110R. In such a case, only the selection signal VM1 is activated high. If the address signal CAi changes to “1” while data is being loaded, the output signal S of the NOR gate G7 changes from high level to low level in synchronization with the low-high transition of the clock signal CLK. That is, the output of the flip-flop FF2 is activated from the low level to the high level. In such a case, the selection signals VM1 and VM2 are all activated high. The activated selection signals VM1 and VM2 have a high voltage through the corresponding high voltage switches 151 and 152.

  The determination circuit 150 activates the selection signal VM1 when the data to be programmed is loaded only into the sensing and latch circuit 170R of the first memory block 110R. The determination circuit 150 activates the selection signal VM2 when the data to be programmed is loaded only into the sensing and latch circuit 170L of the second memory block 110L. The determination circuit 150 activates the selection signals VM1 and VM2 when all data to be programmed is loaded into the sensing and latch circuits 170R and 170L of the first and second memory blocks 110R and 110L.

  FIG. 7 is a circuit diagram illustrating the switch circuit 160 of FIG. 3 according to a preferred embodiment of the present invention. Referring to FIG. 7, the switch circuit 160 is supplied with drive signals S0 to S15 output from the drive signal generation circuit 140, and responds to the selection signals VM1 and VM2 from the determination circuit 150, or the first drive signals S0R to S15R or Second drive signals S0L to S15L are output. The switch circuit 160 corresponds to the drive signals S0 to S15 and is commonly controlled by the selection signal VM1, and is commonly controlled by the selection signal VM2 and the depletion type MOS transistors 161, 163,. The depletion type MOS transistors 162, 164,.

  When the data to be programmed is loaded only into the sensing and latch circuit 170R of the first memory block 110R, the determination circuit 150 activates the selection signal VM1. Then, the switch circuit 60 outputs the drive signals S0 to S15 from the drive signal generation circuit 140 as the first drive signals S0R to S15R applied to the first word line switch block 120R. When the data to be programmed is loaded only into the sensing and latch circuit 170L of the second memory block 110L, the determination circuit 150 activates the selection signal VM2. Then, the switch circuit 160 outputs the drive signals S0 to S15 from the drive signal generation circuit 140 as the second drive signals S0L to S15L applied to the second word line switch block 120L. When all data to be programmed is loaded into the sensing and latch circuits 170R and 170L of the first and second memory blocks 110R and 110L, the determination circuit 150 activates the selection signals VM1 and VM2 at the same time. Then, the switch circuit 160 applies the drive signals S0 to S15 from the drive signal generation circuit 140 to the first and second word line switch blocks 120R and 120L, and the first and second drive signals S0R to S15R and S0L to S15L. As output.

  FIG. 8 is a timing diagram illustrating a program operation of the NAND flash memory device according to the present invention. The program operation of the memory device according to the present invention will be described in detail with reference to the accompanying drawings.

  As is well known, according to the program operation of the NAND flash memory device, first, a sequential data input command is applied, and the first column address and row (or page) address at which data is loaded. Are input continuously. The first column address is loaded into an internal address counter (not shown), and the internal address counter increments the internal column address by one bit each time data is input in a determined unit (byte or word unit). Data to be programmed is loaded to a sensing and latch circuit as a page buffer circuit through a gate circuit by increasing a column address. When all data to be programmed is loaded, a program command for starting the program is input. Then, the NAND flash memory device performs a program operation by an internal algorithm after inputting a program command, and informs the outside that the memory device is in a busy state through the R / nB pin during the program operation.

  When a sequential data input command is input, the reset signal RST is activated in a pulse form. When the reset signal RST transitions from the low level to the high level, the flip-flops FF1 and FF2 of the determination circuit 150 are initialized. By initializing the flip-flops FF1 and FF2, as shown in FIG. 8, the output signals of the determination circuit 150, that is, the selection signals VM1 and VM2 are set to a low level. Next, the first column address CAi into which data is loaded is input, and an internal address counter (not shown) is set to the first column address. Assume that the column address (for example, the most significant address signal) for selecting the memory block among the first column addresses is “0”. According to this assumption, the data to be programmed is loaded into the sensing and latch circuit 170R of the first memory block 110R.

  After inputting the column address, the data to be programmed is loaded into the sensing and latch circuit 170R through the gate circuit 190R in synchronization with the clock signal CLK. Since the column address for selecting the memory block is “0”, the output signal of the NOR gate G6 of the determination circuit 150 transitions from the high level to the low level when the clock signal CLK transitions to the low and high levels. This causes the selection signal VM1 to transition from the low level to the high level. At this time, the activated selection signal VM1 has a high voltage through the high voltage switch 151.

  If the column address for selecting the memory block is continuously maintained at “0” until all the data to be programmed is loaded, only the selection signal VM1 is activated. This causes the drive signals S0 to S15 input to the switch circuit 160 to be transmitted only to the first word line switch block 120R. When data loading is completed and a program command is input, a program voltage and a pass voltage are applied to the word line of the first memory block 110R. On the other hand, since the selection signal VM2 is in an inactive state, the program voltage and the pass voltage are not applied to the word line of the second memory block 110L. That is, in the case of the partial program, the program voltage and the pass voltage are applied only to the word line of the memory block corresponding to the sensing and latch circuit loaded with the data to be programmed. Therefore, the program voltage and the pass voltage are not applied to the word line of the memory block corresponding to the sensing and latch circuit in which the data to be programmed is not loaded, so that the program disturb due to the partial program scheme can be prevented (or reduced). Can do).

  On the other hand, if the value of the column address for selecting the memory block changes from “0” to “1” before all the programmed data is loaded, the programmed data is transferred to the second memory block through the gate circuit 190L. 110L sensing and latching circuit 170L is loaded. When the column address changes from “0” to “1”, the output signal of the NOR gate G7 of the determination circuit 150 changes from the high level to the low level in synchronization with the clock signal CLK. This activates the select signal VM2 high. This also transmits the drive signals S0 to S15 input to the switch circuit 160 to the second word line switch block 120L. Therefore, when data loading is completed and a program command is input, a program voltage and a pass voltage are applied to the word lines of the first and second memory blocks 110R and 110L through the switch circuit 160. Accordingly, the data loaded in the sensing and latch circuits 170R and 170L is programmed in the corresponding first and second memory blocks 110R and 110L.

  Although not shown in the figure, it is obvious to those skilled in the art that the memory block of the present invention includes a corresponding spare field memory area. When one row is separated into two word lines, the spare field memory region is also separated into two regions. The separated spare field memory areas correspond to the corresponding memory blocks, respectively. Therefore, in the NAND flash memory device according to the present invention, as shown in FIG. 2, the memory cell array includes one of the spare field memory regions from which the first memory block 110R is separated, and the second memory block 110L It is configured to include the remaining spare field memory area. In the manner described above, the word lines of the memory block and the corresponding spare field memory area are controlled by the same row selection circuit.

  In the above embodiment, the present invention has been described based on a structure in which one array is simply separated into two memory blocks. However, it is obvious to those skilled in the art that the technical idea of the present invention can be applied to a structure in which one array is divided into four, eight, or more memory blocks. is there. Therefore, the above embodiment is merely an example, and it is needless to say that the present invention can be variously changed and changed without departing from the technical idea and scope of the present invention.

1 is a block diagram showing a general NAND flash memory device. It is a figure for demonstrating a general partial program system. 1 is a block diagram illustrating a NAND flash memory device according to an embodiment of the present invention; FIG. FIG. 5 is a block diagram illustrating a NAND flash memory device according to another embodiment of the present invention. FIG. 4 is a circuit diagram illustrating a block decoder and a word line switch block of FIG. 3 according to a preferred embodiment of the present invention. FIG. 4 is a circuit diagram illustrating a determination circuit of FIG. 3 according to a preferred embodiment of the present invention. FIG. 4 is a circuit diagram illustrating the switch circuit of FIG. 3 according to a preferred embodiment of the present invention. FIG. 10 is a timing diagram illustrating a partial program operation of the NAND flash memory device according to the present invention.

Explanation of symbols

100 NAND type flash memory device 110R, 110L first and second memory block 120R, 120L first and second word line switch block 130 block decoder 140 drive signal generation circuit 150 discriminating circuit 160 switch circuit 170R, 170L sensing and latch circuit 180 High voltage generation circuit

Claims (17)

An array of memory cells arranged in rows and columns, wherein the columns are separated into at least two column regions, and each row is divided into two electrically isolated word lines arranged in each column region. An isolated array;
A register for latching data programmed into the array;
A gate circuit for transmitting the programmed data to the register in response to column address information;
Means for determining whether the data loaded in the register belongs to which column area during a program operation, and outputting a selection signal as a determination result ;
Selecting means for selecting one of the rows in response to row address information and driving one , a plurality, or all of the word lines of the selected row to a program voltage in response to the selection signal ; , only including,
The means for outputting the selection signal includes a plurality of flip-flops each reset by a reset signal,
A plurality of set circuits for setting the corresponding flip-flops in response to an input of an address signal for designating each column region during the program operation;
The output signals of the corresponding flip-flops are input to output the corresponding selection signals, and the corresponding selection signals include a plurality of high voltage switches having a high voltage when activated. A non-volatile semiconductor memory device.   The non-volatile semiconductor memory device according to claim 1, wherein the determination unit determines whether or not to which column area the data loaded in the register belongs according to column address information.   2. The non-volatile semiconductor device according to claim 1, wherein when the data loaded in the register belongs to all of the column regions, the selection unit drives all the word lines of the selected row to the program voltage. Memory device.   When the data loaded into the register belongs to any one of the column regions, the selection unit drives one of the word lines of the selected row to the program voltage, and the word driven to the program voltage. The nonvolatile semiconductor memory device according to claim 1, wherein a line corresponds to a column area of the loaded data.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the selection unit drives all word lines of a selected row to a ground voltage regardless of a determination result of the determination unit during a read operation. .   2. The nonvolatile semiconductor memory device according to claim 1, wherein the selection unit drives all word lines of a selected row to a ground voltage regardless of a determination result of the determination unit during an erasing operation. . The selection means includes
One of the word lines of the selected row is driven to the program voltage, and the word line driven by the program voltage belongs to one of the column regions;
One of the word lines of the selected row is driven to the program voltage, and the word line driven to the program voltage includes a second selection circuit belonging to another one of the column regions. The nonvolatile semiconductor memory device according to claim 1. The discrimination means includes
In response to a column address for selecting the column region, a detection circuit that detects a column region to which the data loaded in the register belongs, and generates a selection signal as a detection result;
8. The nonvolatile semiconductor memory device according to claim 7, further comprising a switch circuit that selectively transmits the program voltage to the first and second selection circuits in response to the selection signal.   The nonvolatile semiconductor device according to claim 1, wherein a pass voltage is applied to a word line of an unselected row in a column region including the word line of the selected row to which the program voltage is supplied. Memory device. An array separated into a first memory block and a second memory block, wherein each of the first and second memory blocks has a plurality of NAND strings, and each NAND string is connected to a corresponding word line. Including an array of memory cells,
A first row decoder circuit for selecting one of the word lines of the first memory block, driving the selected word line to a program voltage, and driving a non-selected word line to a pass voltage;
A second row decoder circuit for selecting one of the word lines of the second memory block, driving the selected word line to the program voltage, and driving a non-selected word line to the pass voltage;
A page buffer circuit for latching data programmed into the array;
A gate circuit for transmitting the programmed data to the page buffer circuit in response to a column address;
In response to a column address for selecting the first and second memory blocks, it is determined in which memory block the data loaded in the page buffer circuit is programmed, and a selection signal is determined as a determination result. A discriminating circuit for generating
A driving signal supplied to a corresponding word line of each of the first and second memory blocks is generated. During a program operation, one of the driving signals has the program voltage, and the remaining driving signals are the A drive signal generating circuit having a pass voltage;
Wherein in response to the selection signal from the determination circuit saw including a switch circuit for switching said drive signal all or any one of the first and second row decoder circuit,
The discrimination circuit includes:
First and second flip-flops that are respectively reset by a reset signal;
A first set circuit for setting the first flip-flop in response to an input of an address signal for designating the first memory block during the program operation;
An output signal of the first flip-flop is input to output a first selection signal among the selection signals, the first selection signal having a high voltage when activated;
A second set circuit for setting the second flip-flop in response to an input of an address signal for designating the second memory block during the program operation;
The flash is characterized in that an output signal of the second flip-flop is inputted to output a second selection signal among the selection signals, and the second selection signal includes a second high voltage switch having a high voltage when activated. Memory device. 11. The flash memory device according to claim 10 , wherein the reset signal is activated when a sequential data input command is input. The switch circuit includes switches that operate in response to the first and second selection signals and respectively correspond to the drive signals;
Each of the switches includes a first depletion type MOS transistor that transmits a driving signal corresponding to the first row decoder circuit in response to the first selection signal, and the second row decoder in response to the second selection signal. 11. The flash memory device according to claim 10 , further comprising a second depletion type MOS transistor for transmitting a driving signal corresponding to the circuit. The array additionally includes a spare field memory area, and the spare field memory area is divided into spare memory blocks respectively corresponding to the first and second memory blocks, and each of the spare memory blocks is associated with a corresponding memory block. The flash memory device according to claim 10 , wherein the flash memory device is arranged. 14. The flash memory device according to claim 13 , wherein the memory block and the spare memory block arranged in the same area are controlled by the same row decoder circuit. An array separated into a plurality of memory blocks, each of the memory blocks having a plurality of NAND strings, each NAND string including a memory cell coupled to a corresponding word line;
A plurality of rows corresponding to each of the memory blocks, each of which selects one of the word lines of the corresponding memory block, drives the selected word line to a program voltage, and drives a non-selected word line to a pass voltage. A decoder circuit;
A page buffer circuit for latching data programmed into the array;
A gate circuit for transmitting the programmed data to the page buffer circuit in response to a column address;
A determination circuit that determines whether or not the data loaded in the page buffer circuit is programmed in response to a column address for selecting the memory block, and generates a selection signal as a determination result When,
A driving signal supplied to a corresponding word line of each of the memory blocks is generated. During a program operation, one of the driving signals has the program voltage, and the remaining driving signals have the pass voltage. A signal generation circuit;
A switch circuit that selectively switches the drive signal to the row decoder circuit in response to a selection signal from the determination circuit;
The driving signal is transmitted to one or more row decoder circuits in which data loaded in the page buffer circuit is programmed ,
The determination circuit includes a plurality of flip-flops each reset by a reset signal,
During the program operation, in response to a column address for selecting the memory block, an output signal of the corresponding flip-flop is input, the corresponding selection signal is output, and the corresponding selection signal is output. Includes a plurality of high voltage switches having a high voltage when activated . The array additionally includes a spare field memory area, the spare field memory area is divided into spare memory blocks corresponding to the memory blocks, and each of the spare memory blocks is arranged together with the corresponding memory block. 16. The flash memory device according to claim 15 , wherein: 17. The flash memory device according to claim 16 , wherein the memory block and the spare memory block arranged in the same area are controlled by the same row decoder circuit.

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