KR20090000330A - Data setting method of non volatile memory device - Google Patents

Abstract

A data setting method of non volatile memory device is provided to reduce a time required for data input without a data input process by setting identically up data of the total page. A data setting method of non volatile memory device is comprised of the steps; inputting a program setup command(510); Inputting the address of the memory cell performing the program operation(520); Inputting a confirmation command without a step for inputting data from outside(530); making the first data setting control signal enabled with the input of the first confirm command; completing data setting in the register of each page buffer according to inputting the first and second command.

Description

Data setting method of non volatile memory device

1 is a view showing the overall configuration of a nonvolatile memory device to which the present invention is applied.

2 is a waveform diagram of signals associated with a typical program operation of a nonvolatile memory device.

3 is a circuit diagram illustrating a page buffer according to an embodiment of the present invention.

4 is a circuit diagram showing a specific configuration of the first data setting unit and the second data setting unit.

5 is a flowchart illustrating a method of operating the first data setting unit and the second data setting unit.

6A is a waveform diagram illustrating an operation of the first data setting unit.

6B is a waveform diagram illustrating an operation of the second data setting unit.

The present invention relates to a nonvolatile memory device, and more particularly, to a data setting method of a nonvolatile memory device that sets specific data to a specific node of a register before a program operation of the nonvolatile memory device.

Recently, there is an increasing demand for nonvolatile memory devices that can be electrically programmed and erased, and do not require a refresh function that requires rewriting data at regular intervals. Attempts to store more than one bit of data in one cell are ongoing.

The nonvolatile memory device typically includes a memory cell array having cells in which data is stored in a matrix form, and a page buffer for writing a memory to a specific cell of the memory cell array or reading a memory stored in a specific cell. . The page buffer may include a pair of bit lines connected to a specific memory cell, a register for temporarily storing data to be written to the memory cell array, or a register for reading and temporarily storing data of a specific cell from the memory cell array, a voltage of a specific bit line or a specific register. It includes a sensing node for sensing a level, a bit line selection unit for controlling the connection of the specific bit line and the sensing node.

 In the program method of the nonvolatile memory device as described above, when a particular page is programmed with the same data as '0' or '1', the data is repeatedly applied to each page buffer in the conventional program method. As the memory capacity increases, so does the time for which data is applied to each page buffer.

In order to solve the above-described problem, an object of the present invention is to provide a data setting method of a nonvolatile memory device that can set the data of all pages equally without a separate data input procedure.

The data setting method of the nonvolatile memory device of the present invention for achieving the above object of the present invention is a first data setting unit for applying the first data to the first node of the register and the first node to the second node of the register. A program setup command is input to a plurality of page buffers including a second data setting unit for applying data, an address of a memory cell where specific data is to be stored, and a confirmation command is input to set specific data. Activating a negative data setting control signal, outputting a high level data setting signal while the operation status signal and the data setting control signal simultaneously have a high level value, and specifying the register by the data setting signal; Applying the first data to a node It features.

 Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view showing the overall configuration of a nonvolatile memory device to which the present invention is applied.

The nonvolatile memory device 100 includes a memory cell array 102, a page buffer 108, an X / Y-decoder 104 and 106, a high voltage generator 110, a command interface logic unit 112, and a command register ( 114, an address register / counter 116, and an IO buffer unit 120.

An operation of the nonvolatile memory device will be described.

First, when the chip enable signal / CE is disabled and the write enable signal / WE is toggled with respect to the command interface logic unit 112, the command interface logic unit 112 may respond in response thereto. The command signal received through the IO buffer unit 110 and the command register 114 is received, and a program command, an erase command, or a read command is generated according to the command. In this case, the command signal includes a page program setup code for determining an operation mode of the nonvolatile memory device. Meanwhile, the operation state signal / R / B output from the command interface logic unit 112 is disabled for a predetermined time, and an external memory controller (not shown) transmits the operation state signal / R / B. Receives and recognizes that the nonvolatile memory device is in an operating state such as program / erase / read. That is, during the time when the operation state signal / R / B is disabled, program / erase / read of one page of the memory cell array is executed.

In addition, the address register / counter 116 receives an address signal received through the IO buffer unit 120 and generates a row address signal and a column address signal. The address signal corresponds to one of pages included in one of the memory cells.

The high voltage generator 110 generates bias voltages in response to the program command, erase command or read command and supplies them to the page buffer 108, the X-decoder 104, and the like.

The X-decoder 104 supplies the bias voltages supplied from the high voltage generator 110 to the memory cell array 102 in one of the blocks of the memory cell array in response to the row address signal.

The Y-decoder 106 supplies a data signal to bit lines (not shown) shared by the blocks of the memory cell array through the page buffer in response to the column address signal.

The page buffer 108 latches a data signal received through the IO buffer unit 110 and the Y-decoder 106 to bit lines (not shown) shared by the blocks of the memory cell array. Output

2 is a waveform diagram of signals associated with a typical program operation of the nonvolatile memory device.

First, the IO buffer unit 120 receives a start command signal including a program setup code (for example, 80h) from an external device, and outputs it to the command interface logic unit 112. In addition, the IO buffer unit 120 receives external address signals from the external device and outputs the external address signals to the address register / counter 116. The address register / counter 116 outputs a plane address signal, a block address signal, a column address signal, and the like based on some of the address signals.

In addition, the IO buffer unit 120 receives data from the external device and inputs the data to the page buffer 108.

Thereafter, when a confirmation command signal including a confirmation code (eg, 10h) is input, the command interface logic unit 112 disables the operation status signal / R / B for a set time. . During this time, the program operation proceeds.

However, in the case of the above method, when the data of the entire page is the same as '0' or '1', the time required for data input is unnecessarily long.

3 is a circuit diagram illustrating a page buffer according to an embodiment of the present invention.

The page buffer 300 includes first and second registers 330 and 340, bit lines BLe and BLo, and a sensing node SO and even bits formed at connection points of the respective registers. A bit line selection unit 310 for selectively connecting a line BLe or an odd bit line BLO to the sensing node SO, and a data input unit for storing data input externally to the first register 330 ( 350). In addition, the first data setting unit 360 sets the first node QA of the first register 330 to '0' data, and the first node QA of the first register 330 to '1' data. And a second data setting unit 370 set to.

The bit line selector 310 may include an NMOS transistor N316 connecting the even bit line BLe and the sensing node SO in response to a first bit line select signal BSLe, and a second bit line select signal. And an NMOS transistor N318 connecting the odd bit line BLo and the sensing node SO in response to BSLo.

In addition, the bit line selector 310 connects the even bit line BLe and the control signal input terminal in response to a control signal input terminal for applying a control signal VIRPWR having a specific level and a first discharge signal DISCHe. NMOS transistor N312 and an NMOS transistor N314 connecting the odd bit line BLo and a control signal input terminal in response to a second discharge signal DISCHo.

 The first resistor 330 includes a first latch including two inverters IV332 and IV334, an NMOS transistor N334 connected to a ground power source, and turned on in response to a voltage level of the sensing node SO, and the NMOS. An NMOS transistor N336 connected between the transistor N334 and the first node QA of the first latch and turned on in response to the first data setting signal PBRESET_L, and the NMOS transistor N334 and the first latch of the first latch. The NMOS transistor N332 is connected between the two nodes QAb and turned on in response to the second data setting signal PBRESET_L.

In addition, the second register 340 includes a second latch including two inverters IV342 and IV344, an NMOS transistor N346 connected to a ground power source and turned on in response to a voltage level of the sensing node SO; An NMOS transistor N342 connected between the NMOS transistor N346 and the first node QB of the second latch and turned on in response to the data setting signal PBSET_R, and the second of the NMOS transistor N346 and the second latch. The NMOS transistor N344 is connected between the nodes QBb and turned on in response to the data reset signal PBRESET_R.

In addition, the page buffer senses data stored in a specific node of a specific latch in response to a program signal PGM and a PMOS transistor P320 for connecting the sensing node SO and a power supply voltage in response to a precharge signal PRECH_N. An NMOS transistor N322 applied to the node SO and an NMOS transistor N324 for outputting data stored in a specific node of a specific latch to the outside in response to the data output signal PBDO.

The data input unit 350 is connected between the data input terminal YA and the first node QA of the first latch and is turned on in response to the first data input signal nDI and the NMOS transistor N354 and the data input terminal. And an NMOS transistor N352 connected between YA and a second node QAb of the first latch and turned on in response to the second data input signal DI. Therefore, data stored in the first node varies according to the level of the first data input signal or the second data input signal.

The first data setting unit 360 inputs an operation state signal / R / B and a first data setting control signal PAGEPGM_A0 output from the command interface logic unit 112 of FIG. 1 to set first data. Generate the signal PBRESET_L.

Also, the second data setting unit 370 generates the second data setting signal PBSET_L by inputting the operation state signal / R / B and the second data setting control signal PAGEPGM_A1.

Now, a detailed configuration of the first data setting unit 360 and the second data setting unit 370 will be described.

4 is a circuit diagram showing a specific configuration of the first data setting unit and the second data setting unit.

The first data setting unit 360 may include an AND gate AND362 and an operation state signal (/ R / B) that input an operation state signal (/ R / B) and a first data setting control signal (PAGEPGM_A0). Negative-OR gate NOR364, which receives the logical product signal of the first data setting control signal PAGEPGM_A0 and the data reset signal PBRESET, and an output signal of the negative-OR gate, invert the first data setting signal PBRESET_L. And an inverter IV366 for outputting.

The second data setting unit 370 includes an AND gate (AND372), an operation state signal (/ R / B), and an operation state signal (/ R / B) and a second data setting control signal (PAGEPGM_A1). Negative-OR gate NOR374, which inputs the AND signal of the second data setting control signal PAGEPGM_A1 and the data set signal PBSET, and the output signal of the negative-OR gate, are inverted to convert the second data-setting signal PBSET_L. And an inverter IV376 for outputting.

An operation of each data setting unit will be described with reference to the drawings.

5 is a flowchart illustrating an operating method of the first data setting unit and the second data setting unit.

First, a program setup command is entered (step 510).

Next, various addresses for the memory cells in which the program operation is performed are input (step 520).

Next, a confirmation command (PGM A0h or PGM A1h) is immediately input (step 530) without inputting data from the outside. The first confirmation command PGM A0h is a command signal for inputting '0' data on the entire page, and the second confirmation command PGM A1h is a command signal for inputting '1' data on the entire page.

The first data setting control signal PAGEPGM_A0 is enabled by the input of the first confirmation command PGM A0h, and the second data setting control signal PAGEPGM_A0 is set by the input of the second confirmation command PGM A0h. Is enabled.

Upon completion of data setting in the register of each page buffer according to the input of the confirmation command, a program operation is performed according to the set data (step 540).

6A and 6B are waveform diagrams illustrating operations of the first data setting unit and the second data setting unit.

Referring to FIG. 6A, the first data setting control signal PAGEPGM_A0 is enabled by the input of the first confirmation command PGM A0h.

Next, the operation state signal / R / B is disabled to the low level.

The first data setting signal PBRESET_L becomes high during a period in which the first data setting control signal PAGEPGM_A0 and the operation state signal / R / B simultaneously have a high level value by the first data setting unit 360. Has a level value.

At this time, the sensing node precharge signal PRECH_N maintains the low level value during the period in which the first data setting signal PBRESET_L has a high level value. As a result, the NMOS transistor N334 of FIG. 1 is turned on, and the NMOS transistor N336 is turned on by the first data setting signal PBRESET_L.

Therefore, the first node QA of the first latch is set to low level data.

Next, referring to FIG. 6B, the second data setting control signal PAGEPGM_A1 is enabled by the input of the second confirmation command PGM A1h.

Next, the operation state signal / R / B is disabled to the low level.

The second data setting signal PBSET_L becomes high during a period in which the first data setting control signal PAGEPGM_A1 and the operation state signal / R / B simultaneously have a high level value by the second data setting unit 370. Has a level value.

At this time, the sensing node precharge signal PRECH_N maintains the low level value during the period in which the second data setting signal PBSET_L has a high level value. As a result, the NMOS transistor N334 of FIG. 1 is turned on, and the NMOS transistor N332 is turned on by the second data setting signal PBSET_L.

Therefore, the first node QA of the first latch is set to high level data.

According to the above-described configuration of the present invention, when programming the same data on a page basis, the entire page can be set to the same data without using a separate data input procedure, thereby reducing the time required for data input.

Claims (11)

For a plurality of page buffers including a first data setting unit for applying first data to a first node of a register and a second data setting unit for applying the first data to a second node of the register, Where the program setup command is entered, Inputting an address of a memory cell in which specific data is to be stored; Inputting a confirmation command to activate a data setting control signal of a specific data setting unit; Outputting a high level data setting signal while the operation state signal and the data setting control signal simultaneously have a high level value; Applying the first data to a specific node of the register according to the data setting signal And a data setting method of the nonvolatile memory device. The method of claim 1, wherein when the first data is applied to the first node, second data having a level opposite to the first data is applied to the second node. The nonvolatile device according to claim 1, wherein the activating of the data setting control signal comprises inputting a first confirmation command to activate a first data setting control signal with respect to the first data setting unit. How to set data on memory device. The nonvolatile memory as claimed in claim 1, wherein the activating of the data setting control signal comprises inputting a second confirmation command to activate a second data setting control signal with respect to the second data setting unit. How to set data on your device. The method of claim 3, wherein the outputting of the data setting signal comprises outputting a first data setting signal having a high level while an operation state signal and the first data setting control signal simultaneously have a high level value. The data setting method of a nonvolatile memory device. The method of claim 4, wherein the outputting of the data setting signal comprises outputting a high level second data setting signal while the operation state signal and the second data setting control signal simultaneously have a high level value. A data setting method of a nonvolatile memory device. The method of claim 1, wherein applying the first data to the specific node comprises applying a low-level sensing node precharge signal during a period in which the data setting signal is at a high level to apply a ground voltage to a specific node of the register. And setting the data of the nonvolatile memory device. The method of claim 5, wherein applying the first data to the specific node comprises applying a low level sense node precharge signal during a period in which the first data setting signal is at a high level, thereby providing a ground voltage to the first node of the register. And applying the data to the data of the nonvolatile memory device. The method of claim 6, wherein the applying of the first data to the specific node comprises applying a low level sense node precharge signal to the second node of the register during a period in which the second data setting signal is at a high level. And applying the data to the data of the nonvolatile memory device. 4. The data setting method of claim 3, wherein the first data setting unit comprises an AND gate that receives the operation state signal and the first data setting control signal. The data setting method of claim 4, wherein the second data setting unit includes an AND gate that receives the operation state signal and the second data setting control signal.

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