KR20080038936A - Erasing method of non-volatile memory device - Google Patents

Abstract

An erase method of a non-volatile memory device is provided to erase all blocks without inputting an address signal by inputting a total erase command signal at one time. According to an erase method of a non-volatile memory device, a total erase command signal to erase all memory cell blocks included in a memory cell array is inputted(S210). A row address to select a first memory cell block according to the total erase command signal is generated(S240). Erase operation to erase a memory cell block selected by the row address is performed(S250). The erased memory cell block is judged to be the last memory cell block, and the row address signal is changed to select a next memory cell block if the erased memory cell block is not the last memory cell block(S270). The step of performing the erase operation and the step of changing the row address are repeated until the last memory cell block is erased.

Description

Erasing method of non-volatile memory device

1 is a block diagram of a nonvolatile memory device according to an embodiment of the present invention.

2 is a flowchart illustrating an erase method of a nonvolatile memory device according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: nonvolatile memory device 110: input buffer

120: control logic circuit 130: high voltage generator

140: X-decoder 150: Y-decoder

160: memory cell array 170: page buffer unit

180: data input / output circuit

The present invention relates to a method of erasing a nonvolatile memory device, and more particularly, to a method of erasing a nonvolatile memory device applicable to a flash memory device.

A nonvolatile memory device is a memory device in which stored data is not erased even when a power supply is interrupted. Among these nonvolatile memory devices, a flash memory device corresponds to a representative nonvolatile memory device. The flash memory device stores or outputs data through a program operation, a read operation, and an erase operation. Here, the erasing operation is performed to delete the stored data. Such a flash memory device may be classified into a NAND flash memory device of a NOR flash memory device, and an erase operation of the NAND flash memory device will be described as an example.

The memory cell array of the NAND type flash memory device includes a plurality of blocks. Each block includes a plurality of memory cells, and the plurality of cells are connected in units of pages. Since the cell array structure of the NAND type flash memory device is already known, a detailed description thereof will be omitted. Meanwhile, operations of the NAND type flash memory device include a program operation, an erase operation, and a read operation. Here, the program operation and the read operation are performed in units of pages, and the erase operation is performed in units of blocks. Specifically, when the erase command signal is input followed by the address signal, the erase operation of the block corresponding to the address signal is performed. Since the erase operation is performed in units of blocks, in order to erase a plurality of blocks or erase all blocks, the erase command signal and the address for selecting the next block are reset whenever the erase operation of the block selected by the address signal is completed. It must be entered.

In contrast, the erase method of the nonvolatile memory device according to the present invention implements a control logic circuit to recognize an entire erase command signal for performing an erase operation on all blocks from the outside, and controls the input of the erase erase signal. An erase command signal and an address signal for selecting the first block are generated from the logic circuit to perform an erase operation, and each time the erase operation of the selected block is completed, the address signal is increased to perform the erase operation to the last block. With the input of the entire erase command signal, all blocks can be erased without input of the address signal.

According to an embodiment of the present invention, an erase method of a nonvolatile memory device includes inputting an entire erase command signal for erasing all memory cell blocks included in a memory cell array, and a first memory cell block according to the entire erase command signal. Generating a row address for selecting a memory cell, performing an erase operation for erasing the memory cell block selected by the row address, and determining whether the erased memory cell block is the last memory cell block, Changing the row address signal so that the next memory cell block is selected if not the block, and repeating the erase operation and the row address changing step until the last memory cell block is erased.

The method may further include inputting a dummy address signal after the entire erase command signal is input. The dummy address signal is input for three cycles. Before generating the row address signal, the method may further include inputting an erase confirmation command signal. The erase command signal is output together with the row address signal.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

1 is a block diagram of a nonvolatile memory device according to an embodiment of the present invention. The nonvolatile memory device 100 includes an input buffer 110, a control logic circuit 120, a high voltage generator 130, an X-decoder 140, a Y-decoder 150, a memory cell array 160, and a page buffer. The unit 170 and the data input / output circuit 180 are included. In the above, the memory cell array 160 includes a plurality of memory cell blocks. The input buffer 110 outputs the external address signal ADD, the command signal CMD, or the entire erase command signal ABD to the control logic circuit 120.

The control logic circuit 120 responds to the chip enable signal CEb and the control signals REb, WEb, ALE, and CLE to the command signal CMD, the external address signal ADD, or the entire erase command signal ABD. ). The control logic circuit 120 internally generates one of a program command PGM, a read command READ, and an erase command ERS in response to the command signal CMD. In addition, the control logic circuit 120 outputs the row address signal RADD and the column address signal CADD according to the external address signal ADD. In addition, when the entire erase command signal ABD is input, the control logic circuit 120 may be the first of the memory cell blocks included in the memory cell array together with the erase command signal ERS regardless of the external address signal ADD. The row address signal RADD for selecting the memory cell block is output. In addition, when the erase operation of the memory cell block selected by the row address signal RADD is completed, the control logic circuit 120 increases the row address signal RADD to select the next memory cell block. The row address signal RADD is incremented each time the erase operation is completed until it is selected.

The high voltage generator 130 outputs bias voltages VD, VS, VW1 to VWK (K is an integer) in response to one of the program command PGM, the read command READ, and the erase command ERS. Voltage VD is a drain voltage to be supplied to a drain select line (not shown), voltage VS is a source voltage to be supplied to a source select line (not shown), and voltages VW1 to VWK are word lines (not shown). Are the word line voltages to be supplied respectively. The X-decoder 140 outputs a block select signal BSEL for selecting one of a plurality of memory cell blocks according to the row address signal RADD, and the switching unit 145 outputs a drain voltage according to the block select signal. VD), the source voltage VS, and the word line voltages VW1 to VWK (K is an integer) to the selected memory cell block. The Y-decoder 150 decodes the column address signal CADD to generate the column decoding signal CDEC, and outputs the column decoding signal CDEC to the page buffer unit 170. The page buffer unit 170 transfers the input data Di input through the input / output circuit 160 to the bit lines (not shown) of the memory cell array 160 according to the column decoding signal CDEC during the program operation. In the read operation, data transferred from the memory cell block through the bit lines is transferred to the input / output circuit 160. Unexplained reference numeral Do is output data.

The erasing method of the nonvolatile memory device described above will be described below. 2 is a flowchart illustrating an erase method of a nonvolatile memory device according to an exemplary embodiment of the present invention.

1 and 2, when all memory cell blocks included in the memory cell array 160 are erased from the outside, the entire erase command signal ABE is transmitted to the control logic circuit 120 through the input buffer 110. Next, a dummy address is input. (S220) In general, when a command signal CMD related to an erase operation is input, an external address ADD is input to designate an erase target memory cell block. However, in the entire erase operation of the memory cell block, all the memory cell blocks are erased so that the external address ADD is not used. Therefore, the external address does not have to be input. However, unlike an ordinary erase operation, if an erase confirm command signal is input immediately without an external address, it may be difficult to synchronize an operation with peripheral circuits. Therefore, even when the address signal ADD is not input to match the operation timing as in the normal erase operation, it may affect the waiting for the time required to input the address signal ADD (for example, 3 cycles) or the selection of the memory cell block. A dummy address that is not provided is input (S220). If there is no problem in synchronizing the operation with the peripheral circuits, the input step S220 of the dummy address may be omitted.

Subsequently, an erase confirm command signal indicating that all inputs of the signal required for the erase operation is completed is input to the control logic circuit 120 through the input buffer 110 (S230). The control logic circuit 120 outputs the row address signal RADD for selecting the first memory cell block among the memory cell blocks included in the memory cell array 160 together with the erase command signal ERS. In operation S240, an erase operation is performed according to the row address signal RADD and the erase command signal ERS. In detail, in operation S250, the high voltage generator 130 may drain a drain required for the erase operation according to the erase command signal ERS. The voltage VD, the source voltage VS, and the word line voltages VW1 to VWK (K is an integer) are generated and output to the switching unit 145. The X-decoder 140 generates a block select signal BSEL for selecting the first memory cell block according to the row address signal RADD, and the switching unit 145 generates a drain voltage according to the block select signal BSEL. VD, the source voltage VS, and the word line voltages VW1 to VWK (K is an integer) are transferred to the first memory cell block. The first memory cell block is erased according to the drain voltage VD, the source voltage VS, and the word line voltages VW1 to VWK (K is an integer) applied through the switching unit 145.

When the erase operation of the selected memory cell block is completed according to the row address signal RADD, it is determined whether the erased memory cell block corresponds to the last cell block. (S260) If the erased memory cell block is not the last cell block, The control logic circuit 120 increments the row address signal RADD so that the next memory cell block is selected (S270). In this case, the control logic circuit 120 performs the next memory when the erased memory cell block is not the last cell block. The row address signal RADD for selecting a cell block is automatically generated. Therefore, the erase command signal or address signal for selecting and erasing the next memory cell block does not need to be input again from the outside. After the row address signal RADD is increased, the erase operation step S250 is performed again according to the increased row address signal RADD. The erase operation step S250 and the address increase step S270 are repeatedly performed until the erase operation of the last memory cell block is completed. When the erase operation of the last memory cell block is completed, the erase operation of the entire memory cell block is completed.

As described above, the present invention implements a control logic circuit to externally recognize the entire erase command signal for performing an erase operation on all blocks, and the first and second erase command signals from the control logic circuit when the entire erase command signal is input. By generating an address signal for selecting the first block and performing an erase operation, each time the erase operation of the selected block is completed, the address signal is incremented and the erase operation is performed until the last block. All blocks can be erased without input.

Claims (5)

Inputting an entire erase command signal for erasing all memory cell blocks included in the memory cell array; Generating a row address for selecting a first memory cell block according to the entire erase command signal; Performing an erase operation to erase the memory cell block selected by the row address; And Determining whether the erased memory cell block is the last memory cell block, and changing the row address signal to select the next memory cell block if not the last memory cell block, And performing the erase operation and the row address signal changing step until the last memory cell block is erased. The method of claim 1, wherein after the entire erase command signal is input, And a dummy address signal is inputted to the erase method of the nonvolatile memory device. The method of claim 2, And the dummy address signal is input for three cycles. The method of claim 2, wherein before generating the row address signal, And erasing an erase confirmation command signal. The method of claim 1, And an erase command signal are output together with the row address signal.

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