KR100628443B1 - Liquid crystal display and method for driving the same - Google Patents

Abstract

The present invention is to minimize the difference in the charging level (charging level) between each pixel by inverting the polarity of the gradation voltage for each pixel unit consisting of three pixel electrodes and one pixel unit consisting of red, green, and blue color filters. The LCD panel is driven by a pixel unit inversion method by applying a high level select signal to an exclusive or circuit formed in a buffer among the drive ICs, and inverting the reverse signal to a low level and a high level every one or two gate lines. Let's do it.

As a result, power consumption is reduced, flicker is reduced to 1/3, and driving frequency is lowered compared to sync bank dot inversion, thereby minimizing interference and noise of electromagnetic waves.

In addition, when the pixel dot inversion is performed, the difference in charging level between the pixel units is almost the same as compared to the dual bank dot inversion, so that generation of streaks toward the gate line direction and color change can be prevented, thereby improving image quality.

Description

Liquid crystal display and method for driving the same

1 is a conceptual diagram showing a sync bank dot inversion in a conventional LCD panel.

2 is a conceptual diagram illustrating dual bank dot inversion in a conventional LCD panel.

3 is a block diagram for explaining driving of a liquid crystal display device according to the present invention;

4 is a perspective view showing the structure of a display unit according to the present invention;

5 is a detailed block diagram of a source drive IC according to the present invention.

Fig. 6 is a block diagram showing a buffer structure of a source drive IC according to the first embodiment of the present invention.

7 is a block diagram showing a buffer structure of a source drive IC according to a second embodiment of the present invention.

FIG. 8 is a table showing polarities of gray voltages output from each switch to data lines in response to input of a select signal and a reverse signal; FIG.

9 and 10 are conceptual views illustrating pixel unit inversion in an LCD panel according to the present invention;

The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to inverts the polarity of grayscale voltages at intervals of one pixel unit including three pixel electrodes and red, green, and blue color filters. A liquid crystal display and a driving method thereof having improved image quality by minimizing a difference in charging level.

As shown in FIG. 1 or 2, a general liquid crystal display device includes gate lines 10 for transmitting a driving signal, a data line 20 for transmitting an image signal, and an image applied to the data line 20 according to the driving signal. The lower substrate 1 including the thin film transistors 30 for transmitting a signal to the pixel electrode 35 and the lower substrate 1 are attached to face the lower substrate, and the counter electrode is red, green, and blue (hereinafter, referred to as “RGB”). An apparatus including an upper substrate on which a color filter is formed, and a liquid crystal injected between the lower substrate and the upper substrate, the information being displayed by using the electro-optical properties of the liquid crystal injected therein.

When the gray voltages of the same polarity are continuously applied to the pixel electrodes of the liquid crystal display device, ionic impurities in the liquid crystal material are precipitated due to the characteristics of the liquid crystal, thereby causing an electrochemical change in the pixel electrode and the counter electrode, resulting in a decrease in luminance. Afterimages remain.

To prevent this, the polarity of the gradation voltage applied to the pixel electrode is inverted periodically. The inversion is divided into a frame inversion, a line inversion, and a dot inversion according to the period of inversion. .

Frame inversion is used to invert polarity every frame. It was mainly used in the early stages, but it is rarely used at present because of a high possibility of flicker.

In addition, line inversion inverts polarity at each gate line, and line inversion causes signal distortion and crosstalk in adjacent pixel electrodes due to an increase in resistance and capacitance when the LCD panel is enlarged. There is a disadvantage in that the image quality is reduced.

On the other hand, dot inversion inverts the polarity differently with the pixel electrode as a cycle, and has an advantage of easily suppressing flicker and afterimages compared to frame inversion and line inversion.

This dot inversion is divided into sync bank dot inversion and dual bank dot inversion. The sync bank dot inversion is along the gate line 10 (hereinafter referred to as "row direction") and data line as shown in FIG. Along the pixel 20 (hereinafter, referred to as "column direction"), the polarity of the gradation voltage is reversed with one pixel electrode 35 as a cycle.

However, when the liquid crystal display is driven in such a sync bank dot inversion method, power consumption is increased and driving frequency is increased due to frequent switching operations, thereby causing problems such as electromagnetic interference or noise.

In order to solve this problem, a dual bank dot inversion method has been developed. For example, as shown in FIG. 2, the dual bank dot inversion reverses the polarity of the gray scale voltage with one pixel electrode 35 in the row direction. Inverting the polarity of the gray voltages in cycles of the two pixel electrodes 35 in the column direction has the advantage of reducing power consumption and driving frequency than the sync bank dot inversion method.

However, in the case of the dual bank dot inversion, the gray voltage of the pixel electrode is distorted due to the parasitic capacitance between the data line and the pixel electrode, which is used to charge the parasitic capacitor in the polarity of the gate line with the parasitic capacitor. Due to the different levels, the amount of distortion of the gradation voltage of the pixel electrode is also changed.

As a result, streaks are generated along the horizontal direction of the LCD panel, that is, the gate lines, and the color to be displayed is discolored, thereby degrading the image quality.

Accordingly, an object of the present invention has been devised in view of the above-described problems, and is intended to prevent the occurrence of discoloration, streaks or flickering by inverting the polarity every one pixel unit.

Other objects of the present invention will become more apparent from the following detailed description and the accompanying drawings.

In order to achieve the above object, the source drive IC of the present invention shifts and stores RGB data transferred from a controller, and converts RGB data output from the shift resist into a gray scale voltage corresponding to an encoding value. And a buffer for selecting a polarity of the gray voltages output from the digital / analog converter and the digital / analog converter and applying a source signal to the LCD panel so that the polarity of the gray voltages is inverted every one pixel unit.

For example, the buffer may be electrically connected to the LCD panel and the plurality of buffer units in which a pair of the positive buffer to which the positive gray voltage is applied and the negative buffer to which the negative gray voltage is applied are paired, and the level of the reverse signal. And a source signal connected to any one of an output terminal of the positive and negative buffers, and a source signal applied to the LCD panel, and alternately connected to the output terminals of the positive and negative buffers at intervals of the three buffer units. A liquid crystal display device comprising two switches.

As another example, the buffer may include a plurality of buffer units including a pair of a positive buffer to which a positive gray voltage is applied and a negative buffer to which a negative gray voltage is applied, and one of a pixel unit inversion method and a dot inversion method from a controller. According to the output signal and the reverse signal output from the exclusive OR circuit and the exclusive OR circuit to which the select signal for selecting one method and the reverse signal for selecting the polarity of the gray scale voltage are input, the positive and negative buffers It is composed of a plurality of switches connected to any one of the output terminals and applying a source signal to the LCD panel.

Preferably, the switches are alternately connected to the output terminals of the positive and negative buffers at intervals of one buffer unit in an initial state, and the outputs of the buffer units to which the gray voltages corresponding to the R data and the B data are respectively input. The switches to be selected are electrically connected to the reverse signal line, and the switches connected to the output terminals of the buffer units to which the gray voltage corresponding to the green data of the switches are input are connected to the output line of the exclusive or circuit.

Also, when a low level select signal is input to the exclusive or circuit, the LCD panel is driven by a dot inversion method in which the polarity of the gray voltage is inverted at one pixel electrode.

When a high level select signal is input to the exclusive or circuit, the LCD panel includes one pixel unit including three pixel electrodes corresponding to the red, green, and blue color filters, and the red, green, and blue color filters. The polarity of the gradation voltage is reversed every cycle.

Hereinafter, the structure of the liquid crystal display according to the present invention will be described with reference to FIGS. 3 to 8.

In the driving system of the liquid crystal display 100 shown in FIG. 3, predetermined data and control signals are input to the controller 110, and DC power is supplied to the power supply unit 120. When DC power is applied to the power supply unit 120, the power supply unit 120 supplies a constant voltage necessary for the operation of the controller 110, the gray scale generator 130, and the gate voltage generator 140.

Here, the controller 110 outputs various control signals and data for determining the gray level for each pixel to the source drive part 220 electrically connected to the LCD panel 160, and also controls the gate drive part 210. Configured to output signals.

In addition, the gray voltage generator 140 is configured to supply a gray voltage to the source drive part 220, and the gate voltage generator 140 supplies a voltage for generating turn-on / turn-off voltage to the gate drive part 210. Supply.

The gate and source drive parts 210 and 220 electrically connected to the LCD panel 250 generate a source signal and a gate signal and apply the generated source signal to the LCD panel 250.

Here, the LCD panel 250 is injected between the lower substrate 260, the upper substrate 290 attached to the lower substrate, and the lower substrate 260 and the upper substrate 290 as a sealing material as shown in FIG. 4. It consists of a sealed liquid crystal (not shown).

As shown in FIGS. 4 and 8, the plurality of data lines 270 and the gate lines 280 vertically cross each other on one surface of the lower substrate 260, and the data lines 270 and the gate lines ( Each of the thin film transistors 273 is formed at an intersection point of the 280, and pixel electrodes 275 are formed in the intersection area, and the pixel electrodes 275 are arranged in a matrix form.

Meanwhile, a black matrix (not shown) is formed on one surface of the upper substrate 290 facing the lower substrate 260 to correspond to the data lines 270 and the gate lines 280, and correspond to the pixel electrodes 275. Red, green, and blue color filter patterns (not shown) are formed on the portion, and a common electrode (not shown) is formed on the entire surface of the upper substrate 290 on which the black matrix and the color filter pattern are formed.

Here, three pixel electrodes 275 adjacent to each other and color filters of different colors corresponding to the three pixel electrodes 275, that is, red, green, and blue color filters are referred to as pixel units 276.

The gate and source drive parts 210 and 220 may include a plurality of gates electrically connecting the LCD panel 250 to the printed circuit boards 150 and 160 having various signal transmission lines formed thereon and mounted with components such as a controller and the like. Source driver dry ICs 210 and 220.

Here, a shift resist 223, a digital-to-analog converter 225, and a buffer 230 are formed inside each source drive IC 220 according to the present invention.

The shift resist 223 latches the RGB data transmitted from the controller according to the rising time of the horizontal clock signal, and then continuously shifts and stores the RGB data, and the digital / analog converter 225 transmits the shift resist. The RGB data is converted into a gray voltage corresponding to an encoding value, and the buffer 230 selects the polarity of the gray voltage output from the digital / analog converter 225 and adjusts the gray voltage to apply to the LCD panel 250.

The buffer 230 according to the first embodiment of the present invention selects an output such that the polarity of the gray voltage is inverted at intervals of one pixel unit 276 including three pixel electrodes 275 and an RGB color filter. It is for applying to the panel 250.

As shown in FIG. 6, the buffer 230 which inverts polarity with the pixel unit 276 as shown in FIG. 6 includes the positive buffer 231 and the negative gray scale having the negative gray voltage applied thereto. A negative buffer 233 to which a voltage is applied is connected to a buffer unit forming a pair, and a reverse signal line and a reverse signal line 239 to which a reverse signal for selecting a polarity of a gray voltage is input, according to a reverse signal. The switch 240 selects one of the positive buffer 231 and the negative buffer 233.

In addition, one buffer unit and a switch 240 are connected to one data line 270, and the polarities of the positive buffer 231 and the negative buffer 233 connected to one data line 270 are different from each other. The same gradation voltage is input to each level.

For convenience of description, in FIG. 6, six buffer units and six switches will be described as examples, and in FIG. 9, six data lines respectively connected to the six switches will be described.

In FIG. 6, the first, second, third, fourth, fifth, and sixth switches 241, 242, 243, 244, 245, and 246 are referred to as the sixth switches 241, 242, 243, 244, 245, and 246 from the outermost side. And D5 and D6 respectively.

Meanwhile, each switch 240 is initially set to a high level reverse signal so that the first, second and third switches 241, 242, 243 are initially configured with the positive buffers 231a, 231b, The fourth, fifth and sixth switches 244, 245 and 246 are initially connected to the output side of the negative buffers 233d, 233e and 233f.

The operation of the source drive IC according to the first embodiment configured as described above is as follows.

When the shift signal STH is input to the shift resist 223, the shift resist 223 simultaneously inputs the RGB data output from the controller 110 to latch the RGB data at the rising time of the horizontal clock signal H_CLK. After the latched RGB data is shifted and stored continuously, when the RGB data is completely filled in the first source drive IC, a carry out signal is transmitted to the next source drive IC.

If all of the data is filled in the plurality of source drive ICs 220 through this process, when the load signal TP input to the shift resist 223 rises, all the RGB data stored in the shift resist 223 are digitally collected at once. Output to the analog converter 225.

On the other hand, the digital / analog converter 225 inputs the RGB data output from the shift resist 223 to convert the RGB data into a gray voltage corresponding to an encoding value to load the signal TP input to the digital / analog converter 225. Outputs to the buffer 230 when is polled.

At this time, gray level voltages having the same polarity but different levels are input to the pair of positive buffer 231 and the negative buffer 233, respectively.

As described above, when the gray voltage output from the digital / analog converter 225 is applied to each of the positive buffers 231 and the negative buffers 233, the positive buffers 231 and the negative buffers ( A reverse signal for selecting a polarity for each grayscale voltage input to 233 is input to the reverse signal line 239.

Here, when the low level reverse signal is input to the reverse signal line 239, the switches 240 that are initially set to the high level reverse signal and maintain the initial setting state as shown in FIG. 6 operate to be opposite to the initial setting state. do.

That is, the first, second, and third switches 241, 242, 243, which are connected to the output terminals of the positive buffers 231a, 231b, and 231c, are connected to the output terminals of the negative buffers 233a, 233b, and 233c. The fourth, fifth and sixth switches 244, 245 and 246, which were initially connected to the output terminals of the negative buffers 233d, 233e and 233f, are connected to the output terminals 231d, 231e and 231f of the positive buffers.

Therefore, when the low level reverse signal is input to the reverse signal line 239, the negative gray voltage is applied to the data lines of D1, D2, and D3, and the positive gray voltage is applied to the data lines of D4, D5, and D6. .

When the high level reverse signal is input to the reverse signal line 239, the switches 240 maintain the initial setting state.

That is, the first, second, and third switches 241, 242, 243 are directly connected to the output terminals of the positive buffers 231a, 231b, and 231c to output positive grayscale voltages. The switches 244, 245, and 246 are directly connected to output terminals of the negative buffers 233d, 233e, and 233f to output the negative gray voltage.

Therefore, when the low level reverse signal is input to the reverse signal line 239, the positive gray scale voltage is applied to the data lines of D1, D2, and D3, and the negative gray scale voltage is applied to the data lines of D4, D5, and D6. .

The switch alternates between the positive and negative buffers at the three buffer sections, and converts the reverse signal into a low level and a high level by applying one gate line (G1, G2, G3, G4) to the connected buffer. In this case, as shown in FIG. 9, the polarity of the gray voltage is inverted by three pixel electrodes 275 in the row direction, and the polarity is inverted by one pixel electrode 275 in the column direction. Driven by the pixel unit inversion.

On the other hand, the buffer 230 according to the second embodiment of the present invention may select the output so that the polarity of the gray voltage is inverted at the pixel electrode 275 cycle, one pixel unit (3 pixel electrode 275) The output may be selected and applied to the LCD panel 250 so that the polarity of the gray voltage is inverted at intervals 276.

As shown in FIG. 7, the buffer 230 selectively performing dot inversion and pixel unit inversion has a positive buffer 231 and a negative gray level to which a positive gray voltage is applied. Exclusive OR to which a negative buffer 233 to which a voltage is applied, a select signal for selecting dot inversion or pixel unit inversion, and a reverse signal for selecting the polarity of the gradation voltage are input. OR) is connected to the output line 237 and the reverse signal line 239 of the circuit 235 and the exclusive or circuit 235 to select the output of any one of the positive buffer 231 and the negative buffer 233 It is composed of a switch 240.

Here, when the select signal and the reverse signal of the same level are input to the input side of the exclusive or circuit 235, the exclusive or circuit 235 outputs a low level signal, and the select signal and the reverse of the different levels are selected. When a signal is input, a high level signal is output.

Meanwhile, one positive buffer 231, a negative buffer 233, and a switch 240 are connected to one data line 270, and a positive buffer 231 connected to one data line 270. A gray voltage having different polarities but the same level is respectively input to the negative buffer 233.

The switches 241, 243, 244 and 246 for selecting the outputs of the positive buffers 231a and 231c and the negative buffers 233a and 233c to which the gray voltages corresponding to the R data and the B data are applied are included in the exclusive or circuit 235. The switches 242 and 245 connected to the output line 237 of the output terminal 237b and the output terminals of the negative buffer 231b and the negative buffer 233b to which the gray voltage corresponding to the G data is applied are connected to the reverse signal line 239. do.

Hereinafter, for convenience of description, FIG. 7 illustrates six pairs of positive and negative buffers and switches, and FIG. 9 illustrates six data lines respectively connected to six switches.

In FIG. 7, the switches for selecting the polarity of the gray scale voltage corresponding to the R and B data are referred to as first, third, fourth, and sixth switches 241, 243, 244, 246, and these switches 241, 243, 244, 246 are referred to as data lines D1, It is connected to D3, D4 and D6.

The switches for selecting the polarity of the gray scale voltage corresponding to the G data are referred to as second and fifth switches 242 and 245, which are connected to the data lines D2 and D5 in FIG. 9.

 The operation of the source drive IC configured as described above will be described below.

When the shift signal STH is input to the shift resist 223, the shift resist 223 simultaneously inputs the RGB data output from the controller 110 to latch the RGB data at the rising time of the horizontal clock signal H_CLK. After that, the latched RGB data is shifted and stored continuously. When the RGB data is completely filled in the first source drive IC, a carry out signal is transmitted to the next source drive IC.

If all of the data is filled in the plurality of source drive ICs 220 through this process, when the load signal TP input to the shift resist 223 rises, all the RGB data stored in the shift resist 223 are digitally collected at once. Output to the analog converter 225.

On the other hand, the digital / analog converter 225 inputs the RGB data output from the shift resist 223 to convert the RGB data into a gray voltage corresponding to an encoding value to load the signal TP input to the digital / analog converter 225. Outputs to the buffer 230 when is polled.

At this time, gray level voltages having the same polarity but different levels are input to the pair of positive buffer 231 and the negative buffer 233, respectively.

As described above, when the gray scale voltage output from the digital / analog converter 225 is applied to each of the positive buffers 231 and the negative buffers 233, the exclusive or circuit 235 has a sink bank dot inversion. Alternatively, a select signal for selecting pixel unit inversion and a reverse signal for selecting polarity for each gray voltage are input, and a reverse signal is input to the reverse signal line 239.

Here, as shown in FIG. 8, when a low level select signal is input to the exclusive or circuit 235, the LCD panel 200 does not change the level of the reverse signal as shown in FIG. 1. When the sink bank dot inversion for inverting the polarity of the gray voltage is performed at intervals of two pixel electrodes 275, and a high level select signal is input to the exclusive or circuit 235, the LCD panel 200 illustrated in FIG. 9. As described above, pixel unit inversion for inverting polarity is performed every one pixel unit 276.

First, as shown in FIG. 8, when a low level select signal and a low level reverse signal are input to the buffer 230, a signal initially output at a high level from the exclusive or circuit 235 may be used. The switches 240 that are set to the high level reverse signal and maintain the initial setting state as shown in FIG. 7 operate to be opposite to the initial setting state.

That is, in FIG. 7, the second switch 242 of the two switches connected to the output line 237 of the exclusive or circuit 235 is connected to the output terminal of the negative buffer 233b to be connected to the data line of D2. The gray level voltage of the polarity is applied, and the fifth switch 245 is connected to the output terminal of the positive buffer 231e to apply the positive gray level voltage to the D5 data line.

In addition, the first, third, fourth, and sixth switches 241, 213, 244, and 246 connected to the reverse signal line 239 also operate to be opposite to the initial setting state. The first switch 241 and the third switch 243, which are connected to the output terminal of 231c, are connected to the output terminals of the negative buffers 231a and 231c by a low level reverse signal, thereby connecting to the data lines of D1 and D3. The gray scale voltage of polarity is applied.

In addition, the fourth switch 244 and the sixth switch 246, which are connected to the output terminals of the negative buffers 233d and 233f in the initial setting state, are output terminals of the positive buffers 231d and 231f by the low level reverse signal. Since it is connected to, the positive gray-level voltage is applied to the data lines of D4 and D6.

Second, as shown in FIG. 8, when the low level select signal and the high level reverse signal are respectively input to the buffer, the high level signal is input to each of the switches 240, so that the respective switches 240 may be used. Will remain at the initial setting.

That is, in FIG. 7, the second switch 242 of the two switches connected to the output line 237 of the exclusive or circuit 235 is connected to the output terminal of the negative buffer 233b to be connected to the data line of D2. The gray level voltage of the polarity is applied, and the fifth switch 245 is connected to the output terminal of the positive buffer 231e to apply the positive gray level voltage to the D5 data line.

In addition, in FIG. 7, among the switches connected to the reverse signal line, the first switch 241 and the third switch 243 are connected to the output terminals of the positive buffers 231a and 231c so that the negative gray voltage is applied to the data lines of D1 and D3. The fourth switch 244 and the sixth switch 246 are connected to the output terminals of the negative buffers 233d and 233f so that the negative gray voltage is applied to the data lines of D4 and D6.

Here, as described in the first and the second, the select signal is fixed at the low level and input to the exclusive OR circuit 235, and the reverse signal is performed at one gate line G1, G2, G3, G4 ... Is converted into a low level and a high level and applied to the exclusive or circuit 235 and the reverse signal line 239, respectively, in the LCD panel 200, as shown in FIG. 1, one pixel in the row direction and the column direction. The cycle of the sink bank dots in which the polarity of the gray voltage is inverted is performed at the electrode 35.

The select signal is fixed at a low level and input to the exclusive OR circuit 235, and the reverse signal is converted into a low level and a high level at two gate lines G1, G2, G3, and G4 .... When applied to the exclusive or circuit 235 and the reverse signal line 239, respectively, in the LCD panel 200, as shown in FIG. 1, the polarity of the gradation voltage is changed by one pixel electrode 35 in the row direction. The dual bank dot inversion is performed in which the polarity of the gray voltage is inverted by two pixel electrodes in the column direction.

As described above, the sync bank dot inversion has a high frequency used to generate electromagnetic interference and noise, and the polarity of the gray voltage is continuously inverted with one pixel electrode, thereby increasing power consumption. As the silver color changes and streaks occur, in the present invention, the LCD panel is driven by a pixel unit inversion in which polarities are inverted every three pixel electrodes in order to reduce frequency and power consumption while improving image quality.

In order to perform the pixel unit inversion, the high level select signal may be applied to the buffer 230 instead of the low level select signal.

Third, as shown in FIG. 8, when the high level select signal and the low level reverse signal are respectively input to the buffer 230, the output line of the exclusive or circuit 235 among the switches 240. Since the high level signal is input to the switches 240 connected to 237, the initial setting state is maintained as it is, and a low level signal is input to the switches 240 connected to the reverse signal line 239 among the switches. It is operated to be opposite to the initial setting state.

In detail, in FIG. 7, the second switch 242 of the two switches connected to the output line 237 of the exclusive or circuit 235 is directly connected to the output terminal of the negative buffer 233b. The five switch 245 is connected to the output terminal of the positive buffer 231e.

In addition, in FIG. 7, since the switches 240 connected to the reverse signal line 239 are operated to be opposite to the initial setting state, the first switch 241 and the third switch 243 are the negative buffers 233a and 233c. The fourth switch 244 and the sixth switch 246 are connected to the output terminals of the positive buffers 231d and 231f.

Therefore, when the high level select signal and the low level reverse signal are input to the buffer 230, a negative gray voltage is applied to the data lines of D1, D2, and D3, and a positive polarity voltage is applied to the data lines of D4, D5, and D6. The gradation voltage is applied.

Fourth, when a high level select signal and a reverse signal are input to the buffer 230 as shown in FIG. 8, the output line 237 of the exclusive or circuit 235 among the switches 240 is provided. Since the low level signal is input to the connected switches 240, the switch operates in the opposite direction to the initial setting state. The high setting signal is input to the remaining switches 240 connected to the reverse signal line 239. Keep it.

That is, in FIG. 7, the second switch 242 connected to the output terminal of the negative buffer 233b of the two switches connected to the output line of the exclusive or circuit 235 is connected to the positive buffer 231b. The fifth switch 245 connected to the output terminal and connected to the output terminal of the positive buffer 231e is connected to the output terminal of the negative buffer 233e.

In addition, in FIG. 7, since the switches 240 connected to the reverse signal line 239 maintain the initial setting state, the first switch 241 and the third switch 243 are intact in the positive buffers 231a and 231c. The fourth switch 244 and the sixth switch 246 are also connected to the output terminals of the negative buffers 233d and 233f as they are.

Therefore, when a high level select signal and a high level reverse signal are input to the buffer 230, a positive gray voltage is applied to the data lines of D1, D2, and D3, and a negative polarity voltage is applied to the data lines of D4, D5, and D6. The gradation voltage is applied.

When the pixel unit is inverted in the third and fourth sync bank methods, the select signal is fixed at a high level and input to the exclusive OR circuit 235, and one gate line G1, G2, G3, and G4 is provided. The reverse signal is converted into a low level and a high level at a period of time, and is applied to the exclusive OR circuit 235 and the reverse signal line 239, respectively. Then, as illustrated in FIG. 9, the LCD panel 200 inverts the polarity of the gray scale voltage by three pixel electrodes 275 in the row direction and inverts the polarity of one pixel electrode 275 in the column direction. Driven by pixel unit inversion.

Alternatively, when inverting the pixel unit with the third and fourth dual bank inversions, the select signal is fixed to a high level and input to the exclusive OR circuit 235, and two gate lines G1 and G2 (G3) are provided. The reverse signal is converted into a low level and a high level at a period of G4 to be applied to the exclusive OR circuit 235 and the reverse signal line 239, respectively. Then, as illustrated in FIG. 10, in the LCD panel 200, the polarity of the gray voltage is inverted by three pixel electrodes 275 in the row direction, and the polarity is inverted by two pixel electrodes 275 in the column direction. do.

As such, when the level of the reverse signal is changed every two gate lines, less switching operation is required when the level of the reverse signal is changed every one gate line, thereby reducing power consumption and providing good performance against electromagnetic waves and noise. .

As described above, when the select signal input to the exclusive or circuit is fixed at a high level, and the reverse signal is inverted to a low level and a high level at intervals of one or two gate lines, a sink bank is performed. Compared to dot inversion, power consumption is reduced, flicker is reduced to 1/3, and driving frequency is lowered, thereby minimizing electromagnetic interference and noise.

In addition, when the pixel dot inversion is performed, the difference in charging level between the pixel units is almost the same as compared to the dual bank dot inversion, so that the generation of streaks toward the gate line direction and color change can be prevented, thereby improving the image quality of the LCD panel. .

Claims (13)

The controller, the gray scale generator and the gate voltage generator use source driving signals including RGB data, first control signals and gray voltage, and second control signals using power and information transmitted from a predetermined image signal source. Generating a gate driving signal including the gate on / off voltage and applying the gate driving signals to the respective source drive ICs and the gate drive ICs; The source driving drive ICs which input the source driving signal generate a source signal and latch the line one by one, and then the source latched at intervals of one pixel unit including three pixel electrodes and red, green, and blue color filters. Inverting the polarity of the signal and applying the signal to the LCD panel; Generating gate signals sequentially applying the gate driving signals to the LCD panel; And And the LCD panel displays predetermined information by the applied source signal and the gate signal. The pixel of claim 1, wherein the polarity of the source signal is inverted by one pixel unit in the row direction in which the source driving drive ICs are installed in the LCD panel, and one pixel in the column direction in which the gate driving drive IC is installed. And a polarity of the source signal is inverted at an interval of an electrode. 2. The pixel of claim 1, wherein the polarity of the source signal is reversed by one pixel unit in a row direction in the LCD panel in which the source driving drive ICs are installed, and two pixels are arranged in a column direction in which the gate driving drive ICs are installed. And a polarity of the source signal is inverted at an interval of an electrode. delete delete A power supply unit supplying a voltage required for each unit; A controller for outputting RGB data and first and second control signals to implement a predetermined screen; A gray scale generator which generates a plurality of gray scale voltages using the voltage applied from the power supply unit; A gate voltage generator configured to output a gate turn on / off voltage using a voltage applied from the power supply unit; Source drive ICs configured to input the RGB data, the first control signals, and the gray voltage to output a source signal; Gate drive ICs configured to output a gate signal by applying the second control signals and the gate turn on / off voltage; And An LCD panel displaying a predetermined screen by the source signal and the gate signal, The source drive ICs A shift register for shifting and storing the RGB data in synchronization with a horizontal clock signal included in the first control signals; A digital / analog converter for converting the RGB data output from the shift resist into a gradation voltage corresponding to an encoding value and outputting the gradation voltage; And And a buffer for applying a source signal to the LCD panel by inverting the polarity of the gray voltage output from the digital / analog converter by one pixel unit and adjusting the gray voltage. The method of claim 6, wherein the buffer A plurality of buffer units forming a pair of a positive buffer to which the positive gray voltage is applied and a negative buffer to which the negative gray voltage is applied; Electrically connected to the LCD panel and connected to one of an output terminal of the positive buffer and the negative buffer according to a level of a reverse signal to apply the source signal to the LCD panel, and periodically And a plurality of switches that are alternately connected to the positive buffers and the output terminals of the negative buffers. delete delete delete delete delete delete

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