KR100613378B1 - Capacitor in a semiconductor device and method of manufacturing the same - Google Patents

Abstract

It is an object of the present invention to provide a MIM structure capacitor of a semiconductor device capable of securing excellent barrier properties against copper diffusion while preventing capacitance change due to loss of a dielectric layer, and a method of manufacturing the same. To this end, in the present invention, the step of sequentially forming the lower electrode, the dielectric layer and the upper electrode of the second metal film of the first metal film on the semiconductor substrate, and selectively etching the upper electrode to leave a predetermined width, the lower portion of the upper electrode The present invention provides a method of manufacturing a capacitor of a semiconductor device, the method including etching a dielectric layer to a predetermined thickness to form a dielectric layer under the upper electrode as a protruding region, and forming a compensation layer on the upper electrode and the dielectric layer.

MIM, capacitor, dielectric layer, nitride film, compensation film

Description

Capacitor in semiconductor device and method of manufacturing the same

1 is a cross-sectional view showing a MIM capacitor of a conventional semiconductor device,

2A through 2E are cross-sectional views illustrating MIM capacitors of a semiconductor device according to example embodiments.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a thin film capacitor having a MIM structure and a method for manufacturing the same.

In general, semiconductor integrated circuits have a digital type in which the output signal is turned on / off by a change in the input signal according to a signal processing method, and an analog type in which the output signal is linearly changed by the input signal. Separated by.

These integrated circuits can store information depending on the presence or absence of charge accumulated in the capacitors, regardless of whether they are digital or analogue. Therefore, in order to maintain normal operating characteristics, these circuits have a capacitance change depending on voltage or temperature during device manufacturing. Capacitors should be manufactured so as not to change.

Accordingly, polysilicon-insulator-polysilicon (PIP) structures or metal-insulator-MIMs that do not depend on bias in the manufacture of semiconductor integrated circuits such as CMOS analog circuits. The capacitor is manufactured by the structure.

Among them, the MIM capacitor has a disadvantage that it is difficult to secure the capacitance per unit area much larger than that of the PIP structure, but the capacitance characteristics according to the voltage and temperature change are better than that of the PIP structure. To do this, the capacitor of the MIM structure is mainly applied.

A capacitor manufacturing method of such a MIM structure will be described with reference to FIG. 1.

Referring to FIG. 1, after forming the lower electrode 11 of the first metal film on the semiconductor substrate 10, forming the dielectric layer 12 on the lower electrode 11, and then forming the second electrode on the dielectric layer 12. An upper electrode 13 of the metal film is formed, and a nitride film 14 for controlling via hole etching is formed on the upper electrode 13.

Here, the first metal film is made of a copper film, and the second metal film is made of a titanium nitride film (TiN). The dielectric layer 12 is formed of a nitride film and also serves as a barrier for preventing diffusion of copper from the lower electrode 11. The lower electrode 11, the dielectric layer 12, and the upper electrode 13 form a capacitor 100 having a MIM structure.

Thereafter, the nitride film 14 and the upper electrode 13 are patterned to form a wiring line, and remain in a predetermined width.

Thereafter, the first lower wiring 16a of the copper film in contact with the upper electrode 13 and the lower electrode 11 while being insulated from each other by the first interlayer insulating film 15 by a known dual damascene process. ) And a second lower wiring 16b which is insulated by the first interlayer insulating film 15 and contacts the lower electrode 11 and has wiring holes.

Then, the contact portions are insulated from each other by the second interlayer insulating film 18 by the dual damascene process, thereby forming the upper wiring 20 of the copper film contacting the first and second lower wirings 16a and 16b. . At this time, a barrier to prevent diffusion of copper from the wirings 16a, 16b, and 20 between the first interlayer insulating film 15 and the second interlayer insulating film 18 and between the second interlayer insulating film 18 and the upper wiring 20. As a layer, the 1st barrier layer 17 and the 2nd barrier layer 19 which consist of a nitride film can respectively be interposed.

In order to form the upper electrode 13 in the above-described conventional MIM structure capacitor, a titanium nitride film and a nitride film are deposited on the dielectric layer 12 and the titanium nitride film and the nitride film are patterned by photolithography and etching processes.

However, when the titanium nitride film is etched, the loss of the dielectric layer 12, which is a lower layer, is severely generated, thereby causing a change in capacitance of the capacitor 100, and a barrier property that prevents diffusion of copper from the lower electrode 11 is lowered, thereby increasing wiring reliability. There is a problem of deterioration.

In order to solve this problem, it is necessary to increase the deposition thickness of the dielectric layer 12 of the nitride film in consideration of the loss during etching, but in this case, it is difficult to accurately determine the degree of the etching thickness that is lost.

 The present invention is to solve the conventional problems as described above, to provide a MIM capacitor of a semiconductor device and a method of manufacturing the same that can ensure excellent barrier properties against copper diffusion while preventing capacitance change due to the loss of the dielectric layer. There is a purpose.

In order to achieve the above object, the present invention provides a semiconductor substrate, a lower electrode of the first metal film formed on the substrate, a dielectric layer formed on the lower electrode and having a protruding region thicker than the periphery, and a protruding region of the dielectric layer. A capacitor of a semiconductor device including an upper electrode formed on the upper electrode and a compensation film formed on the upper electrode and the dielectric layer is provided.

In this case, the compensation film preferably has a thickness that is substantially the same height as the dielectric layer of the protruding region at the top of the dielectric layer having a thickness thinner than that of the protruding region.

The dielectric layer having a thickness thinner than that of the protruding region may be 1/2 of the thickness of the protruding region, for example, the dielectric layer of the protruding region may have a thickness of 500 to 1000 GPa, and the compensation layer may have a thickness of 250 to 500 GPa.

If the first metal film is made of a copper film and the second metal film is made of a titanium nitride film, the dielectric layer and the compensation film may be made of a nitride film.

In the present invention, the step of sequentially forming the lower electrode of the first metal film, the dielectric layer and the upper electrode of the second metal film on the semiconductor substrate, and selectively etching the upper electrode to leave a predetermined width, the lower portion of the upper electrode The present invention provides a method of manufacturing a capacitor of a semiconductor device, the method including etching a dielectric layer to a predetermined thickness to form a dielectric layer under the upper electrode as a protruding region, and forming a compensation layer on the upper electrode and the dielectric layer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

A method of manufacturing a MIM structure thin film capacitor according to an embodiment of the present invention will be described with reference to FIGS. 2A to 2E.

First, as shown in FIG. 2A, the lower electrode 51 of the first metal film is formed on the semiconductor substrate 50, and the plasma enhanced chemical vapor deposition of the dielectric layer 52 is performed on the lower electrode 51. Vapor Deposition (PECVD) to form a thickness of 500 to 1000 kPa. Here, the lower electrode 51 is made of a copper film, and the dielectric layer 32 is made of a nitride film, and the dielectric layer 32 also serves as a barrier to prevent diffusion of copper from the lower electrode 31.

Next, as shown in FIG. 2B, an upper electrode 53 is formed on the dielectric layer 52. As the upper electrode 52, a titanium nitride film may be formed to have a thickness of 500 to 1000 Å by PECVD.

Next, as shown in FIG. 2C, a photoresist pattern (not shown) is formed on the upper electrode 53 to expose a portion of the upper electrode by a photolithography process to form the wiring of the upper electrode 53. The exposed upper electrode 53 is etched and patterned using the photoresist pattern as a mask.

In the process of patterning the upper electrode 53, the lower dielectric layer 52 is etched together by about 250 to 500 microseconds, which is about 1/2 of the thickness of the entire dielectric layer 52.

Next, as illustrated in FIG. 2D, a compensation film 54 is deposited on the upper electrode 53 and the dielectric layer 52. In this case, the compensation layer 54 may be formed of a nitride layer and is deposited by the thickness of the dielectric layer 52 etched during the patterning of the upper electrode 53 to restore the thickness of the dielectric layer 52 to the initial (before etching). In this case, the thickness of the nitride film, which serves to prevent diffusion of copper on the upper portion of the lower electrode 51, can be maintained at the initial deposition thickness, thereby maintaining performance as a barrier.

2E is a cross-sectional view illustrating a wiring structure including a thin film capacitor having a MIM structure manufactured as described above. Referring to FIG. 2E, a first lower interconnection of a copper film, which is insulated from each other by the first interlayer insulating film 55 by a dual damascene process known in the art, and contacts the upper electrode 53 and the lower electrode 51, respectively. A second lower interconnection 56b, which is insulated from each other by the first interlayer insulating film 55 and contacts the lower electrode 51 and has wiring holes, is formed.

Thereafter, the contact portions are insulated from each other by the second interlayer insulating film 58 by the dual damascene process, thereby forming the upper wiring 60 of the copper film contacting the first and second lower wirings 56a and 56b. . At this time, a barrier that prevents diffusion of copper from the wirings 56a, 56b, and 60 between the first interlayer insulating film 55 and the second interlayer insulating film 58 and between the second interlayer insulating film 58 and the upper wiring 60. As the layer, the first and second nitride films 57 and 59 may be interposed, respectively.

As described above, in the present invention, the dielectric layer lost in the process of patterning the upper electrode is recovered by depositing a compensation film on the upper electrode, thereby preventing the diffusion of copper due to unwanted dielectric layer loss.

Accordingly, excellent barrier properties of the dielectric layer against copper diffusion from the lower electrode can be ensured, and when the upper electrode is patterned, the etching thickness of the dielectric layer is controlled and the etched thickness is deposited to recover the initial dielectric layer deposition thickness. This prevents the loss of capacitance.

As a result, the characteristics and reliability of the MIM structure capacitor can be improved.

The present invention described above is not limited to the above-described embodiments and drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be apparent to those who have knowledge.

Claims (14)

Semiconductor substrates; A lower electrode of the first metal film formed on the substrate; A dielectric layer formed on the lower electrode and having a protruding region thicker than a periphery thereof; An upper electrode formed on the protruding region of the dielectric layer; And a compensation layer formed on the upper electrode and the dielectric layer. The method of claim 1, The compensation layer is a capacitor of a semiconductor device having a thickness that is substantially the same height as the dielectric layer of the protrusion area on top of the dielectric layer having a thickness thinner than the protrusion area. The method of claim 1, The first metal film is made of a copper film, the second metal film is a capacitor of a semiconductor device made of a titanium nitride film. The method of claim 1, The dielectric layer and the compensation layer is a capacitor of the semiconductor device consisting of a nitride film. The method of claim 1, The dielectric layer having a thickness thinner than that of the protrusion region is 1/2 of the thickness of the protrusion region. The method of claim 1, The dielectric layer of the protruding region has a thickness of 500 to 1000 GPa, and the compensation layer has a thickness of 250 to 500 GPa. The method of claim 1, And a dielectric layer having a thickness thinner than that of the protruding region is etched during the patterning of the upper electrode. Sequentially forming a lower electrode of the first metal film, a dielectric layer, and an upper electrode of the second metal film on the semiconductor substrate; Selectively etching the upper electrode to leave a predetermined width, and etching a dielectric layer excluding a lower portion of the upper electrode to a predetermined thickness to make the dielectric layer below the upper electrode a protruding region; Forming a compensation film on the upper electrode and the dielectric layer Capacitor manufacturing method of a semiconductor device comprising a. The method of claim 8, The compensation film is a capacitor manufacturing method of a semiconductor device to form a thickness that is substantially the same height as the dielectric layer of the protrusion area on top of the dielectric layer having a thickness thinner than the protrusion area. The method of claim 8, And the dielectric layer and the compensation layer are formed of a nitride film. The method of claim 8, The method of manufacturing the capacitor of the semiconductor device to selectively etch the dielectric layer except the lower portion of the upper electrode by etching half the total thickness of the upper electrode to selectively etch the upper electrode. The method of claim 8, The dielectric layer is formed to have a thickness of 500 to 1000 Å, and when the upper electrode is selectively etched, the dielectric layer excluding the lower portion of the upper electrode is etched to have a thickness of 250 to 500 Å to make the dielectric layer below the upper electrode a protruding region. Capacitor Manufacturing Method. The method of claim 8, The first metal film is made of a copper film, the second metal film is a capacitor manufacturing method of a semiconductor device consisting of a titanium nitride film. The method of claim 8, The upper electrode is a capacitor manufacturing method of a semiconductor device to form a thickness of 500 to 1000Å.

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