KR100604879B1 - Semiconductor device for decreasing data skew - Google Patents

Abstract

Disclosed is a semiconductor device capable of differently controlling an enable time or a disable time of a column select signal according to a data line length. The semiconductor device may include enabling and disabling the column selection signal for controlling the operation of the switch forming the long data path and disabling the column selecting signal for controlling the operation of the switch forming the short data path. It is faster than the starting point. Therefore, the data validity interval output through the short data path and the data validity interval output through the long data path are the same. Therefore, since skew between data output from the semiconductor device according to the present invention is reduced, the semiconductor device can operate at a high speed.

Description

Semiconductor device for reducing data skew

1 is a block diagram of a general semiconductor device according to the prior art.

FIG. 2 is a circuit diagram of a column select line driver of the semiconductor memory device of FIG.

3 is a timing diagram illustrating data skew during a data read operation of the semiconductor memory device of FIG. 1.

4 is a configuration diagram of a semiconductor device according to the present invention.

FIG. 5 is a timing diagram illustrating data skew during a data read operation of the semiconductor memory device of FIG. 4.

The present invention relates to a semiconductor device capable of reducing data skew, and more particularly, to a semiconductor device capable of controlling an enable time and a disable time of a column select line according to a length of a data line. .

Semiconductor devices in general. In particular, the data read operation of the memory device consists of a word line active process and a data transfer process of transferring data to an external pin by column select line enable.

In the word line active process, a desired word line is selected through a combination of at least one control signal output from a memory controller and an address decoding process, and a charge of a memory cell connected to the selected word line is transferred between the bit line and the complementary bit line. The process of amplifying the voltage of the bit line by using charge sharing and bit line sense amplifier.

In addition, the data transfer process includes transferring the voltage of the amplified bit line to the data line and amplifying a predetermined voltage using a data line sense amplifier, and then transferring the amplified voltage to the corresponding data pin.

1 is a configuration diagram of a conventional semiconductor device 100. Referring to FIG. 1, the memory array 101 is formed in a region where a plurality of word lines and a plurality of bit lines cross each other as is well known in the art.

The row address decoder 102 receives a row address, decodes it, and generates a signal for selecting / driving a word line. The column address decoder 103 receives the column address, decodes it, and generates a decoded address DCAB. Each column select line driver 104 generates respective column select signals CSL_L and CSL_S for controlling a switching operation of each switch 107 connecting the bit lines and the data lines 105 and 106.

Information (or data) carried on each data line pair is output to the corresponding data line sense amplifiers 108a and 108b and the pads 109a and 109b as data DATA_S and DATA_L.

1 is a block diagram of a conventional semiconductor device according to the prior art, FIG. 2 is a circuit diagram of a column select line driver of the semiconductor memory device of FIG. 1, and FIG. 3 is a data skew during a data read operation of the semiconductor memory device of FIG. Is also a timing diagram.

The data reading operation will be described briefly with reference to FIGS. 1 to 3 as follows. When the read command is decoded, the column address decoder 103 decodes the input column addresses and outputs the decoded address DCAB to the column select line driver 104.

The internal clock generator 110 generates an internal clock PCLK by delaying the external clock CLK. The column select line enable signal generator 111 receives the internal clock PCLK and delays it to generate the column select line enable signal CSLEB.

The column select line disable signal generator 112 receives the column select line enable signal CSLEB and delays it to generate the column select line disable signal CSLDB. Each of the column select line drivers 104 receives a decoded address DCAB, a column select line enable signal CSLEB, and a column select line disable signal CSLDB, and based on them, each column select signal CSL_L. And CSL_S).

Referring to FIG. 3, the time points at which the column selection signals CSL_L and CSL_S are activated are the same.

The length of the data line, i.e. the distance from the column select switch 107 to the data line sense amplifiers 108a and 108b is short and long, i.e. long regardless of the loading of the data line 105 or 106. The enable time and the disable time of the column select signal CSL_L for activating the data line and the column select signal CSL_S for activating the short data line are the same.

Therefore, in the conventional semiconductor device, skew DSK occurs between the data DATA_L and DATA_S due to the loading difference depending on the length of the data line. The skew DSK is a constraint that the semiconductor device operates at a high frequency.

Accordingly, an aspect of the present invention is to provide a semiconductor device capable of controlling an enable time and a disable time of column select signals according to a length of a data line in order to solve the above-described problems of the related art.

According to an aspect of the present invention, a semiconductor device includes: a plurality of memory cells positioned at intersections of each of a plurality of word lines and a plurality of bit lines; A plurality of switches each connecting a corresponding bit line and a corresponding data line in response to a corresponding column selection signal; A first column selection line driver configured to generate a corresponding first column selection signal based on corresponding first control signals; And a second column selection line driver configured to generate a corresponding second column selection signal based on corresponding second control signals, wherein an activation period of the first column selection signal is based on the first control signals. And the activation period of the second column selection signal is determined based on the second control signals, and the activation period of the second column selection signal is longer than the activation period of the first column selection signal. There is a corresponding delay.

The semiconductor device further includes a first control signal generation circuit for generating the first control signals and a second control signal generation circuit for generating the second control signals, wherein the first control signal generation circuit generates an internal clock signal. A first enable signal generator that receives and outputs a first enable signal as one of the first control signals; And a first disable signal generator configured to receive the first enable signal and to output a first enable signal as another one of the first control signal, wherein the second control signal generator is configured to provide the internal clock signal. A second enable signal generator that receives and outputs a second enable signal as one of the second control signals; And a second enable signal generator configured to receive the second enable signal and output a second enable signal as another one of the first control signals.

The generation time point of the first enable signal and the generation time point of the second enable signal are different from each other. The timing of generating the first disable signal and the timing of generating the second disable signal are different from each other.

In accordance with an aspect of the present invention, a semiconductor device includes: a first bit line and a second bit line connected to corresponding word lines; A first switch connecting the first bit line and the first data line in response to a first column selection signal; A second switch connecting the second bit line and the second data line in response to a second column selection signal; An internal clock generator configured to generate an internal clock in response to the external clock; A first control signal generation circuit generating a first enable signal in response to the internal clock, and generating a first enable signal in response to the first enable signal; A second control signal generation circuit generating a second enable signal in response to the internal clock, and generating a second disable signal in response to the second enable signal; A first column select line driver configured to receive an address, the first enable signal and the first disable signal, and generate the first column select signal based on the first enable signal and the first enable signal; And a second column select line driver configured to receive the address, the second enable signal, and the second disable signal and generate the second column select signal based on the address and the second enable signal.

The length of the first data line is different from the length of the second data line. The semiconductor device further includes a first delay circuit for delaying the second enable signal, and the semiconductor device further includes a second delay circuit for delaying the second enable signal.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

4 is a configuration diagram of a semiconductor device according to the present invention. Referring to FIG. 4, the semiconductor device 200 may include a memory cell array 101, a row address decoder 102, a column address decoder 103, a plurality of data line sense amplifiers 108a and 108b, and a plurality of switches. 107_L and 107_S, internal clock signal generator 110, first column select line driver 104_L, second column select line driver 104_S, first control signal generator circuit 220, and second control signal generation Circuit 230.

Referring to FIG. 4, the distance from the column select switch 107_L to the data line sense amplifier 108b is long. This distance is referred to as the "long data path".

The distance from the column select switch 107_S to the data line sense amplifier 108a is short. This distance is referred to as the "short data path."

Accordingly, the first control signal generation circuit 220 and the second control signal generation circuit 230 may adjust the enable timing of each column selection signal CSL_L and CSL_S differently as shown in FIG. 5.

The internal clock signal generator 110 receives the external clock CLK and delays it for a predetermined time to generate the internal clock signal PCLK. The first control signal generation circuit 220 includes a first enable signal generator 221 and a first disable signal generator 222.

The first enable signal generator 221 receives the internal clock signal PCLK and delays it for a predetermined time to generate the first enable signal CSLEB_L.

The first enable signal generator 222 receives the first enable signal CSLEB_L and delays it for a predetermined time to generate a first enable signal CSLDB_L.

As shown in FIG. 2, the first column select line driver 104_L receives the decoded address DCAB, the enable signal CSLEB_L, and the disable signal CSLDB_L, and in response to the column select signal Enable time and / or disable time of CSL_L) are controlled. Accordingly, the first column select line driver 104_L may drive the long data line 105.

The second control signal generator 230 includes a second enable signal generator 231 and a second enable signal generator 232.

The second enable signal generator 231 receives the internal clock signal PCLK and generates a second enable signal CSLEB_S by delaying the internal clock signal PCLK for a predetermined time. The semiconductor device 200 may further include a delay circuit 233 for adjusting a delay of the second enable signal CSLEB_S. The delay circuit 233 may be implemented with a resistor and / or a capacitor. In addition, the delay circuit 233 may be implemented in the second enable signal generator 231.

The second disable signal generator 232 receives the output signal CSLEB_S of the second enable signal generator 231 and delays it for a predetermined time to generate a second disable signal CSLDB_S.

The semiconductor device 200 may further include a delay circuit 234 for adjusting a delay of the second disable signal CSLDB_S. The delay circuit 234 may be implemented with a resistor and / or a capacitor.

In addition, the delay circuit 234 may be implemented inside the second disable signal generator 232.

As shown in FIG. 2, the second column select line driver 104_S receives the decoded address DCAB, the second enable signal CSLEB_S, and the second disable signal CSLDB_S, and in response thereto. An enable time point and / or a disable time point of the column selection signal CSL_S are controlled. Accordingly, the second column select line driver 104_S may drive the short data line 106.

FIG. 5 is a timing diagram illustrating data skew during a data read operation of the semiconductor memory device of FIG. 4. Referring to FIG. 5, the state of the column selection signal CSL_L for controlling the switching operation of the switch 107_L is determined based on the first enable signal CSLEB_L and the first disable signal CSLDB_L.

 The state of the column selection signal CSL_S for controlling the switching operation of the switch 107_S is determined based on the second enable signal CSLEB_S and the second disable signal CSLDB_S.

The first enable signal CSLEB_L is enabled (for example, transitions to a logic low) faster than the second enable signal CSLEB_S by a predetermined time ΔT1.

Therefore, the enable time of the column select signal CSL_L is earlier than the enable time of the column select signal CSL_S. Therefore, if the enable time of the column select signal CSL_L and the enable time of the column select signal CSL_S can be properly controlled, the data DATA_L is stored through the long data line 105 and the pad 109b. The time point at which the data DATA_S is output through the short data line 106 and the pad 109a may be the same.

In addition, the time of disabling the column select signal CSL_L is earlier than the time of disabling the column select signal CSL_S. Therefore, when the disable timing of the column selection signal CSL_L and the disable timing of the column selection signal CSL_S can be properly controlled, the data DATA_L output through the long data line 105 and the pad 109b. ) And the end of the data DATA_S output through the short data line 106 and the pad 109a may be the same.

Therefore, the semiconductor device according to the present invention always starts outputting a plurality of data at the same time regardless of the difference in the length of the data line, that is, the loading difference.

Therefore, since the effective periods between the plurality of data are the same, the semiconductor device according to the present invention can prevent the occurrence of skew between the plurality of data.

Although the present invention has been described with reference to the embodiments illustrated in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, since the semiconductor device according to the present invention can control the enable time and / or the disable time of the column selection signal according to the length of the data line, skew of the data of the semiconductor memory device is reduced. Therefore, the data error is reduced during the data read operation of the semiconductor device.

Claims (8)

In a semiconductor device, A plurality of memory cells positioned at intersections of each of the plurality of word lines and each of the plurality of bit lines; A plurality of switches each connecting a corresponding bit line and a corresponding data line in response to a corresponding column selection signal; A first column selection line driver configured to generate a corresponding first column selection signal based on corresponding first control signals; And A second column selection line driver for generating a corresponding second column selection signal based on corresponding second control signals, The activation period of the first column selection signal is determined based on the first control signals, and the activation period of the second column selection signal is determined based on the second control signals. The activation period is delayed by a length corresponding to the length of the data line than the activation period of the first column selection signal. The semiconductor device of claim 1, further comprising a first control signal generation circuit for generating the first control signals and a second control signal generation circuit for generating the second control signals. The first control signal generation circuit, A first enable signal generator for receiving an internal clock signal and outputting a first enable signal as one of the first control signals; And A first enable signal generator configured to receive the first enable signal and output a first disable signal as another one of the first control signals, The second control signal generation circuit, A second enable signal generator that receives the internal clock signal and outputs a second enable signal as one of the second control signals; And And a second disable signal generator configured to receive the second enable signal and output a second disable signal as another one of the first control signal. The semiconductor device of claim 2, wherein a generation time of the first enable signal and a generation time of the second enable signal are different from each other. The semiconductor device of claim 2, wherein a generation time point of the first disable signal and a generation time point of the second disable signal are different from each other. A first bit line and a second bit line connected to each of the corresponding word lines; A first switch connecting the first bit line and the first data line in response to a first column selection signal; A second switch connecting the second bit line and the second data line in response to a second column selection signal; An internal clock generator configured to generate an internal clock in response to the external clock; A first control signal generation circuit generating a first enable signal in response to the internal clock, and generating a first enable signal in response to the first enable signal; A second control signal generation circuit generating a second enable signal in response to the internal clock, and generating a second disable signal in response to the second enable signal; A first column select line driver configured to receive an address, the first enable signal and the first disable signal, and generate the first column select signal based on the first enable signal and the first enable signal; And And a second column select line driver configured to receive the address, the second enable signal, and the second disable signal and generate the second column select signal based on the address and the second enable signal. The semiconductor device of claim 5, wherein a length of the first data line and a length of the second data line are different from each other. 7. The semiconductor device of claim 6, wherein the semiconductor device further comprises a first delay circuit for delaying the second enable signal. 8. The semiconductor device of claim 7, wherein the semiconductor device further comprises a second delay circuit for delaying the second disable signal.

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