KR19980015747A - Semiconductor memory device capable of reducing CSL skew - Google Patents

Abstract

And a semiconductor memory device capable of reducing CSL skew. The present invention is characterized by including loading means for compensating a loading difference depending on the position of a column decoder to which the output of each column decoder is gated, or by compensating for a CSL enable time by a distance from a column decoder to a selected word line There is an advantage that the CSL skew can be reduced.

Description

Semiconductor memory device capable of reducing CSL skew

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of reducing CSL skew.

2. Description of the Related Art [0002] With the progress of high performance of semiconductor memory devices in recent years, SDRAM (Synchronous DRAM) has been developed as a method for coping with these. Since the SDRAM operates in a short cycle, skew of a chip internal signal appears as one of the important problems. Accordingly, various methods for minimizing such a signal skew have been proposed.

Hereinafter, the prior art will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram of a general SDRAM. Memory arrays 1a to 1h are divided into a predetermined size and distributed in a chip. A word line (WL) and a column select line There are row decoders 2a to 2h and column decoders 3a to 3h for controlling the CSL. The column predecoders 4a to 4h receive a column address and decode the address to supply the address information to the column decoders 3a to 3h.

3 shows a timing diagram (Timing Diagram) of a read operation of the SDRAM. In this case, CAS latency = 3 and burst length = 4. The external address ADD is received at the rising edge of the CLK and the next address is generated using the counter at every CLK And proceeds with the burst operation. Since CL = 3, Dout is taken first in the third CLK.

In the case of the SDRAM, a plurality of data exist simultaneously in one data path according to the CL, and in the case of a pipelined operation, more data than one prefetch It is present in the path. Accordingly, when the data generation time of each address is changed, the intervals between data and data are different from each other, and accordingly, the time for latching valid data becomes relatively small. This becomes a more important factor as the frequency becomes higher.

4 shows a circuit diagram of a column predecoder according to the prior art. Here, the DCAij information generated by CAi and CAj has gating memory blocks 21a to 21d, respectively. In the case of DCAibjb, the gating is performed to the nearest and the DCAij is gated to the farthest. Therefore, the time to arrive at the column decoder is different between DCAibjb and DCAij, and the time interval between data by the selected address is different.

In addition, due to an increase in chip size, the loading on one column select line CSL also increases gradually. When the column select line CSL is selected, the side closer to the CSL driver The timing of the enable of the column selection line CSL on the far side is also different.

It is therefore an object of the present invention to provide a semiconductor memory device capable of reducing the CSL skew in order to solve the problems in the prior art.

1 is a block diagram of a general SDRAM

Fig. 2 is a view showing a part of Fig. 1

3 is a timing chart of the read operation of the SDRAM

4 is a circuit diagram of a column pre-decoder according to the prior art.

5 is a circuit diagram of another embodiment of a column predecoder according to the present invention.

FIG. 6 is a block diagram showing another configuration example of the column pre-decoder according to the present invention

According to an aspect of the present invention, there is provided a semiconductor memory device capable of reducing CSL skew, including: a memory array including a plurality of memory cells, a plurality of word lines, and a plurality of bit lines; And a read / write means for writing data into or from the column decoder, the pre-decoder means predecoding the column address as input; A column decoder means for receiving the output of the pre-decoder means and generating a column selection signal; And loading means for compensating a loading difference depending on the position of the column decoder to which the output of each column decoder is gated.

A semiconductor memory device comprising: a memory array having a plurality of memory cells, a plurality of word lines, and a plurality of bit lines; and a read / write means for reading or writing data of the memory cells, A column pre-decoder means for pre-decoding the data; A column decoder means for receiving the output of the column pre-decoder means and generating a column select signal; Row decoder means for decoding a row address as an input and selecting a word line; A row pre-decoder means for predecoding the row address as an input; And loading means for compensating for the CSL enable time by the distance from the column decoder to the selected word line.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 shows a part of FIG. 1, in which the memory block is divided into banks 0 11a and 1 11b by banks and word lines WL are divided into row addresses RAi, RAiB, RAj , RAjB, which are separated by the row decoders 12a and 12b. Also, the CSLs are selected by the column decoders 13a and 13b classified by the column addresses (CAi, CAiB, CAj, and CAjB). As shown in FIG. 2, the column predecoders 14a and 14b are selected by CAi, and the selected DCAij line runs all over the memory block.

5 shows a circuit diagram of a column predecoder according to the present invention, showing a method of eliminating skew between DCAij lines.

Referring to FIG. 5, in the case of the memory block CBLKO 31a, DCAibjb is gated and CBLK3 (31d) is gated DCAij. Herein, the DCA ijjb line intentionally loads a capacitor 33a which can compensate for the delay corresponding to the CBLK3 31d at which the DCAij information arrives latest. In this way, the compensation capacitors 33b and 33c are also applied to the DCAibj and DCAijb lines, respectively. Therefore, the delays of the DCAij lines from the column pre-decoder 32 to the respective memory blocks 31a to 33d can be the same.

As shown in FIG. 2, the SDRAM has a plurality of banks enabled, and data can be extracted from each bank. Here, the case where the bank 0 (11a) and the bank 1 (11b) are enabled is shown. At this time, the word line (WL) of the block corresponding to RAib and RAjb is selected in the bank 0 (11a), and the block corresponding to RAi and RAj is selected in the bank 1 (11b). Therefore, in the bank 0 (11a), the one farther from the CSL driver is selected, and in the bank 1 (11b), the one closest to the CSL driver is selected. Therefore, it is not possible to have a constant interval width between data generated as the bank changes.

FIG. 6 shows another circuit diagram of a column pre-decoder according to the present invention and shows a method of compensating the CSL enable time by CSL loading.

When the far block (RBLK0) is in the CSL driver as in bank 0, the NMOS transistor 44a is selected by DRAibjb and the capacitor 45a is added to the loading component of the DCAij line to set the CSL enable point in bank 1 . In this way, the delay can be compensated by the corresponding capacitors 45b and 45c for RBLK1 and RBLK2 as well.

Therefore, the semiconductor memory device capable of reducing the CSL skew according to the present invention has loading means for compensating for the loading difference depending on the position of the column decoder to which the output of each column decoder is gated, CSL skew can be reduced by providing loading means for compensating for the CSL enable time by the distance from the selected word line to the selected word line.

It is apparent that the present invention is not limited to the above-described embodiments, and that various modifications can be made by those skilled in the art within the technical scope of the present invention.

Claims (4)

1. A semiconductor memory device comprising a memory array composed of a plurality of memory cells, a plurality of word lines, and a plurality of bit lines, and a read / write means for reading or writing data of the memory cells, Pre-decoder means for predecoding the column address as an input; A column decoder means for receiving the output of the pre-decoder means and generating a column selection signal; And loading means for compensating a loading difference depending on a position of a column decoder to which an output of each column decoder is gated. The method according to claim 1, Wherein the loading means comprises MOS capacitors capable of compensating delays between predecoding lines. ≪ Desc / Clms Page number 19 > 1. A semiconductor memory device comprising a memory array composed of a plurality of memory cells, a plurality of word lines, and a plurality of bit lines, and a read / write means for reading or writing data of the memory cells, Column pre-decoder means for predecoding the column address as an input; A column decoder means for receiving the output of the column pre-decoder means and generating a column select signal; Row decoder means for decoding a row address as an input and selecting a word line; A row pre-decoder means for predecoding the row address as an input; And a loading means for compensating a CSL enable timing by a distance from the column decoder to a selected word line. The method of claim 3, And the loading means is composed of an NMOS transistor in which a MOS capacitor which can compensate for a delay corresponding to the distance from the column decoder to a selected word line and an output signal pre- The CSL skew can be reduced.