JPH11126475A - Semiconductor memory and data allotting method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory and its data allotting method in which the access time of initial data and the pre-charge time can be shortened. SOLUTION: A cell array is divided by a sub-word decoder column 102 and a sense amplifier row 101. Cell arrays YA0-YA3, to which the lead bit and the trailing bit of serial access are allotted are smaller than the other cell arrays CA00-CA33. Further, a code 103 shows a main word decoder row and a code 104 shows a column decoder column, in the figure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory of the type which accesses in units of sectors and reads / writes data serially, and a data allocation method thereof.

[0002]

2. Description of the Related Art With the increase in the capacity of semiconductor memories, the type of serial access in units of sectors has increased.

[0003] Conventional DRA mainly for serial access
M is described in JP-A-9-82086, and FIG.
The block diagram is shown in FIG. Data read from the memory cell selected by the word line is transmitted to the main sense amplifier MSA via the sub-sense amplifier SSA shared by the four bit lines. Next, the data is transferred to the data latch DAL. The data stored in the DAL is read out serially and output to the outside through an output buffer. While data is serially read from the DAL, data of another bit line sharing the sub-sense amplifier is sensed by SSA and MSA. Conversely, in the case of a write operation, data written to the DAL in a serial manner is simultaneously transferred to the MSA and written to the memory cells via the bit lines.

[0004] These word lines and bit lines were all the same.

[0005]

By the way, high speed is required for semiconductor memories, and a memory which is accessed in units of sectors as in the conventional example is no exception. The cycle time of serial access has already been shortened, and the access time of the first data and the time from when the last data is written until when the next sector can be accessed are obtained.
(Precharge time) is required to be faster.

Therefore, the inventor of the present invention has conceived that the first data access time and the precharge time can be reduced by shortening the bit lines or word lines of the cell array to which the first or last several bits are allocated.

The present invention has been made based on such a situation and idea, and an object of the present invention is to shorten the initial data access time and the precharge time as compared with the related art.

[0008]

The gist of the semiconductor memory according to the present invention is that it is a semiconductor memory for reading and writing data in a serial manner, in which a first and / or last several bits of data are allocated to another cell array. A semiconductor memory comprising a bit line or a word line shorter than a bit line or a word line, or a cell array of bit lines and a word line. It is also possible to provide a plurality of columns of a cell array of short bit lines or word lines.

The gist of the semiconductor memory allocating method according to the present invention is a semiconductor memory for serially reading and writing data, wherein a bit of another cell array to which data of several bits at the beginning and / or the end is allocated is assigned. A semiconductor memory comprising a bit line or a word line shorter than a line or a word line, or a cell array of bit lines and a word line.

In the present invention, "several bits" means
The number of bits suitable for carrying out the present invention, such as 2 bits, 4 bits, and 8 bits, can be obtained.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to embodiments. (Embodiment 1)

FIG. 1 is a configuration diagram of the semiconductor memory according to the first embodiment. FIG. 12 shows a configuration diagram of a conventional semiconductor memory for comparison. The cell array is divided by a sub-word decoder row 102 and a sense amplifier row 101. The cell arrays YA0-YA3 to which the first and last bits of the serial access are allocated are smaller than the other cell arrays CA00-CA33. In the figure, reference numeral 103 denotes a main word decoder row, and 104 denotes a column decoder row.

FIG. 2 shows the assignment of the order of cells to be read / written in the sector. The word line direction is a sector, and cells attached to one word line are read out serially, but only the first and last cells are allocated to another cell array. This cell array YA0 has half the length of the word line as compared with the other cell arrays.

FIG. 3 shows waveforms of word lines and bit lines when reading the cell array YA0. Compared to FIG. 5 of the conventional example shown for comparison, the time (T1-T0) at which cell data starts to appear on the bit line after the word line starts rising is １ ／. This means that when the wiring length becomes 1/2, the wiring delay becomes 1 /
This is because it becomes 4. Since data comes out earlier, the access time of the 0th cell can be shortened.

FIG. 4 shows waveforms of word lines and bit lines at the time of writing to the cell array YA0. As compared with FIG. 6 of the conventional example shown for comparison, the time (T8-T7) from when the word line starts lowering until it is completely lowered is 下 が り.
Since the word line is closed early after the fifteenth cell is written, the time required for the next cycle can be shortened.

(Embodiment 2) Next, Embodiment 2 will be described. FIG. 7 is a configuration diagram of the semiconductor memory according to the second embodiment. As shown in FIG. 7, the cell arrays XA00 to XA13 to which the bits at the beginning, end, and the end before the end of the serial access are allocated are the other cell arrays CA.
It is smaller than OO-CA33. FIG. 8 shows the assignment of the serial read / write cell order. The sector is in the word line direction, and only the head, the tail, and the cell immediately before the tail are assigned to XAO0 and XA1O.
The bit lines of the cell arrays XAO0 and XA1O are half the length of the other cell arrays. In the figure, reference numeral 103 denotes a main word decoder row, and 104 denotes a column decoder row.

FIG. 9 shows waveforms of word lines and bit lines when reading the cell array XAOO. Compared to FIG. 5 of the conventional example shown for comparison, the time (T2−T1) from the start of cell data to the saturation of cell data is １ ／. The time (T4-T3) from the start of sensing to the end of sensing is also reduced to 1/4. This is because when the wiring length becomes T / 2, the wiring delay becomes T / 4. By finishing the sensing earlier, the access time of the 0th cell can be shortened.

FIG. 9 shows waveforms of word lines and bit lines at the time of writing in the cell array XA00. As compared with FIG. 6 of the conventional example shown for comparison, the time (T6−T5) from the start of data inversion to the end thereof is １ ／.
In addition, the time (T10-T9) from the start of the balance of the bit line to the end thereof is also reduced to 1/4. Since the time from the writing of the fifteenth cell to the end of the balance of the bit line is shortened, the time required for the next cycle can be shortened.

The present invention is not limited to the above embodiment. Modifications can be made without departing from the scope of the present invention.

[0020]

As described in detail above, the word line or bit line, or the word line and bit line are shorter than those of other cell arrays. Can be shortened, and the precharge time of the last bit can be shortened. These improve the access time and precharge time of the entire DRAM.

[Brief description of the drawings]

FIG. 1 is a block layout diagram of a semiconductor memory according to a first embodiment of the present invention;

FIG. 2 is an assignment diagram of serial input / output order of cells of the semiconductor memory according to the first embodiment of the present invention;

FIG. 3 is a waveform diagram of a bit line and a word line during reading of the semiconductor memory according to the first embodiment of the present invention;

FIG. 4 is a waveform diagram of a bit line and a word line during writing in the semiconductor memory according to the first embodiment of the present invention;

FIG. 5 is a waveform diagram of a bit line and a word line during reading of a semiconductor memory according to a conventional example of the present invention.

FIG. 6 is a waveform diagram of a bit line and a word line during writing in a semiconductor memory according to a conventional example of the present invention.

FIG. 7 is a block layout diagram of a semiconductor memory according to a second embodiment of the present invention;

FIG. 8 is an assignment diagram of serial input / output order of cells of a semiconductor memory according to a second embodiment of the present invention;

FIG. 9 is a waveform diagram of a bit line and a word line during reading of the semiconductor memory according to the second embodiment of the present invention;

FIG. 10 is a waveform diagram of bit lines and word lines at the time of writing in the semiconductor memory according to the second embodiment of the present invention;

FIG. 11 is a circuit diagram of a semiconductor memory according to a conventional example.

FIG. 12 is a block layout diagram of a semiconductor memory according to a conventional example.

[Explanation of symbols]

 CA00-CA33 Cell array YA00-YA3 Cell array with short word line YA00-YA3 Cell array with short lead line SSA Subsense amplifier (Subsense amplifier) MSA Main sense amplifier DAL Data latch 101 Sense amplifier array 102 Subword decoder array 103 Main word decoder array 104 Column decoder row

Claims (15)

[Claims] 1. A semiconductor memory for serially reading and writing data, comprising a cell array of bit lines shorter than bit lines of other cell arrays to which data of the first few bits are allocated. memory. 2. A semiconductor memory for serially reading and writing data, comprising a cell array of a word line shorter than a word line of another cell array to which data of the first few bits is allocated. . 3. A semiconductor memory for reading and writing data serially, comprising: a cell array of bit lines shorter than bit lines of other cell arrays to which data of the last several bits are allocated. Semiconductor memory. 4. A semiconductor memory for reading and writing data serially, comprising a cell array of a word line shorter than a word line of another cell array to which data of the last several bits are allocated. memory. 5. A semiconductor memory for serially reading and writing data, comprising a cell array of bit lines and word lines shorter than the bit lines and word lines of another cell array to which the first few bits of data are allocated. Semiconductor memory characterized by the above-mentioned. 6. A semiconductor memory for reading and writing data serially, comprising a cell array of bit lines and word lines shorter than the bit lines and word lines of another cell array to which the last few bits of data are allocated. Semiconductor memory characterized by the above-mentioned. 7. The semiconductor memory according to claim 1, wherein the data to be assigned is several bits of data at the beginning and end. 8. The semiconductor memory according to claim 1, comprising a plurality of columns of said cell array of short bit lines or word lines according to claim 1. 9. A data allocating method for a semiconductor memory, comprising: allocating first several bits of data to a cell array having a short bit line. 10. A data allocating method for a semiconductor memory, wherein data of the first few bits are allocated to a cell array having a short word line. 11. A data allocating method for a semiconductor memory, wherein data of the last several bits are allocated to a cell array having a short bit line. 12. A data allocating method for a semiconductor memory, wherein the data of the last few bits is allocated to a cell array having a short word line. 13. A data allocating method for a semiconductor memory, comprising allocating first several bits of data to a cell array having short bit lines and word lines. 14. A data allocating method for a semiconductor memory, comprising allocating the last few bits of data to a cell array having a short bit line and a short word line. 15. The data allocation method for a semiconductor memory according to claim 9, wherein data of several bits at the beginning and end are allocated.