KR100602326B1 - Method of forming a gate in a flash memory device - Google Patents

Abstract

According to the present invention, a tunnel oxide film and a first polysilicon layer are formed on a silicon substrate, and an ion implantation process is performed after etching a predetermined region of the first polysilicon layer and the tunnel oxide film, leaving only the active region of the cell. Forming a junction region in a predetermined region of the silicon substrate, forming a first insulating film on the entire structure, and performing an etch back process so that the first insulating film remains on portions of both sides of the first polysilicon layer. And sequentially forming a second insulating film, a second polysilicon layer for a control gate, and a tungsten silicide film on the entire structure, and etching a predetermined region of the tungsten silicide film, the second polysilicon layer, and the second insulating film. The present invention provides a method of forming a gate of a flash memory device, the method including forming a gate line.

Floating gate, first photoresist pattern, control gate

Description

Method of forming a gate in a flash memory device             

1 is a layout structure diagram of a mask shown for explaining a conventional method for forming a cell gate.

2 is a layout diagram of a mask shown for explaining a cell gate forming method according to the present invention.

3 (a) and 3 (b) are cross-sectional views illustrating a conventional cell gate forming method.

4 (a) to 4 (f) are cross-sectional views for explaining the cell gate forming method according to the present invention.

<Explanation of symbols for the main parts of the drawings>

11: silicon substrate 12: tunnel oxide film

13: first polysilicon layer 14: first photoresist pattern

15: insulating film 16: oxide-nitride-oxide (ONO) film

17: conductive film for control gate 18: hard mask film
19: second photoresist pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate formation method of a flash memory device, and more particularly to a buffer layer to prevent tunnel oxide damage of a source edge region due to plasma etching loss during gate formation of a cell. By using), the tunnel oxide and silicon substrates are not exposed during the Self-Aligned Etch (SAE) process, thereby fundamentally solving the substrate loss, oxide loss, and residual poly problems caused by the etching process. In addition, the present invention relates to a method of forming a gate of a flash memory device that can improve the reliability characteristics of the device due to process problems.

A method of forming a gate of a conventional flash memory device will be described below with reference to FIGS. 1 and 3.

FIG. 1 is a layout diagram of a mask shown to describe a conventional gate forming method, and FIGS. 3A to 3C are cross-sectional views illustrating a conventional cell gate forming method. .

Reference numeral (a) of FIG. 1 denotes an area that is opened during the first polysilicon layer etching process, and reference numeral b denotes an isolation pattern (ISO) pattern. As shown in FIG. 1, the conventional first polysilicon layer etching process may etch the first polysilicon layer over a portion of the tunnel oxide layer to insulate the cell from the cell along the word line.

In FIG. 3A, a tunnel oxide film 2 is formed over the silicon substrate 1. After forming the first polysilicon layer 3 for the floating gate on the tunnel oxide film 2, an oxide-nitride-oxide (ONO) film 4, which is an insulating film, is formed on the first polysilicon layer 3. . Thereafter, the second polysilicon layer 5 and tungsten silicide (WSix) 6 for the control gate are sequentially formed. Oxynitride, an anti-reflective coating (ARC), is formed on the tungsten silicide (WSix) 6. Thereafter, the gate mask 7 is deposited on the whole.

In FIG. 3B, the cell region is etched to the second polysilicon layer 5 using the gate mask 7 as an etch mask, and the peripheral circuit (Peri. Tr) region is etched to the silicon substrate 1. . The cell region is formed of a first polysilicon layer, an oxide-nitride-oxide (ONO) film, a second polysilicon layer, tungsten silicide (WSix), and an antireflection film (ARC), and the peripheral circuit (Peri.Tr) region is formed of a first polysilicon layer. Cell word lines are formed through two processes: gate etching and self-aligned etching (SAE) because it consists of one polysilicon layer or a second polysilicon layer, tungsten silicide (WSix), and anti-reflective coating (ARC). do.

This conventional gate forming method has the following problems.

First, in the gate and self-aligned etching (SAE) process, there is always a problem of attack of the under layer and residual of the etching layer unless the selectivity between the oxide layer and the polysilicon is very good. That is, due to the self-aligned etching (SAE) process, there is always a process change between wafer to wafer and lot to lot during etching of the first polysilicon layer. To reduce the erase characteristics. In addition, when the etching is less, poly-residue (Poly residue) is generated due to the gate contact bridge (Gate to contact bridge) or the increase in the channel length (Fail bit) occurs.

In addition, a charge up phenomenon due to plasma loss occurring at the tunnel oxide edge side during the etching process greatly affects the reliability of the device. That is, charges existing inside the floating gate near the source / drain vulnerable to etching loss are lost, which seriously affects the initial failure and operating life characteristics of the device.

Accordingly, the present invention provides the above-described disadvantages by preventing the tunnel oxide film and the silicon substrate from being exposed during the self-aligned etching process using a buffer layer to prevent the tunnel oxide film loss in the source edge region due to the plasma etching loss during the gate formation of the cell. It is an object of the present invention to provide a method for forming a gate of a flash memory device capable of solving the problem.

In accordance with another aspect of the present invention, there is provided a method of forming a gate of a flash memory device, the method including forming a tunnel oxide layer and a first polysilicon layer on a silicon substrate, and leaving only the active region of the cell. And etching a predetermined region of the tunnel oxide film to perform an ion implantation process to form a junction region in the predetermined region of the silicon substrate, and forming a first insulating film over the entire structure, followed by an etch back process. Allowing the first insulating film to remain on portions of both sides of the polysilicon layer, sequentially forming a second insulating film, a second polysilicon layer for control gate, and a tungsten silicide film on the entire structure, and the tungsten silicide Etching a predetermined region of the film, the second polysilicon layer, and the second insulating film to form a gate line Characterized in that made in box.

The present invention uses a first photoresist pattern instead of a conventional gate forming method that defines a first polysilicon layer for isolation between cells in the wordline direction. In addition, all areas except the gate active area are protected with an oxide film, an oxide film-based insulating film such as PSG (Phosphorus Silicate Glass), BPSG (Boron Phosphorus Silicate Glass), and then the buffer layer and channel loss to prevent etch loss. Used as an insulating film for prevention.

In addition, by dividing the first polysilicon layer and the second polysilicon layer separately, the contact area between the oxide-nitride-oxide (ONO) layer and the gate is increased to increase the gate coupling ratio, thereby improving characteristics.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

FIG. 2 is a layout diagram of a mask shown to explain a method of forming a cell gate according to the present invention, and FIGS. 4A to 4F illustrate a method of forming a cell gate according to the present invention. It is a cross section.

First, FIG. 4A is a cross-sectional view of a state in which a tunnel oxide film 12, a first polysilicon layer 13 for floating gates, and a first photoresist pattern 14 are sequentially deposited on a silicon substrate 11. .

FIG. 4B shows the first photosilicon layer 13 and the tunnel oxide layer 12 being etched after etching the floating gate, leaving only the active region of the cell, using the first photoresist pattern 14 as an etching mask. The resist pattern 14 is removed. Then, an ion implantation process for forming a junction is performed.

FIG. 4C is an insulating film 15 to be used as side wall passivation and an etching buffer layer of the first polysilicon layer 13 for floating gate on the entire structure of FIG. 4B. It is sectional drawing of the state formed. As the insulating layer 15, boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), medium temperature oxide (MTO), or the like, which is an oxide-based material, is used.

FIG. 4D illustrates an etching back process using a recipe having a high selectivity between polysilicon and an oxide film, so that a part of both sides of the first polysilicon layer 13 for floating gate is used as the insulating film 15. It is sectional drawing of the state which formed the protective film.

4E shows an oxide-nitride-oxide (ONO) film 16, an insulating film for control gate 17, a hard mask film 18, and an insulating film between the first polysilicon layers 13 on the entire structure. It is sectional drawing of the state which formed the 2nd photoresist pattern 19 sequentially. At this time, the control gate conductive film 17 is formed of a structure in which a polysilicon layer and a tungsten silicide layer are laminated, and the hard mask film 18 is formed of an oxynitride film which is an anti-reflective coating (ARC). . The second photoresist pattern 19 for the gate line is slightly larger than the floating gate to minimize misalignment and increase the gate coupling ratio with the first polysilicon layer 13 for the floating gate. .

4 (f) sequentially illustrates the hard mask film 18, the control gate conductive film 17, and the ONO (Oxide-Nitride-Oxide) film 16 using the second photoresist pattern 19 as an etching mask. It is sectional drawing of the state which formed the gate line by etching.

The present invention as described above can improve the reliability problem (Charge Loss) of the device, which is the biggest factor that determines the marketability of the flash memory device. Computationally, if one or more electrons escape from the floating gate a day, they will not be able to compensate for 10 years. The electrons in the floating gate are escaped by thermal and electrical stress, and the tunnel oxide is known to be the most vulnerable, and the measurement results prove the same. For this reason, in the present invention, the charge loss may be minimized toward the edge of the tunnel oxide layer by forming a protective layer around the floating gate with an oxide-based material.

In addition, the present invention can fundamentally solve the problem of semiconductor substrate (Sub) loss and the excess of polysilicon caused by the etching process. In the prior art, the cell region (the first polysilicon layer, the oxide-nitride-oxide (ONO) layer, the second polysilicon layer, the tungsten silicide layer (WSix), the hard mask layer) and the peripheral circuit region (the first polysilicon layer or Since the structures of the second polysilicon layer, the tungsten silicide layer (WSix), and the hard mask layer are different, the etching process is performed only to the second polysilicon layer of the cell region by the gate etching process, and the peripheral circuit region is etched to the silicon substrate. After opening only the cell region, the gate line was formed by etching the remaining oxide-nitride-oxide (ONO) layer, the first polysilicon layer, and the tunnel oxide layer. In such a case, etching of various other materials always causes an etch selectivity problem, which causes a problem of silicon substrate loss in the cell region or a surplus of poly silicon remaining in a very vulnerable place such as a step portion between the tunnel oxide layer and the active region. They increase junction leakage and become a charge pass if polysilicon remains, greatly affecting device reliability.

Therefore, the present invention fundamentally solves the problem of silicon substrate loss and poly silicon remaining due to the subsequent self-aligned etching (SAE) process using not only tunnel oxide protection but also an oxide layer (etch buffer layer).

In addition, the coupling ratio is improved by increasing the contact area between the ONO (Oxide-Nitirde-Oxide) film and the gate.

The gate of the present invention is divided into a floating gate and a control gate separately from the gate of the prior art, and the control gate is slightly enlarged so that the contact area between the polysilicon and the oxide-nitride-oxide (ONO) film is increased to couple. The ring ratio can be improved.

In this way, the same electric field can be obtained by applying a gate voltage lower than that of the prior art in order to apply an electric field required for erasing, which is advantageous in devices using low voltage.

As described above, the present invention can obtain the following effects.

First, it is possible to improve the reliability loss (Charge Loss) of the device, the biggest factor that determines the marketability of the flash memory device.

Second, the present invention can fundamentally solve the problem of silicon substrate loss and polysilicon remaining by the etching process.

Third, the coupling ratio is improved by increasing the contact area between the ONO (Oxide-Nitirde-Oxide) film and the gate.

Claims (7)

Forming a tunnel oxide film and a first polysilicon layer on the silicon substrate; Etching a predetermined region of the first polysilicon layer and the tunnel oxide layer, leaving only the active region of the cell, and then performing an ion implantation process to form a junction region in the predetermined region of the silicon substrate; Forming a first insulating film on the entire structure and then performing an etch back process so that the first insulating film remains on portions of both sides of the first polysilicon layer; Sequentially forming a second insulating film, a second polysilicon layer for control gate, and a tungsten silicide film on the entire structure; Etching a predetermined region of the tungsten silicide layer, the second polysilicon layer, and the second insulating layer to form a gate line. The method of claim 1, And the first insulating layer is used as sidewall passivation and an etching buffer layer of the first polysilicon layer. The method of claim 1, The first insulating layer is a gate forming method of a flash memory device using a PSG (Phosphorus Silicate Glass) is an oxide-based material. The method of claim 1, The first insulating layer is a gate forming method of a flash memory device using a BPSG (Boron Phosphorus Silicate Glass) is an oxide-based material. The method of claim 1, The first insulating layer is a gate forming method of a flash memory device using an oxide-based material MTO (Medium Temperature Oxidation). The method of claim 1, And forming the floating gate and the control gate separately. The method of claim 1, And defining the control gate larger than the floating gate.

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