KR100598244B1 - Method for manufacturing contact hole of semiconductor device - Google Patents

Method for manufacturing contact hole of semiconductor device Download PDF

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KR100598244B1
KR100598244B1 KR1020020023311A KR20020023311A KR100598244B1 KR 100598244 B1 KR100598244 B1 KR 100598244B1 KR 1020020023311 A KR1020020023311 A KR 1020020023311A KR 20020023311 A KR20020023311 A KR 20020023311A KR 100598244 B1 KR100598244 B1 KR 100598244B1
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layer
etch stop
contact hole
semiconductor device
stop layer
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KR20030085154A (en
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강철구
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 콘택홀 제조 방법에 관한 것으로, 특히 반도체 기판에 소자 분리막과 반도체 소자를 형성하고, 구조물 전면에 식각 정지막을 형성하고, 식각 정지막 상부 전면에 층간 절연막을 형성한 후에, 층간 절연막을 건식 식각하고 식각 정지막을 습식 식각하여 소자 분리막 및 반도체 소자의 활성 영역이 개방되는 콘택홀을 형성한다. 그러므로, 본 발명은 콘택홀 식각 공정시 식각 정지막을 습식 식각하기 때문에 소오스/드레인 접합 상부의 실리사이드막까지 과도 식각되지 않고 남아 있게 된다. 따라서, 반도체 기판의 접합 표면이 드러나거나 소자분리막의 에지가 과도 식각되지 않는 등 식각 정지막의 식각 불량이 발생하지 않게 되어 식각 정지막의 식각 불량으로 인해 야기되는 콘택 스파이크 현상을 미연에 방지할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a contact hole in a semiconductor device, and in particular, after forming an isolation layer and a semiconductor device on a semiconductor substrate, forming an etch stop film on the entire surface of the structure, and forming an interlayer insulating film on the entire surface of the etch stop film, The insulating layer is dry-etched and the etching stop layer is wet-etched to form contact holes for opening the device isolation layer and the active region of the semiconductor device. Therefore, the present invention wet-etches the etch stop layer during the contact hole etching process, so that the silicide layer on the top of the source / drain junction remains unetched. Therefore, the etching failure of the etch stop layer is not generated, such as the bonding surface of the semiconductor substrate is exposed or the edge of the device isolation layer is not excessively etched, thereby preventing contact spikes caused by the etching failure of the etch stop layer.

Description

반도체 소자의 콘택홀 제조 방법{METHOD FOR MANUFACTURING CONTACT HOLE OF SEMICONDUCTOR DEVICE}Method for manufacturing contact hole of semiconductor device {METHOD FOR MANUFACTURING CONTACT HOLE OF SEMICONDUCTOR DEVICE}

도 1a 내지 도 1c는 종래 기술에 의한 반도체 소자의 콘택홀 제조 방법을 설명하기 위한 공정 순서도,1A to 1C are flowcharts illustrating a method for manufacturing a contact hole in a semiconductor device according to the prior art;

도 2는 종래 기술의 콘택홀 제조 공정에 따른 콘택홀 식각 형태를 나타낸 단면도,2 is a cross-sectional view showing a contact hole etching form according to a prior art contact hole manufacturing process;

도 3a 내지 도 3c는 본 발명에 따른 반도체 소자의 콘택홀 제조 방법을 설명하기 위한 공정 순서도,3A to 3C are flowcharts illustrating a method for manufacturing a contact hole in a semiconductor device according to the present invention;

도 4는 본 발명의 콘택홀 제조 공정에 따른 콘택홀 식각 형태를 나타낸 단면도.Figure 4 is a cross-sectional view showing a contact hole etching form according to the contact hole manufacturing process of the present invention.

＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>

100 : 반도체 기판 102 : 소자 분리막100 semiconductor substrate 102 device isolation film

104 : 게이트 전극 106 : 스페이서104: gate electrode 106: spacer

108 : 소오스/드레인 영역 110 : 실리사이드막108: source / drain region 110: silicide film

112 : 식각 정지막 114 : 층간 절연막112: etch stop film 114: interlayer insulating film

116 : 콘택홀116: contact hole

본 발명은 반도체 제조 방법에 관한 것으로서, 특히 식각 정지막 및 층간 절연막에 반도체 소자의 콘택홀을 제조하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor, and more particularly, to a method for manufacturing a contact hole of a semiconductor device in an etch stop film and an interlayer insulating film.

반도체장치가 고집적화 됨에 따라 소자의 크기 및 선폭 등의 감소는 필연적인 사항이 되었으며, 이에 따라 미세 선폭의 구현 기술은 반도체장치 제작에 핵심 기술이 되고 있다. 소자의 고집적화에 직접적으로 영향을 미치는 콘택홀의 마진(margin)또한 아주 미세해지고 있다. 고집적 반도체소자의 콘택홀을 형성하기 위한 식각 공정으로는 콘택홀의 크기를 정확하게 조절하기가 용이한 건식 식각공정이 널리 사용된다.As semiconductor devices have been highly integrated, reductions in device size and line width have become inevitable. As a result, the technology for implementing fine line widths has become a key technology in the fabrication of semiconductor devices. The margin of contact holes, which directly affects the high integration of devices, is also becoming very fine. As an etching process for forming a contact hole of a highly integrated semiconductor device, a dry etching process for easily controlling the size of the contact hole is widely used.

도 1a 내지 도 1c는 종래 기술에 의한 반도체 소자의 콘택홀 제조 방법을 설명하기 위한 공정 순서도이다.1A to 1C are flowcharts illustrating a method for manufacturing a contact hole in a semiconductor device according to the prior art.

도 1a에 도시된 바와 같이, 반도체 기판(10)으로서 실리콘 기판에 우선 소자의 활성 영역과 비활성 영역사이를 분리하기 위한 소자 분리막(12)을 형성한다. 그리고 소자 분리막(12)이 형성된 실리콘 기판에 반도체 소자로서, MOSFET(Metal Oxide Semiconductor Field Effect Transistor)를 형성한다. 이때, MOSFET는 게이트 전극(14), 스페이서(16), 소오스/드레인 접합(18)으로 구성되며 게이트 전극(14) 및 소오스/드레인 접합(18) 표면에는 실리사이드막(20)이 추가 형성되어 전기 저항을 낮출 수 있다.As shown in FIG. 1A, a device isolation film 12 for first separating an active region and an inactive region of an element is formed on a silicon substrate as a semiconductor substrate 10. Then, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is formed on the silicon substrate on which the device isolation film 12 is formed. In this case, the MOSFET includes a gate electrode 14, a spacer 16, and a source / drain junction 18, and a silicide layer 20 is additionally formed on the surfaces of the gate electrode 14 and the source / drain junction 18. Can lower the resistance.

그리고 도 1b에 도시된 바와 같이, MOSFET가 형성된 반도체 기판(10) 전면에 식각 정지막(22)으로서 실리콘질화막을 얇게 형성한다. 식각 정지막(22) 상부 전면에 층간 절연막(PMD: Poly Metal Dielectric layer)(24)으로서 BPSG(BoroPhospho Silicate Glass) 또는 PSG(Phospho Silicate Glass)를 증착 및 어닐링한다. 그런 다음 화학적기계적연마(Chemical Mechanical Polishing)로 층간 절연막(24) 표면을 평탄화한다. 도면에 도시하지는 않았지만, 화학적기계적연마 공정시 발생된 스크래치(scratch)를 보상해주기 위하여 층간 절연막(24) 상부에 캐핑막을 추가 형성할 수도 있다.As shown in FIG. 1B, a thin silicon nitride film is formed as an etch stop film 22 on the entire surface of the semiconductor substrate 10 on which the MOSFET is formed. A BPG (BoroPhospho Silicate Glass) or PSG (Phospho Silicate Glass) is deposited and annealed as an interlayer insulating film (PMD) 24 over the etch stop layer 22. Then, the surface of the interlayer insulating film 24 is planarized by chemical mechanical polishing. Although not shown in the drawings, a capping film may be further formed on the interlayer insulating film 24 to compensate for the scratches generated during the chemical mechanical polishing process.

그리고나서 도 1c에 도시된 바와 같이, 층간 절연막(24) 상부에 콘택홀 영역을 정의하기 위한 마스크 패턴(미도시함)을 형성하고 이를 이용한 건식 식각 공정을 진행하여 층간 절연막(24)을 식각하고 그 하부의 식각 정지막(22)을 건식 식각한 후에 상기 마스크 패턴을 제거한다. 그러면 층간 절연막(24) 및 식각 정지막(22)에 MOSFET의 소오스/드레인 접합(18)이 드러나는 콘택홀(26)이 형성된다. 최근에는 반도체 소자가 고집적화됨에 따라 소자의 크기가 더욱 축소되고 있는데, 만약 마스크 패턴이 미스얼라인될 경우 층간 절연막(24) 및 식각 정지막(22)의 콘택홀 식각시 미스얼라인되어 소자분리막(12)이 드러나는 경우가 있다.Then, as shown in FIG. 1C, a mask pattern (not shown) for defining a contact hole region is formed on the interlayer insulating layer 24, and a dry etching process using the same is performed to etch the interlayer insulating layer 24. The mask pattern is removed after dry etching the etch stop layer 22 at the lower portion thereof. Then, contact holes 26 are formed in the interlayer insulating layer 24 and the etch stop layer 22 to expose the source / drain junctions 18 of the MOSFETs. Recently, as semiconductor devices are highly integrated, the size of the devices is further reduced. If the mask patterns are misaligned, they are misaligned at the time of contact hole etching between the interlayer insulating film 24 and the etch stop layer 22. 12) may be revealed.

도 2는 종래 기술의 콘택홀 제조 공정에 따른 콘택홀 식각 형태를 나타낸 단면도이다. 도 2에 도시된 바와 같이, 종래 기술의 콘택홀 식각 공정은 대개 건식 식각 공정으로 층간 절연막(24) 및 식각 정지막(22)을 식각하게 된다. 하지만, 이와 같은 식각 정지막(22)의 건식 식각 공정시 식각 균일도가 불량하게 될 경우 소오스/드레인 접합(18) 상부의 실리사이드막(20)까지 과도 식각되어 기판 표면이 드 러나거나 소자분리막(12) 에지가 과도 식각된다. 이러한 식각 정지막(22)의 식각 불량으로 인해 콘택 스파이크(contact spiking) 현상이 발생하게 되어 소자의 수율 및 제품의 신뢰성이 저하되는 문제점이 있었다.2 is a cross-sectional view illustrating a contact hole etching form according to a prior art contact hole manufacturing process. As shown in FIG. 2, the conventional contact hole etching process typically etches the interlayer insulating layer 24 and the etch stop layer 22 by a dry etching process. However, when the etching uniformity of the etch stop layer 22 becomes poor during the etching process, the surface of the substrate may be excessively etched to the silicide layer 20 on the source / drain junction 18 or the device isolation layer 12 may be excessively etched. ) The edge is over-etched. The contact spiking occurs due to the poor etching of the etch stop layer 22, resulting in a decrease in yield and reliability of devices.

본 발명의 목적은 상와 같은 종래 기술의 문제점을 해결하기 위하여 콘택홀 식각 공정시 층간 절연막은 건식 식각 공정으로 식각하되, 식각 정지막은 습식 식각 공정으로 식각함으로써 소오스/드레인 접합의 실리사이드막이 콘택홀 식각 공정시 식각 정지막의 식각 균일도를 양호하게 하여 콘택 스파이크 현상을 미연에 방지하고 이로 인해 소자의 수율 및 제품의 신뢰성을 높일 수 있는 반도체 소자의 콘택홀 제조 방법을 제공하는데 있다.An object of the present invention is to solve the problems of the prior art such as the phase, the interlayer insulating film during the contact hole etching process is a dry etching process, the etching stop film is a wet etching process by etching the silicide layer of the source / drain junction contact hole etching process The present invention provides a method for manufacturing a contact hole of a semiconductor device capable of improving the etching uniformity of a time etch stop layer to prevent a contact spike phenomenon in advance, thereby increasing the yield of a device and the reliability of a product.

이러한 목적을 달성하기 위하여 본 발명은 반도체 소자와 소자 분리막이 형성된 반도체 기판에 콘택홀을 형성함에 있어서, 반도체 기판에 소자 분리막과 반도체 소자를 형성하는 단계와, 구조물 전면에 식각 정지막을 형성하는 단계와, 식각 정지막 상부 전면에 층간 절연막을 형성하는 단계와, 층간 절연막을 건식 식각하고 식각 정지막을 습식 식각하여 소자 분리막 및 반도체 소자의 활성 영역이 개방되는 콘택홀을 형성하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method for forming a contact hole in a semiconductor substrate on which a semiconductor device and a device isolation film are formed, forming a device isolation film and a semiconductor device on a semiconductor substrate, and forming an etch stop film on the entire structure of the semiconductor substrate. And forming an interlayer insulating layer on the entire upper surface of the etch stop layer, and dry etching the interlayer insulating layer and wet etching the etch stop layer to form contact holes in which the device isolation layer and the active region of the semiconductor device are opened.

이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

도 3a 내지 도 3c는 본 발명에 따른 반도체 소자의 콘택홀 제조 방법을 설명 하기 위한 공정 순서도이다.3A to 3C are flowcharts illustrating a method for manufacturing a contact hole in a semiconductor device according to the present invention.

도 3a에 도시된 바와 같이, 반도체 기판(100)으로서 실리콘 기판에 우선 소자의 활성 영역과 비활성 영역사이를 분리하기 위한 소자 분리막(102)을 형성한다. 그리고 소자 분리막(102)이 형성된 실리콘 기판에 반도체 소자로서, MOSFET를 형성한다. 이때, MOSFET는 게이트 전극(104), 스페이서(106), 소오스/드레인 접합(108)으로 구성되며 게이트 전극(104) 및 소오스/드레인 접합(108) 표면에는 실리사이드막(110)이 추가 형성되어 전기 저항을 낮출 수 있다.As shown in FIG. 3A, a device isolation film 102 is formed on a silicon substrate as a semiconductor substrate 100 to separate between an active region and an inactive region of a device. Then, a MOSFET is formed as a semiconductor element on the silicon substrate on which the element isolation film 102 is formed. In this case, the MOSFET includes a gate electrode 104, a spacer 106, and a source / drain junction 108, and a silicide layer 110 is further formed on the surfaces of the gate electrode 104 and the source / drain junction 108. Can lower the resistance.

그리고 도 3b에 도시된 바와 같이, MOSFET가 형성된 반도체 기판(100) 전면에 식각 정지막(112)으로서 실리콘질화막을 얇게 형성한다. 식각 정지막(112) 상부 전면에 층간 절연막(114)으로서 BPSG 또는 PSG를 증착 및 어닐링한다. 그런 다음 화학적기계적연마로 층간 절연막(114) 표면을 평탄화한다. 도면에 도시하지는 않았지만, 화학적기계적연마 공정시 발생된 스크래치(scratch)를 보상해주기 위하여 층간 절연막(114) 상부에 캐핑막을 추가 형성할 수도 있다.3B, a thin silicon nitride film is formed as an etch stop film 112 on the entire surface of the semiconductor substrate 100 on which the MOSFET is formed. BPSG or PSG is deposited and annealed as an interlayer insulating layer 114 over the etch stop layer 112. Then, the surface of the interlayer insulating film 114 is planarized by chemical mechanical polishing. Although not shown in the drawings, a capping layer may be further formed on the interlayer insulating layer 114 to compensate for the scratches generated during the chemical mechanical polishing process.

그리고나서 도 3c에 도시된 바와 같이, 층간 절연막(114) 상부에 콘택홀 영역을 정의하기 위한 마스크 패턴(미도시함)을 형성하고 이를 이용한 건식 식각 공정을 진행하여 층간 절연막(114)을 식각한다. 그리고 그 하부의 식각 정지막(112)을 습식 식각한 후에 상기 마스크 패턴을 제거함으로써 층간 절연막(114) 및 식각 정지막(112)에 MOSFET의 소오스/드레인 접합(108)용 실리사이드막(110)이 드러나는 콘택홀(116)이 형성된다. 만약, 마스크 패턴이 미스얼라인될 경우 층간 절연막(114) 및 식각 정지막(112)의 콘택홀 식각시 미스얼라인되어 콘택홀 영역에 실리사이드막(11)과 소자분리막(102)이 함께 드러나는 경우가 있다. 하지만, 상기 식각 정지막(112)을 습식 식각해서 콘택홀을 형성하였기 때문에 그 하부의 소오스/드레인 접합(108)용 실리사이드막(110)의 과도 식각을 막아서 이후 콘택홀에 형성될 배선의 전기 저항 특성을 높여준다. 3C, a mask pattern (not shown) for defining a contact hole region is formed on the interlayer insulating layer 114, and a dry etching process using the interlayer insulating layer 114 is performed to etch the interlayer insulating layer 114. . After the wet etch stop layer 112 is wet-etched, the mask pattern is removed to form the silicide layer 110 for the source / drain junction 108 of the MOSFET in the interlayer insulating layer 114 and the etch stop layer 112. An exposed contact hole 116 is formed. If the mask pattern is misaligned, when the interlayer insulating layer 114 and the etch stop layer 112 are misaligned, the silicide layer 11 and the device isolation layer 102 are exposed together in the contact hole region. There is. However, since the etch stop layer 112 is wet-etched to form a contact hole, the electrical resistance of the wiring to be formed in the contact hole after preventing excessive etching of the silicide layer 110 for the source / drain junction 108 thereunder. Improves the characteristics.

도 4는 본 발명의 콘택홀 제조 공정에 따른 콘택홀 식각 형태를 나타낸 단면도이다.4 is a cross-sectional view illustrating a contact hole etching form according to the process of manufacturing a contact hole of the present invention.

도 4를 참조하면, 본 발명의 콘택홀 식각 공정은 건식 식각 공정으로 층간 절연막(114)을 식각하고 습식 식각 공정으로 식각 정지막(112)을 식각한다. 그러므로, 본 발명은 식각 정지막(112)의 습식 식각 공정시 식각 균일도가 양호해져소오스/드레인 접합(108) 상부의 실리사이드막(110)까지 과도 식각되지 않게 된다. 그러므로, 반도체 기판의 접합 표면이 드러나거나 소자분리막(102)의 에지가 과도 식각되지 않는다.Referring to FIG. 4, in the contact hole etching process of the present invention, the interlayer insulating layer 114 is etched by the dry etching process and the etch stop layer 112 is etched by the wet etching process. Therefore, in the present invention, the etching uniformity during the wet etching process of the etch stop layer 112 is improved, so that the etch stop layer 112 does not excessively etch the silicide layer 110 on the source / drain junction 108. Therefore, the bonding surface of the semiconductor substrate is not exposed or the edge of the device isolation film 102 is not excessively etched.

이상 설명한 바와 같이, 본 발명은 콘택홀 식각 공정시 식각 정지막을 습식 식각하기 때문에 소오스/드레인 접합 상부의 실리사이드막까지 과도 식각되지 않고 남아 있게 된다. 그러므로, 반도체 기판의 접합 표면이 드러나거나 소자분리막의 에지가 과도 식각되지 않는 등 식각 정지막의 식각 불량이 발생하지 않게 된다.As described above, in the present invention, since the etch stop layer is wet etched during the contact hole etching process, the silicide layer on the source / drain junction is left without excessive etching. Therefore, the etching failure of the etch stop layer does not occur, such as the bonding surface of the semiconductor substrate is exposed or the edge of the device isolation layer is not excessively etched.

따라서 본 발명은 식각 정지막의 식각 불량을 막아 콘택 스파이크 현상으로 인한 소자의 수율 및 제품의 신뢰성 저하를 미연에 방지할 수 있는 효과가 있다.Therefore, the present invention prevents the etching failure of the etch stop layer, thereby preventing the device yield and the reliability of the product due to the contact spike phenomenon can be prevented in advance.

한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위 에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (3)

반도체 소자와 소자 분리막이 형성된 반도체 기판에 콘택홀을 형성함에 있어서,In forming a contact hole in a semiconductor substrate on which a semiconductor device and an isolation layer are formed, 상기 반도체 기판에 상기 소자 분리막과 반도체 소자를 형성하는 단계;Forming the device isolation layer and the semiconductor device on the semiconductor substrate; 상기 구조물 전면에 식각 정지막을 형성하는 단계;Forming an etch stop layer on the front of the structure; 상기 식각 정지막 상부 전면에 층간 절연막을 형성하는 단계; 및Forming an interlayer insulating layer on an entire upper surface of the etch stop layer; And 상기 층간 절연막을 건식 식각하고 상기 식각 정지막을 습식 식각하여 상기 소자 분리막 및 반도체 소자의 활성 영역이 개방되는 콘택홀을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 콘택홀 제조 방법.And dry etching the interlayer insulating layer and wet etching the etch stop layer to form contact holes for opening the active region of the device isolation layer and the semiconductor device. 제 1항에 있어서, 상기 식각 정지막은 실리콘 질화막인 것을 특징으로 하는 반도체 소자의 콘택홀 제조 방법.The method of claim 1, wherein the etch stop layer is a silicon nitride layer. 제 1항에 있어서, 상기 콘택홀에 의해 개방된 상기 반도체 소자의 활성 영역 표면에는 실리사이드막이 형성된 것을 특징으로 하는 반도체 소자의 콘택홀 제조 방법.The method of claim 1, wherein a silicide layer is formed on a surface of an active region of the semiconductor device opened by the contact hole.
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