KR100597124B1 - Solid-state imaging device and method of manufacturing the same - Google Patents

Abstract

A plurality of N-type photodiode regions 3 formed in the P-type well 2, a gate electrode 4 having one end adjacent to the photodiode region, an N-type drain region 7 adjacent to the other end thereof, A device isolation region 10 having an STI structure is provided, and the thickness of the gate oxide film 5 is 10 nm or less. One end of the gate electrode overlaps the photodiode region. A first region 11 having a P-type first concentration C1 disposed at a surface portion from the photodiode region to the drain region at a predetermined distance from one end of the gate electrode, and one end thereof is adjacent to the first region. A second region 12 having a second P-type concentration C2 having the other end overlapping with the gate electrode, and a third P-type concentration C3 having one end adjacent to the second region and the other end adjacent to the drain region; A third region 13 is formed, and C1> C2> C3 or C1 ≒ C2> C3. The read characteristic at low voltage is favorable, and image defects, such as a white defect and a dark current, are fully suppressed.

Description

Solid-state imaging device and its manufacturing method {SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING THE SAME}

1 is a cross-sectional view showing a cell structure of a solid-state imaging device in Embodiment 1 of the present invention;

2 is a cross-sectional view showing a cell structure of a solid-state imaging device in Embodiment 2 of the present invention;

3 is a cross-sectional view showing a cell structure of the solid-state imaging device in Embodiment 3 of the present invention;

4 is a cross-sectional view for explaining generation of an image defect in the vicinity of a gate of a solid-state imaging device;

5 is a sectional view for explaining occurrence of the same image defect when the gate insulating film is thin;

6 is a cross-sectional view showing a cell structure of a solid-state imaging device of the prior art.

<Description of Symbols for Main Parts of Drawings>

1 Si substrate 2 P well

3: N-type photodiode 4: Gate electrode

5 gate oxide film 6: threshold injection region

7: drain region 8: P-type diffusion layer

9: P-type diffusion layer 10: device isolation

11: P-type first region 12: P-type second region

13: P-type 3rd area 14: P-type 2A area

15: P type 2B area 16: P type 3A area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device using an amplification-type MOS sensor, and in particular, a solid-state imaging device which enables reading at low voltage and suppresses image defects (in particular, white defects and dark currents). It is about.

The solid-state imaging device using the amplification-type MOS sensor has a structure of amplifying a signal detected by the photodiode with a transistor for each cell constituting each pixel, and has a feature of high sensitivity. One of the biggest problems of the solid-state imaging device is the reverse leakage current of the pn junction of a silicon semiconductor. Since this leak current cannot be separated from the signal current generated by the incident light, it becomes a noise and degrades the performance of a solid-state image sensor. One cause of this leakage current is due to the stress applied to the silicon substrate.

4 illustrates a state in which the gate insulating film 102 and the gate electrode 103 are formed on the silicon substrate 101. In this structure, the region where the stress causing the leakage current was applied in the vicinity of the surface of the silicon substrate 101 was the gate end region 104 from the end of the gate electrode 103 to the vicinity of the periphery thereof. In fact, inside this gate end region 104, a crystal defect 105 due to stress was observed. Such crystal defects were not observed under the gate electrode 103. From this, in the past, when designing a high performance solid-state imaging device, it was important how to suppress the leakage current generated in the portion of the gate end region 104. Since the gate end region 104 is also a pass point of charge when the signal charge is read from the photodiode formed on the left side of the gate electrode 103 in the drawing, the condition for making it easy to read the charge and the leakage current The design of the trade-off of the conditions to suppress the will be made.

In recent years, as the size of silicon semiconductors has progressed, it has been found that the place where stress is applied as a cause of the leakage current becomes a problem in addition to the above-mentioned region. As shown in FIG. 5, when a thin gate insulating film 102a is formed as compared with the conventional art, it has been found that the leakage current generated in the region below the gate 106 is larger than that of the conventional gate end region 104. Among the leak currents generated in the region under the gate 106, the leak current 108 flowing into the photodiode region 107 is a problem, and the leak current 110 flowing into the drain region 109 does not become a noise. There is no problem. In addition to the problem of how to suppress the leakage current 108 flowing into the photodiode region 107 under the gate electrode 103, the problem is how to design a trade-off that makes it easier to read signal charges from the photodiode. come.

Next, the structure of the cell cross section of the conventional solid-state imaging device is demonstrated, referring FIG. 6 is a cross-sectional view of a cell of a conventional solid-state imaging device (see, for example, Japanese Patent Laid-Open No. 11-274450). P wells 2 are formed on the Si substrate 1, and N-type photodiode regions 3 for photoelectric conversion are formed in the P wells 2. One end of the gate electrode 4 is adjacent to the N-type photodiode region 3. The lower portion of the gate electrode 4 has a MOS transistor structure, and the gate oxide film 5 and the threshold injection region 6 of the transistor are formed. The N-type drain region 7 is formed adjacent to the other end of the gate electrode 4. Photoelectrically converted electrons are accumulated in the N-type photodiode region 3, transferred to the N-type drain region 7, and detected as a signal. On the upper surface of the N-type photodiode region 3, a high concentration P-type diffusion layer 8 is adjacent to one end of the gate electrode 4 and a high concentration P-type diffusion layer 9 is adjacent to the P-type diffusion layer 8. ) Is formed. The high concentration P-type diffusion layer 9 is a surface shield layer that shields the upper surface of the photodiode, and is formed to suppress the influence of the Si-SiO ₂ interface on the interface level due to crystal defects and metal contamination. Each element of the photodiode and the plurality of MOS transistors is separated by an element isolation unit 10.

In the above conventional technique, the readout characteristics are improved by making the concentration of the P-type diffusion layer 8 near the gate lower than that of the P-type diffusion layer 9 forming the surface shield layer. However, when the concentration of the P-type diffusion layer 8 in the vicinity of the gate electrode 4 is reduced, the interface level at the Si-SiO ₂ interface and the active level in the Si substrate 1 cannot be sufficiently deactivated, resulting in an image defect ( Problems such as white defects and dark currents).

An object of the present invention is to provide a solid-state imaging device in which read characteristics at low voltage are good and image defects are sufficiently suppressed.

A solid-state imaging device of the present invention includes a plurality of N-type photodiode regions for photoelectric conversion of incident light formed inside a P-type well on a Si substrate, a gate electrode having one end adjacent to each of the photodiode regions, and the gate electrode. An N-type drain region adjacent to the other end of the substrate; and an element isolation region having a shallow trench isolation (STI) structure that separates each of a plurality of elements each of the photodiode region and the group of MOS transistors. The thickness is 10 nm or less. In order to solve the above problem, one end of the gate electrode overlaps the photodiode region, and is disposed at a surface portion from the upper portion of the photodiode region to the drain region and spaced apart from the one end of the gate electrode by a predetermined distance. A first region having a P-type first concentration C1 and a region having one end adjacent to the first region and the other end overlapping with the gate electrode; A third region having a P-type third concentration C3 having a second region and one end adjacent to the second region and the other end adjacent to the drain region is formed, and the relationship between the respective concentrations is C1> C2> C3 or C1 ≒ C2> C3.

The manufacturing method of the solid-state imaging device of this invention is a method of manufacturing the solid-state imaging device of the said structure, It is characterized by adjusting each said density | concentration by controlling the dose amount in the ion implantation which forms a P type diffused layer.

Another manufacturing method of the solid-state imaging device of the present invention is a method of manufacturing the solid-state imaging device having the above configuration, wherein the P-type diffusion layer in the first region is diffused under the gate electrode by heat treatment to form the P-type in the second region. By forming the diffusion layer, the concentration C1 is different from the concentration C2.

According to the configuration of the solid-state imaging device of the present invention, by separately controlling the concentrations of the P-type diffusion layers in the P-type second and P-type third regions, low voltage operation of 3 V or less can be achieved and image defects can be extremely small. have.

In the solid-state imaging device of the present invention, it is preferable that the bottom of the P-type diffusion layer in the second region is deeper than the bottom of the first region and the P-type diffusion layer in the third region. Moreover, it is preferable that the bottom part of the said 2nd area | region and the P type diffused layer of a 3rd area exists in a position deeper than the bottom part of the P type diffused layer of a said 1st area | region.

In the manufacturing method of the solid-state imaging device of the present invention, the acceleration energy in the ion implantation when forming the second region is made larger than when the first region and the third region are formed. It is preferable to make the bottom of the P-type diffusion layer deeper than the bottom of the P-type diffusion layer of the first region and the third region. Alternatively, the bottom of the P-type diffusion layer in the second region and the third region is made larger by accelerating the acceleration energy in the ion implantation when forming the second region and the third region than when forming the first region. It is preferable to make it deeper than the bottom part of the P-type diffusion layer of a said 1st area | region.

In addition, the bottom of the P-type diffusion layer in the second region and the third region is lower than the bottom of the P-type diffusion layer in the first region by heat treatment after ion implantation at the time of forming the second region and the third region. I can deepen it. The heat treatment can be a heat treatment in a gate oxide film forming step. Moreover, it is preferable to further perform an annealing process of 30 minutes or more at 1050 degreeC to the said gate oxide film formation process.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described concretely with reference to drawings.

(Embodiment 1)

 1 is a cross-sectional view showing a cell structure of the solid-state imaging device according to the first embodiment. In the P well 2 on the Si substrate 1, an N-type photodiode region 3 for photoelectric conversion of incident light is formed. One end of the gate electrode 4 is provided so as to form an overlap region between the photodiode region 3 and the photodiode region 3. Adjacent to the other end of the gate electrode 4, an N-type drain region 7 is formed. Under the gate electrode 4, a gate oxide film 5 is formed with a thickness of 10 nm or less. The element isolation unit 10 having a shallow trench isolation (STI) structure separates each element composed of a photodiode and a plurality of MOS transistors.

In the surface portion of the photodiode region 3, a P-type first region 11 having a P-type first concentration and a P-type second region 12 having a P-type second concentration are formed. In the region adjacent to the P-type second region 12 and across the drain region 7, a P-type third region 13 having a P-type third concentration is formed. The P-type first region 11 is formed in a region that extends from the outer edge of the photodiode region 3 to a position away from the proximal end of the gate electrode 4 by a predetermined distance. This predetermined distance, that is, the distance between the gate electrode 4 and the P-type first region 11, is preferably set to 0.2 µm or more. One end of the P-type second region 12 is adjacent to the P-type first region 11, and the other end thereof overlaps the gate electrode 4. However, the P-type second region 12 may be adjacent to each other without overlapping with the gate electrode 4.

In this structure, when the concentration of the P-type first region 11 is represented by C1, the concentration of the P-type second region 12 is represented by C2, and the concentration of the P-type third region 12 is represented by C3, the relationship between the respective concentrations is , C1> C2> C3, or C1 ≒ C2> C3.

Here, in order to obtain the individual imaging device with very few image defects (represented by white defects and dark currents), the dose of B + ion implantation for forming the P-type second region 12 is 2.0E12 /. It is preferable that it is cm <2> or more. Moreover, even if the high concentration P-type first region 11 is diffused below the gate electrode 4 by thermal diffusion, the P-type second region 12 having a lower concentration than the P-type first region 11 can be formed. do.

As for the readout characteristic, since the N-type photodiode region 3 overlaps with the gate electrode 4, the object imaging apparatus capable of low voltage operation is controlled by controlling the amount of B + dose in the P-type third region 13. You can get it. It is preferable that the length of the overlap region between the gate electrode 4 and the photodiode region 3, that is, the distance in the transverse direction in FIG. 1, is set in the range of 0.1 µm to 0.3 µm. In addition, the amount of B + dose for forming the P-type third region 13 is preferably smaller than that of the P-type second region 12.

(Embodiment 2)

2 is a cross-sectional view showing a cell structure of the solid-state imaging device in the second embodiment. About the same part as Embodiment 1 mentioned above, the same reference number is attached | subjected, and description is abbreviate | omitted.

In this embodiment, instead of the P-type second region 12 in the first embodiment, the P-type second A region 14 is formed. The P-type 2A region 14 is characterized in that the bottom of the P-type diffusion layer is deeper than the bottom of the P-type diffusion layer of the P-type first region 11 and the P-type third region 13. In order to make the bottom of the P-type diffusion layer of the P-type 2A region 14 deeper than the P-type first region and the P-type third region, the acceleration energy of ion implantation is increased. That is, when the acceleration energy of the P-type first region 11 is represented by E1 and the acceleration energy of the P-type second A region 14 is represented by E2A and the acceleration energy of the P-type third region 13 is represented by E3, The relationship is E1 ≒ E3 <E2A.

By this structure, in the region where the N-type photodiode region 3 and the gate electrode 4 overlap, the active level occurring near the end of the gate electrode 4 can be deactivated, and the image defect (white defect) , Represented by a dark current) can be further improved.

 (Embodiment 3)

 3 is a cross sectional view showing a cell structure of the solid-state imaging device according to the third embodiment. About the same part as Embodiment 1 mentioned above, the same reference number is attached | subjected, and description is abbreviate | omitted.

In the present embodiment, instead of the P-type second region 12 and the P-type third region 13 in the first embodiment, the P-type 2B region 15 and the P-type 3A region 16 are provided. Formed. The bottom portion of the P-type diffusion layer of the P-type 2B region 15 and the P-type 3A region 16 is located at a position deeper than that of the P-type first region. In order to obtain this structure, the bottom of the P-type diffusion layer of the P-type 2B region 15 and the P-type 3A region 16 is increased by increasing the energy of ion implantation during formation of the P-type diffusion layer. Deeper than (11). That is, when the acceleration energy of the P-type first region 11 is represented by E1, the acceleration energy of the P-type second B region 15 is represented by E2B, and the acceleration energy of the P-type 3A region 16 is represented by E3A, The relationship is E1 <E2B ≒ E3A.

As another method of varying the depth, a method of deepening the bottom of the P-type diffusion layer by diffusing heat downward in the P-type diffusion layer by heat treatment after ion implantation can be used. The heat treatment at this time can also serve as a step of forming the gate oxide film 5. Moreover, a larger effect can be acquired by adding an annealing process to a gate oxidation process. As for annealing temperature at this time, 1050 degreeC or more is preferable. By the addition of the annealing, the active level generated near the end of the gate electrode 4 in the region where the N-type photodiode region 3 and the gate electrode 4 overlap is inactivated. Not only that, but also the stress accumulated up to that time, in particular, the stress accumulated in the element isolation unit 10 is alleviated, and the suppression of image defects (represented by white defects and dark currents) due to crystal defects caused by such stresses is achieved. Effects can also be obtained.

According to the present invention, there is provided a solid-state imaging device and a method of manufacturing the same, in which the readout characteristics at low voltage are good and image defects such as white defects and dark currents are sufficiently suppressed.

Claims (10)

A plurality of N-type photodiode regions for photoelectric conversion of incident light, formed inside a P-type well on a Si substrate, a gate electrode having one end adjacent to each photodiode region, and an N-type adjacent to the other end of the gate electrode A solid-state image having a drain region of and a device isolation region having a Sl (Shal1ow Trench Isolation) structure for separating each of a plurality of elements each of the photodiode region and the set of MOS transistors, the gate oxide film having a thickness of 10 nm or less; In the apparatus, One end of the gate electrode overlaps with the photodiode region, A first region having a first P-type concentration C1 disposed at a predetermined distance from one end of the gate electrode to a surface portion from the upper portion of the photodiode region to the drain region, and one end of the first region; A second region having a P-type second concentration (C2) disposed adjacent to the other end and overlapping with the gate electrode, one end adjacent to the second region, and the other end adjacent to the drain region; A third region having a third P-type concentration C3 disposed therein is formed, The relationship between each concentration is C1> C2> C3 or C1 CC2> C3. The solid-state imaging device characterized by the above-mentioned. The solid-state imaging device according to claim 1, wherein the bottom of the P-type diffusion layer in the second region is deeper than the bottom of the first region and the P-type diffusion layer in the third region. The solid-state imaging device according to claim 1, wherein a bottom of the second region and a P-type diffusion layer of the third region is deeper than a bottom of the P-type diffusion layer of the first region. A plurality of N-type photodiode regions for photoelectric conversion of incident light, formed inside a P-type well on a Si substrate, a gate electrode having one end adjacent to each photodiode region, and an N-type adjacent to the other end of the gate electrode And a device isolation region having an STI structure that separates each of a plurality of elements formed of the respective groups of photodiode regions and MOS transistors, and has a thickness of a gate oxide film of 10 nm or less. In The gate electrode is formed such that one end thereof overlaps with the photodiode region, A first region having a first P-type concentration C1 disposed at a predetermined distance from one end of the gate electrode to a surface portion from the upper portion of the photodiode region to the drain region, and one end of the first region; A second region having a P-type second concentration (C2) disposed adjacent to the other end and overlapping with the gate electrode, one end adjacent to the second region, and the other end adjacent to the drain region; The third region having the third concentration (C3) of the P-type arranged is formed so that the relationship of each concentration is C1> C2> C3, or C1 ≒ C2> C3, The respective concentrations are adjusted by controlling the dose in ion implantation forming the P-type diffusion layer. A plurality of N-type photodiode regions for photoelectric conversion of incident light, formed inside a P-type well on a Si substrate, a gate electrode having one end adjacent to each photodiode region, and an N-type adjacent to the other end of the gate electrode And a device isolation region having an STI structure that separates each of a plurality of elements formed of the respective groups of photodiode regions and MOS transistors, and has a thickness of a gate oxide film of 10 nm or less. In The gate electrode is formed such that one end thereof overlaps with the photodiode region, A first region having a first P-type concentration C1 disposed at a predetermined distance from one end of the gate electrode to a surface portion from the upper portion of the photodiode region to the drain region, and one end of the first region; A second region having a P-type second concentration (C2) disposed adjacent to the other end and overlapping with the gate electrode, one end adjacent to the second region, and the other end adjacent to the drain region; The third region having the third P-type concentrations C3 arranged is formed so that the relationship of each concentration is C1> C2> C3, Characterized by varying the concentration (C1) and the concentration (C2) by diffusing the P-type diffusion layer in the first region under the gate electrode by heat treatment to form the P-type diffusion layer in the second region. The manufacturing method of an imaging device. The P of the second region according to claim 4 or 5, wherein the acceleration energy in the ion implantation at the time of forming the second region is made larger than the time of forming the first region and the third region. The manufacturing method of the solid-state imaging device which makes the bottom part of a type | mold diffused layer deeper than the bottom part of the P-type diffused layer of a said 1st area and a said 3rd area. The said 2nd area | region and 3rd of Claim 4 or 5 by making acceleration energy in ion implantation at the time of forming the said 2nd area | region and a 3rd area | region larger than when forming the said 1st area | region. A method of manufacturing a solid-state imaging device, wherein the bottom of the P-type diffusion layer in the region is deeper than the bottom of the P-type diffusion layer in the first region. The bottom part of the P type diffusion layer of the said 2nd area | region and a 3rd area | region by heat processing after the ion implantation at the time of forming said 2nd area | region and 3rd area | region is a said 1st area | region. The manufacturing method of the solid-state imaging device made deeper than the bottom part of the P-type diffusion layer of this. The manufacturing method of the solid-state imaging device of Claim 8 whose said heat processing is a process in a gate oxide film formation process. The manufacturing method of the solid-state imaging device of Claim 9 which further performs an annealing process of 30 minutes or more at 1050 degreeC to the said gate oxide film formation process.

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