KR100593304B1 - Method of fabrication optoelectronic integrated circuit chip - Google Patents

Abstract

The present invention relates to a method for manufacturing a photonic integrated receiver circuit chip, and more particularly, by using a selective crystal growth method, the light absorption layer thickness of the waveguide type photodetector grows thicker than the thickness of the collector layer of the heterojunction bipolar transistor and is semi-insulated. A method for fabricating a photo-integrated receiver circuit chip in which a waveguide photodetector and a heterojunction bipolar transistor are integrated into a single chip on an InP substrate to simplify the implementation of a waveguide photodetector having high photoelectric conversion efficiency and high speed characteristics. will be.

Optical Communication System, Photonic Integrated Receiver, Waveguide Photodetector, Heterojunction Bipolar Transistor, Insulation Layer Pattern

Description

Method of fabricating optoelectronic integrated circuit chip {Method of fabrication optoelectronic integrated circuit chip}

1 is a cross-sectional view illustrating a light receiving chip incorporating a planar long-wavelength photodetector having a general PiN structure and n + InP / p + InGaAs / n-InGaAs / n + InGaAs heterojunction bipolar transistors.

2 is a cross-sectional view showing a photonic integrated receiver circuit chip according to an embodiment of the present invention.

3A to 3J are cross-sectional views illustrating a method of manufacturing a photonic integrated circuit chip according to an embodiment of the present invention.

*** Explanation of symbols on main parts of drawing ***

100: semi-insulated InP substrate, 210: n + InGaAs sub-collector layer,

210a: n + InGaAs layer, 210b: n + InGaAs subcollector,

215: n-InP layer, 220a: n-InGaAs light absorption layer,

220b: n-InGaAs collector layer, 230: p + InGaAs base layer,

230a: p + InGaAs ohmic layer, 230b: p + InGaAs base,

240: n + InP emitter layer, 240 ': n + InP emitter layer,

250: n + InGaAs ohmic layer, 260: emitter electrode,

270: base electrode, 280: collector electrode,

290: p-electrode, 300: n-electrode,

350,350 ': insulation layer pattern, 400: polymer layer,

500: gold plated film, A: waveguide photodetector,

B: Heterojunction Bipolar Transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a photonic integrated circuit chip. In particular, the optical absorption layer thickness of a waveguide type photodetector is grown thicker than the thickness of the collector layer of a heterojunction bipolar transistor by using a selective crystal growth method. An integrated waveguide photodetector and heterojunction bipolar transistor are integrated into a single chip, and the present invention relates to a method for fabricating a photonic integrated receiver circuit chip which enables a simple implementation of a waveguide photodetector having high photoelectric conversion efficiency and ultrafast characteristics.

In general, conventional optical reception chips mainly used in optical communication systems are p + InGaAs / n-InGaAs / n + InGaAs long-wavelength photodetectors (A) and n + InP having a conventional PiN structure. A heterojunction bipolar transistor (B) having a / p + InGaAs / n-InGaAs / n + InGaAs structure has a single integrated structure on the semi-insulated InP substrate 10.

That is, the long wavelength photodetector A includes an n + InGaAs layer 21a, an n-InGaAs light absorbing layer 22a, and a p + InGaAs ohmic layer 23a sequentially stacked on the semi-insulating InP substrate 10, and p. The p-electrode 29 formed on the + InGaAs ohmic layer 23a and the n-electrode 30 formed on a predetermined region on the n + InGaAs layer 21a are formed.

In addition, the heterojunction bipolar transistor B includes an n + InGaAs subcollector 21b, an n-InGaAs collector layer 22b, a p + InGaAs base 23b, an n + InP emitter 24 and an n + InGaAs ohmic layer. 25 is stacked, the n-InGaAs collector layer 22b and the p + InGaAs base 23b are formed in a predetermined region above the n + InGaAs subcollector 21b, and the n + InP emitter 24 And the n + InGaAs ohmic layer 25 is formed in a predetermined region above the p + InGaAs base 23b. The emitter electrode 26 is formed on the n + InGaAs ohmic layer 25, and the base electrode 27 is formed on a predetermined region above the p + InGaAs base 23b, and the n + InGaAs sub is formed. The collector electrode 28 is formed in the predetermined area | region above the collector 21b.

The polymer layer 40 is formed on the surfaces of the long-wavelength photodetector A and the heterojunction bipolar transistor B formed as described above for protection and electrical insulation, and holes are formed in the polymer layer 40 to expose each electrode. The p-electrode 29 of the photodetector A and the base electrode 27 of the heterojunction bipolar transistor B are connected via an air bridge metal line.

The p + InGaAs / n-InGaAs / n + InGaAs long-wavelength photodetector crystal structure of the simple PiN structure configured as described above is formed by forming the same crystal layer of the base and the subcollector of the heterojunction bipolar transistor, thereby providing a separate layer for the photodetector. Since crystal growth is not necessary, it has been used a lot until now.

On the other hand, in the current high-capacity ultrafast optical communication system, the optical signal is converted into an electrical signal using a photodetector and then amplified. Accordingly, since a receiver having a complicated structure for detecting and amplifying an optical signal is required at the receiving end, it is difficult to manufacture an economical and excellent optical receiver due to high manufacturing cost.

Therefore, in order to construct an economical ultrafast long-distance large-capacity optical communication system, the optical absorption layer is formed thickly by using a selective crystal growth method, which has a high photoelectric conversion efficiency and a high-gain waveguide type photodetector having high-speed characteristics and high-gain amplified transformed electrical signal. Integrating heterojunction bipolar transistors onto a single chip on a semi-insulated InP substrate is essential to fabricate an economical optical receiver that can simplify the fabrication process.

In addition, another problem that occurs in the conventional structure is that the light absorbing layer is made of the surface incident type, when the optical fiber is combined to make a module, the cross section of the optical fiber is widened to cover the entire area of the integrated chip As a result, it has become a major cause of great difficulty in modularization.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to grow a photoabsorption layer thicker than that of a heterojunction bipolar transistor using a selective crystal growth method, thereby increasing photoelectric conversion. The present invention provides a method for manufacturing a photo-integrated receiver circuit chip that can increase efficiency and facilitate alignment with an optical fiber.

Another object of the present invention is to use a selective crystal growth method on a semi-insulated InP substrate to integrate a high speed waveguide photodetector having a thick photoabsorption layer with high photoelectric conversion efficiency and a heterojunction bipolar transistor in a single chip. N + InP / p + InGaAs / n-InGaAs / n + InGaAs heterojunction bipolar transistors that convert light into an electrical signal by means of a single chip integrated with a waveguide photodetector on top of a semi-insulated InP substrate. The present invention provides a method of manufacturing a photo-integrated receiver circuit chip that can be amplified by the optical amplifier to improve reception sensitivity and detection speed.

In order to achieve the above object, an aspect of the present invention, (a) forming a sub-collector layer and a first semiconductor layer on the substrate of the photodetector region and the transistor region; (b) forming insulating layer patterns at different intervals on the photodetector region and the first semiconductor layer of the transistor region; (c) forming a light absorbing layer as a second semiconductor layer between the insulating layer patterns in the photodetector region, and forming a collector layer as the second semiconductor layer thinner than the light absorbing layer between the insulating layer patterns in the transistor region. Doing; (d) removing the insulating layer pattern; And (e) a photodetector comprising the subcollector layer, the light absorbing layer, and the base layer in the photodetector region, and a transistor comprising the subcollector layer, the collector layer, the base layer, and the emitter layer in the transistor region. It provides a method for manufacturing a photonic integrated receiving circuit chip comprising the step of forming a.

Here, the second semiconductor layer is made of an n-InGaAs layer, preferably formed by metal organic chemical vapor deposition (MOCVD).

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. This embodiment is not intended to limit the scope of the invention, but is presented by way of example only.

2 is a cross-sectional view illustrating a photoelectric integrated circuit chip according to an embodiment of the present invention.

Referring to FIG. 2, the waveguide photodetector A and the heterojunction bipolar transistor B are formed on the semi-insulated InP substrate 100 in a single integrated structure.

Here, the waveguide type photodetector (A) is n + InGaAs layer 210a, n-InP layer 215a, n-InGaAs light absorption layer 220a sequentially stacked on a predetermined region on the semi-insulating InP substrate 100. And a p + InGaAs ohmic layer 230a. The n-InGaAs light absorption layer 220a and the p + InGaAs ohmic layer 230a are formed in a predetermined region on the n-InP layer 215a, which is an optional sacrificial layer. The p-electrode 290 is formed in a predetermined region above the p + InGaAs ohmic layer 230a, and the n-electrode 300 is formed in a predetermined region above the n + InGaAs layer 210a.

The heterojunction bipolar transistor B includes n + InGaAs subcollector 210b, n-InP layer 215b, n-InGaAs collector layer 220b, p + InGaAs base 230b, n + InP which are sequentially stacked. Emitter 240'and n + InGaAs ohmic layer 250. The n-InGaAs collector layer 220b and the p + InGaAs base 230b are formed on the n-InP layer 215b, which is an optional sacrificial layer, and the n + InP emitter 240 'and the n + InGaAs ohmic layer 250. ) Is formed in a predetermined region above the p + InGaAs base 230b.

In addition, the emitter electrode 260 is formed on the n + InGaAs ohmic layer 250, the base electrode 270 is formed on a predetermined region on the p + InGaAs base 230b, and the n + InGaAs sub-collector ( The collector electrode 280 is formed in a predetermined region above the upper portion 210b.

Meanwhile, the polymer layer 400 is formed on the entire structure to protect the surface of the waveguide type photodetector A and the heterojunction bipolar transistor B and to electrically insulate the hole, so that each electrode is exposed in the polymer layer 400. Is formed. The p-electrode 290 of the photodetector A and the base electrode 270 of the heterojunction bipolar transistor B are connected to each other through an air bridge metal line formed of a gold plated film 500 in the hole.

The thickness of the n-InGaAs light absorbing layer 220a of the waveguide photodetector A is formed to be thicker than the thickness of the n-InGaAs collector layer 220b of the heterojunction bipolar transistor B, thereby absorbing light on the cross section of the waveguide photodetector. The amount of bonds is increased to increase the photoelectric conversion efficiency.

3A to 3J are cross-sectional views illustrating a method of manufacturing a photonic integrated circuit chip according to an embodiment of the present invention.

Referring to FIG. 3A, after the n + InGaAs sub-collector layer 210 and the optional sacrificial layer n-InP layer 215 are sequentially formed on the semi-insulated InP substrate 100, the n-InP layer 215 is formed. The insulating layer patterns 350 and 350 ′ spaced apart from each other at predetermined intervals are formed on the upper side of the substrate. In this case, the insulating layer patterns 350 and 350 ′ of the waveguide type photodetector (A) region are grown at about 600 ° C. using, for example, metal organic chemical vapor deposition (MOCVD) using Si 3 N x material. Let's do it.

Referring to FIG. 3B, a selective crystal growth method may be performed on the n-InP layer 215 between the insulating layer patterns 350 and 350 ′ and the upper surface of the n-InP layer 215 on one side of the insulating layer pattern 350 ′. By growing the n-InGaAs layer using metal organic chemical vapor deposition (MOCVD), the n-InGaAs light absorption layer 220a is formed in the waveguide type photodetector (A) and the heterojunction bipolar transistor (B) region. A relatively thin n-InGaAs collector layer 220b is formed. That is, the gap between the insulating layer patterns 350 and 350 'of the waveguide type photodetector A region is formed to be narrower than that of the heterojunction bipolar transistor B region, thereby forming the insulating layer pattern of the waveguide type photodetector A region. The thickness of the n-InGaAs light absorbing layer 220a formed between the 350 and 350 'is thicker than the n-InGaAs collector layer 220b of the heterojunction bipolar transistor (B) region.

Meanwhile, the waveguide type photodetector A with optimized photoelectric conversion efficiency may be manufactured according to the interval between the insulating layer patterns 350 and 350 'and the thickness and width of the insulating layer patterns 350 and 350'. have. At this time, when the widths of the insulating layer patterns 350 and 350 'are widened, the number of elements moving from the insulating layer patterns 350 and 350' to the growth plane increases, resulting in a thicker thickness, and as a result, the photoelectric conversion efficiency is improved. .

For example, the gaps and widths of the insulating layer patterns 350 and 350 'are grown to about 20 μm and 100 μm, respectively, so that the n-InGaAs light absorbing layer 220a is grown between the insulating layer patterns 350 and 350'. The thickness of (eg, about 10000 GPa) is grown about twice as thick as the thickness (eg, about 5000 GPa) of the n-InGaAs collector layer 220b grown in other portions. By using), it is possible to fabricate a photo-integrated receiver circuit which has excellent light absorption efficiency and simultaneously satisfies an improved amplification characteristic.

Referring to FIG. 3C, after removing the insulating layer patterns 350 and 350 ′, only the p + InGaAs base layer 230, the n + InP emitter layer 240, and the ohmic characteristics are formed on top of the resultant. The n-InGaAs light absorption layer 220a of the waveguide-type photodetector A is formed on the same wafer, that is, the plane of the semi-insulated InP substrate 100 by sequentially forming the n + InGaAs ohmic layer 250 for lifting. The crystal structure of the single chip photo-integrated receiver circuit thicker than the n-InGaAs collector layer 220b of (B) is completed.

Meanwhile, the n + InGaAs ohmic layer 250 of the present invention is formed on top of the n + InP emitter layer 240, but is not limited thereto. The n + InGaAs ohmic layer 250 is formed on the n + InP emitter layer 240. 250) may not be formed.

After the growth of the crystal structure for fabrication of a single-chip photoelectric integrated reception circuit having excellent photoelectric conversion efficiency as described above, the heterojunction bipolar transistor (B) part is first manufactured by using an insulating layer and a conventional photolithography process. do.

Referring to FIG. 3D, first, the photodetector (A) region and the heterojunction bipolar transistor (B) region are determined. In order to isolate the waveguide photodetector (A) and the heterojunction bipolar transistor (B), the insulating film is etched by using an insulating film formation and photolithography process, and then an n + InGaAs ohmic layer using a reactive ion vapor phase etching method. N + InGaAs ohmic layer 250, n + InP emitter layer 240, p + InGaAs base layer 230, n-InP layer 215, from 250 to a predetermined thickness of semi-insulated InP substrate 100; The n + InGaAs sub-collector layer 210 is sequentially removed to expose the semi-insulated InP substrate 100.

Referring to FIG. 3E, after forming an etching mask that closes the waveguide-type photodetector (A) region and exposes the heterojunction bipolar transistor (B) region, an n + InGaAs ohmic layer 250 and an n + InP emi The emitter layer 240 is selectively etched to form a mesa n + InP emitter 240 ′, and an emitter electrode 260 is formed on the n + InGaAs ohmic layer 250.

Meanwhile, although the emitter electrode 260 of the present invention is formed on the n + InGaAs ohmic layer 250, the present invention is not limited thereto, and the n + InP emitter layer is not formed in the n + InGaAs ohmic layer 250. It may be formed directly on the 240.

Referring to FIG. 3F, after exposing the surface of the p + InGaAs base 230b using a photolithography process, the base electrode 270 having a Ti / Pt / Au structure using a deposition and lift off process To form.

Referring to FIG. 3G, the p + InGaAs base 230b, the n-InGaAs collector layer 220b, and the n-InP layer 215b outside the base electrode 27 are removed using a photolithography process, and n is removed. After exposing the top of the + InGaAs sub-collector 210b, a collector electrode 280 having a Ti / Pt / Au structure is formed on the exposed n + InGaAs sub-collector 210b by using a deposition and lift-off process. As a result, the heterojunction bipolar transistor B is completed.

The emitter electrode 260, the base electrode 270, and the collector electrode 280 may be simultaneously formed in one process.

Referring to FIG. 3H, in order to fabricate the waveguide photodetector A, the heterojunction bipolar transistor B region is closed, and an etching mask for exposing the waveguide photodetector A region is formed of an insulating film, and then the waveguide The n + InGaAs ohmic layer 250 and the n + InP emitter layer 240 in the region of the photodetector A are etched to planarize the surface.

Referring to FIG. 3I, the n + InP emitter layer 240, the p + InGaAs ohmic layer 230a, the n-InGaAs light absorbing layer 220a, and n of the waveguide type photodetector (A) region are treated by a photolithography process and an etching process. By removing the predetermined regions of the -InP layer 215a and the n + InGaAs layer 210a to expose the n + InGaAs layer 210a, a predetermined portion of the photodetector A region is formed with a waveguide structure.

Thereafter, a p / electrode 290 having a Ti / Pt / Au structure is formed in a predetermined region on the p + InGaAs ohmic layer 230a by using a deposition and lift-off process. In addition, after the n-electrode 300 having a Ti / Pt / Au structure is formed in a predetermined region on the exposed n + InGaAs layer 210a by using a deposition and lift-off process, a heat treatment process is performed. The photodetector A is completed. Meanwhile, although the p-electrode 290 of the present invention is formed on the p + InGaAs ohmic layer 230a, the p-electrode 290 is not limited thereto, and the n-InGaAs light absorption layer is not formed in the p-InGaAs ohmic layer 230a. It may be formed directly on the upper portion of (220a).

Referring to FIG. 3J, the polymer layer 400 is formed on the entire upper surface of the waveguide photodetector A and the heterojunction bipolar transistor B for surface protection and electrical insulation. To form a hole in 400). The gold plating film 500 is formed inside the hole to form an air bridge metal line connecting the p-electrode 290 of the photodetector A and the base electrode 270 of the heterojunction bipolar transistor B. This completes a photo-integrated receiver circuit chip in which a waveguide photodetector A and n + InP / p + InGaAs / n-InGaAs / n-InP / n + InGaAs heterojunction bipolar transistors B are integrated.

By forming the n-InGaAs light absorption layer 220a thicker than the n-InGaAs collector layer 220b by the selective crystal growth method (MOCVD) using the insulating layer patterns 350 and 350 'as described above, the n-InGaAs light The amount of light absorbed in the cross section of the absorbing layer 220a is increased to increase the photoelectric conversion efficiency.

In other words, while optimizing the characteristics of the heterojunction bipolar transistor B, the waveguide type photodetector A has improved photoelectric conversion efficiency due to the thick n-InGaAs light absorption layer 220a.

Therefore, when the n-InGaAs light absorption layer 220a of the waveguide type photodetector A is designed, the width of the insulating layer patterns 350 and 350 'is optimized, thereby optimizing the waveguide type photodetector A with optimized photoelectric conversion efficiency. I can produce it.

Although a preferred embodiment of a method for manufacturing a photonic integrated receiver circuit chip according to the present invention has been described above, the present invention is not limited thereto, but the scope of the claims and the detailed description of the invention and the accompanying drawings are various. It is possible to carry out modifications and this also belongs to the present invention.

According to the manufacturing method of the photonic integrated receiver circuit chip of the present invention as described above, by using a selective crystal growth method, the absorption layer thickness of the waveguide type photodetector grows thicker than the thickness of the collector layer of the heterojunction bipolar transistor, thereby improving photoelectric conversion efficiency. There is an advantage that can increase the, and facilitate the alignment with the optical fiber.

In addition, by manufacturing the structure of the photodetector according to the present invention in the waveguide type, there is an advantage that the alignment of the optical fiber and the photodetector is very easy because the optical fiber oil is aligned in terms of.

In addition, by integrating the waveguide photodetector and the heterojunction bipolar transistor according to the present invention into a single chip, the structures of the optimized photodetector and the heterojunction bipolar transistor, which are independent in the vertical direction, can be simultaneously grown, thereby requiring other crystal growth. This has the advantage of simplicity over a single chip fabrication process of the device.

Claims (8)

(a) forming a subcollector layer and a first semiconductor layer on substrates of the photodetector region and the transistor region; (b) forming insulating layer patterns at different intervals on the photodetector region and the first semiconductor layer of the transistor region; (c) forming a light absorbing layer as a second semiconductor layer between the insulating layer patterns in the photodetector region, and forming a collector layer as the second semiconductor layer thinner than the light absorbing layer between the insulating layer patterns in the transistor region. Doing; (d) removing the insulating layer pattern; And (e) forming a photodetector comprising the subcollector layer, the light absorbing layer and the base layer in the photodetector region, and forming a transistor comprising the subcollector layer, the collector layer, the base layer and the emitter layer in the transistor region Forming and manufacturing a single integrated structure comprising the step of manufacturing a photonic integrated circuit chip. The method of claim 1, wherein step (e) (e1) forming the base layer and the emitter layer on the entire upper surface after removing the insulating layer pattern; (e2) separating the photodetector region and the transistor region, respectively; (e3) forming a transistor having a structure in which the sub-collector layer, the first semiconductor layer, the collector layer, the base layer, and the emitter layer are stacked in the transistor region; And (e4) forming a photodetector having a structure in which the subcollector layer, the first semiconductor layer, the light absorbing layer, and the base layer are stacked in the photodetector region. Manufacturing method. The method of claim 2, further comprising forming an ohmic layer on the emitter layer in the step (e1). The method of claim 2, wherein step (e3), (e3-1) selectively etching the emitter layer in the transistor region to form a mesa-type emitter, and then forming an emitter electrode on the emitter layer; (e3-2) forming a base electrode on a predetermined region above the base layer; And (e3-3) The base layer, the collector layer, and the first semiconductor layer of the outer side of the base electrode are selectively removed, and an upper portion of the sub collector layer is exposed, and then a collector is disposed in a predetermined region above the sub collector layer. A method for manufacturing a photonic integrated circuit chip, comprising the step of forming an electrode. The method of claim 2, wherein step (e4), (e4-1) removing the emitter layer and the base layer of the photodetector region; (e4-2) determining a waveguide type photodetector by exposing the subcollector by removing predetermined regions of the light absorbing layer, the first semiconductor layer, and the subcollector layer formed in the photodetector region; And (e4-3) forming a p-electrode in a predetermined region above the light absorption layer, and then forming an n-electrode in a predetermined region above the exposed sub-collector layer. Chip manufacturing method. The method of claim 2, wherein the step (e2) comprises removing a predetermined thickness of the emitter layer, the base layer, the first semiconductor layer, the subcollector layer, and the substrate at the interface of the photodetector region and the transistor region. Method for manufacturing a photoelectric integrated circuit chip, characterized in that consisting of. The method of claim 1, wherein an interval between the insulating layer patterns in the photodetector region is smaller than an interval between the insulating layer patterns in the transistor region. The method of claim 1, wherein the second semiconductor layer comprises an n-InGaAs layer and is formed by metal organic chemical vapor deposition (MOCVD).

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