KR100580388B1 - Liquid Crystal Display and Manufacturing Method Thereof - Google Patents

Abstract

A polysilicon pattern is formed on a transparent insulating substrate, and a gate insulating film is covered thereon. The gate line is formed in the horizontal direction on the gate insulating film, and the gate electrode extends from the gate line to overlap the polycrystalline silicon pattern. In addition, the sustain electrode line is formed in the horizontal direction and partially overlaps with the polycrystalline silicon pattern. In this case, the polycrystalline silicon pattern is formed of an undoped channel region located under the gate electrode, a source and drain region doped with a high concentration n-type outside the channel region, and an undoped doped region disposed under the sustain electrode line and adjacent to the drain region. It is divided into a holding region and a conductive region adjacent to the drain region and the holding region and heavily doped with p-type ions. The interlayer insulating film covers the gate line, the gate electrode and the sustain electrode line, and a contact hole exposing the source region is formed in the interlayer insulating film and the gate insulating film, and a data line connected to the source region through the contact hole is formed on the interlayer insulating film. . A passivation film is formed thereon, and a transparent pixel electrode contacting the drain region is formed on the passivation film through a contact hole formed in the passivation film, the interlayer insulating film, and the gate insulating film so as to expose a part of the drain region.

Description

Liquid Crystal Display and Manufacturing Method Thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a manufacturing method thereof, and more particularly, to a storage capacitor and a method of forming the same.

The liquid crystal display includes a data line for transmitting an image signal, a gate line for transmitting a scan signal, a thin film transistor as a three-terminal switching element, a liquid crystal capacitor, and a storage capacitor.

When the open voltage is applied to the gate of the thin film transistor, charge is charged to the liquid crystal capacitor, and the charged charge is maintained until the gate open voltage is applied to the thin film transistor again. In general, when the gate voltage changes from the open state to the closed state, the pixel voltage drops, and the sustain capacitor plays a role in reducing this variation.

Amorphous or polycrystalline silicon is mainly used as a semiconductor layer of the thin film transistor. When polycrystalline silicon is used, the field effect mobility is greater than that of amorphous silicon, so that a better display image quality can be obtained. It can be integrated at the same time as the partial formation, thereby reducing the size of the liquid crystal display.

On the other hand, the process itself is more complicated than using amorphous silicon, which increases the process cost. Therefore, it is important to reduce the number of processes in order to reduce these process costs. However, conventionally, when forming a silicon layer or a gate poly layer of a thin film transistor to form a storage capacitor required for a pixel, a doping step is separately performed to form a portion to be a storage electrode and to use it as a storage electrode. Doping requires an exposure process using a mask.

As mentioned above, it is advantageous to omit the doping process for forming the sustain electrode in order to reduce the process cost.

An object of the present invention is to simplify the manufacturing process of a liquid crystal display device having a storage capacitor.

Another object of the present invention is to provide a liquid crystal display device in which stable image quality is realized due to less variation in holding capacitance.

In order to solve this problem, in the liquid crystal display according to the present invention, the sustain electrode line overlaps the polycrystalline silicon pattern, and the p-type high concentration is adjacent to the drain region heavily doped with n-type polycrystalline silicon pattern outside the edge of the sustain electrode line. The doped conductive region is formed.

As described above, in such a structure having both the p-type and n-type doped regions in the outer polycrystalline silicon pattern of the sustain electrode line, since the sustain capacitance is formed regardless of the polarity of the voltage applied between the sustain electrode line and the drain region, the common voltage is applied to the sustain electrode line. It can be used by applying.

In order to form the liquid crystal display, n-type ions are implanted using a photosensitive pattern formed so that a portion of the gate electrode and the sustain electrode line are exposed to form a mask to form a high concentration of source and drain regions outside the edges of the gate electrode and the sustain electrode line. P-type ions are heavily doped with a photosensitive pattern covering the source and drain regions to form a p-type conductive region adjacent to the drain region.

Since the p-type conductive region is formed in the step of forming the p-type thin film transistor of the driving circuit, no additional process is required.

In consideration of the electrical characteristics at the junction of the drain region and the conductive region, a metal pattern connecting the two regions may be further formed. In this case, the metal pattern is preferably formed of the same material as the data line.

Next, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that a person skilled in the art may easily implement the present invention.

1 is a cross-sectional view of a liquid crystal display device having a storage capacitor according to a first embodiment of the present invention.

As shown in FIG. 1, a polycrystalline silicon pattern 100 is formed on a substrate 1, a gate insulating film 2 is covered thereon, and a gate electrode 210 and a storage electrode line (on the gate insulating film 2 are formed thereon). 220 is formed.

In this case, the polycrystalline silicon pattern 100 may be formed of the undoped channel region 102 formed under the gate electrode 210, and the source and drain regions 101 and 103 doped with a high concentration n-type outside the channel region 102. ), An undoped sustain region 105 adjacent to the drain region 103 and adjacent to the drain region 103 and an n-type adjacent to the sustain region 105 and the same as the source and drain regions 101 and 103. Ions are divided into conductive regions 106 doped at the same concentration.

The interlayer insulating film 3 covers the gate electrode 210 and the storage electrode line 220, and a contact hole C1 exposing the source region 101 is formed in the interlayer insulating film 3 and the gate insulating film 2. The data line 310 is formed on the interlayer insulating layer 3, and the data line 310 is connected to the source region 101 through the contact hole C1, and the passivation layer 4 is formed on the data line 310. Is formed. A contact hole C2 exposing a part of the drain region 103 is formed in the protective film 4, the interlayer insulating film 3, and the gate insulating film 2, and is connected to the drain region 103 through the contact hole C2. The pixel electrode 400 to be formed is formed on the protective film 4.

In the liquid crystal display, when the gate open voltage is applied to the gate line 210, the channel voltage 102 is opened and the signal voltage transmitted to the source region 101 through the data line 310 is transferred to the drain region 103 and the pixel. It is delivered to the electrode 400. At this time, when the voltage V _st applied to the storage electrode line 220 is greater than the signal voltage V _d transferred to the drain region 103, the storage region 105 is turned on to drain the region. Current flows to the holding region 105 surface from the 103 side toward the conductive region 106. Therefore, the storage capacitor is formed between the storage electrode line 220 and the storage region 105.

As such, the voltage applied to the storage electrode line 220 to form the storage capacitor and the storage capacitance value formed according to the applied voltage are shown in FIGS. 2 and 3, respectively.

FIG. 2 is a waveform diagram illustrating the data signal voltage V _d of FIG. 1 and the signal voltage V _st applied to the sustain electrode line, and FIG. 3 is a diagram illustrating the drain region 105 and the sustain electrode line 220 of FIG. 1. It is a graph showing the value of the holding capacitance according to the applied voltage.

As shown in FIG. 2, the data signal voltage V _d having the polarity continuously inverted is applied to the drain region 103 of FIG. 1, and the sustain electrode line 220 is applied to the common electrode of the upper color filter substrate. The common voltage V _com is applied or a voltage different from the common voltage is applied.

When the common voltage V _com is applied to the storage electrode line 220, a period V _com > V _d , that is, a data signal in which the voltage applied to the storage electrode line 220 is greater than the voltage applied to the drain region 103. In the period in which the voltage has a negative polarity, since the storage region 105 is turned on, a storage capacitor is formed between the storage electrode line 220 and the storage region 105. However, in the period V _com < V _d , that is, in the period in which the data signal voltage has a positive polarity, the storage region 105 is less than the voltage applied to the storage electrode line 220. It is turned off and no holding capacity is formed.

Accordingly, in order to use a portion of the non-doped storage region 105 under the storage electrode line 220 as one electrode of the storage capacitor, the voltage V _st applied to the storage electrode line 220 is applied to the data signal voltage V _d . It should be set larger.

As shown in FIG. 2, as the data signal voltage V _d is reversed with negative and positive polarities, the signal V _st applied to the storage electrode line 220 and the data signal voltage applied to the drain region 103 ( Since the difference V _c of V _d ) has a positive value of V ₂ and V ₁ , a storage capacitor is formed between the storage electrode line 220 and the storage region 105.

When the signal as shown in FIG. 2 is applied to the storage electrode line 220, as shown in FIG. 3, as long as the data signal voltage V _d is applied to the drain region 103, a storage capacitor having a size of C ₁ or C ₂ is formed. do. At this time, as the difference V _c between the signal V _st and the data signal voltage V _d applied to the storage electrode line 220 increases, a larger storage capacitor C _st is formed.

In this first embodiment, a separate voltage other than the common voltage must be additionally used to form the storage capacitor, and since the voltage has a larger value than the data signal voltage V _d by a certain amount or more, the gate in which the storage capacitor is formed. Electrical stress is greatly generated in the insulating film 2. In addition, when the data signal voltage V _d is inverted, the change of the holding capacitors C ₁ and C ₂ is severe, resulting in a large variation in the kick back voltage.

An embodiment for improving this point is shown in FIGS. 4 and 5.

4 is a plan view of a liquid crystal display having a storage capacitor according to another exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along line VV ′ of FIG. 4.

As shown in FIG. 4 and FIG. 5, the polysilicon pattern 100 is formed on the transparent insulating substrate 1, and the gate insulating film 2 is covered thereon. The gate line 200 is formed in the horizontal direction on the gate insulating layer 2, and the gate electrode 210 extends from the gate line 200 to overlap the polycrystalline silicon pattern 100. In addition, the storage electrode line 220 is formed in the horizontal direction and partially overlaps the polycrystalline silicon pattern 100.

In this case, the polycrystalline silicon pattern 100 may be formed of the undoped channel region 102 under the gate electrode 210, and the source and drain regions 101 and 103 doped with a high concentration n-type outside the channel region 102. , An undoped storage region 105 positioned below the storage electrode line 220 and adjacent to the drain region 103, and adjacent to the drain region 103 and the storage region 105, and have a high concentration of p-type ions. It is divided into a doped conductive region 107. Although not shown, the electrical characteristics at the junction of the two regions 103 and 107 are connected by connecting the drain region 103 doped with n type and the conductive region 107 doped with p type with a metal for data wiring. Can be improved.

The interlayer insulating film 3 covers the gate line 200, the gate electrode 210, and the storage electrode line 220, and the contact hole C1 exposing the source region 101 includes the interlayer insulating film 3 and the gate insulating film 2. ) The data line 310 is formed in the vertical direction on the interlayer insulating layer 3, and a part thereof extends to be connected to the source region 101 through the contact hole C1.

A protective film 4 is formed on the interlayer insulating film 3 on which the data line 310 is formed, and the contact hole C2 exposing a part of the drain region 103 is provided with the protective film 4, the interlayer insulating film 3, and the like. It is drilled through the gate insulating film 2.

A transparent pixel electrode 400 is formed on the passivation layer 4 in the pixel area PX defined by the gate line 200 and the data line 310 intersecting. The pixel electrode 400 is provided with a contact hole C2. It is connected to the drain region 103 through.

As in the first embodiment, when the gate open voltage is applied to the gate electrode 210, the channel region 102 is opened by the data signal voltage transferred to the source region 101 through the data line 310. The voltage is transferred to the drain region 103 and the pixel electrode 400. At this time, when a predetermined voltage is applied to the storage electrode line 220, a voltage difference occurs between the storage electrode line 220 and the drain region 103, and a current flows on the surface of the storage region 105. Therefore, the storage capacitor is formed between the storage electrode line 220 and the storage region 105.

Unlike the first embodiment, in the second embodiment, since the drain region 103 and the conductive region 107 doped with n-type and p-type, respectively, are adjacent to each other outside the holding region 105, the data signal voltage The storage capacitor can be formed by applying the common voltage V _com to the storage electrode line 220 regardless of the polarity of the.

FIG. 6 is a waveform diagram illustrating a signal voltage applied between a data signal voltage applied to the drain region of FIG. 4 and a storage electrode line, and FIG. 7 illustrates a sustain according to a change of a voltage applied between the drain region and sustain electrode line of FIG. It is a graph showing the value of the capacity.

As shown in FIGS. 6 and 7, when the common voltage V _com is applied to the storage electrode line 220, the data signal voltage V _d is smaller than the common voltage V _com applied to the storage electrode line 220. At V _com > V _d ), a voltage difference of V ₃ is generated between the storage electrode line 220 and the drain region 103, and electrons move from the n-type doped drain region 103 to the storage region 105. Therefore, the storage capacitor C ₃ is formed between the storage electrode line 220 and the storage region 105.

In addition, the storage electrode line 220 and the drain are disposed in a section V _com <V _{d in} which the common voltage V _com applied to the storage electrode line 220 is smaller than the data signal voltage V _d applied to the drain region 103. A voltage difference of V ₄ (= V ₃ ) occurs between the regions 103, wherein holes move from the p-type doped conductive region 107 into the holding region 105 to maintain the holding region 105 and the holding region 105. The storage capacitor C ₃ is formed between the electrode lines 220.

As shown in FIG. 7, the holding capacitor C _st having the same value is always formed regardless of the inversion of the data signal voltage V _d .

As described above, in the second embodiment, since the common voltage is used to form the holding capacitor, it is not necessary to use a separate voltage. Since the common voltage maintains the average value of the data signal voltage V _d , the value is kept relatively small. The electrical stress generated at the portion of the gate insulating film 2 where the capacitance is formed is small. In addition, even when the data signal voltage V _d is inverted, the holding capacitor C _st has a substantially constant value, so that the variation of the kick back voltage is small, thereby achieving stable image quality.

Next, a method of manufacturing the liquid crystal display according to the present invention for implementing such a structure will be described with reference to FIGS. 8A to 8G.

As shown in FIG. 8A, the polysilicon pattern 100 is formed on the transparent insulating substrate 1, and then the gate insulating film 2 is formed.

As shown in FIG. 8B, the gate wiring metal is sequentially deposited and patterned to form the gate line 200, the gate electrode 210, and the storage electrode line 220.

As illustrated in FIG. 8C, the photosensitive film 10 is coated and patterned to form the photosensitive film 10 to expose the polycrystalline silicon pattern 100 around the gate electrode 210. In this case, the photoresist film 10 is formed to expose a part of the storage electrode line 220 from the side where the gate electrode 210 is formed.

Next, the source and drain regions 101 and 103 are formed in the polycrystalline silicon pattern 100 outside the gate electrode 210 and the storage electrode line 220 by injecting a high concentration of n-type ions using the photosensitive film 10 as a mask. After that, the photosensitive film 10 is removed. In this step, each of the undoped channel regions 102 is formed under the gate electrode 210, and a portion of the undoped storage region 105 is formed under the storage electrode line 220.

As shown in FIG. 8D, a photosensitive material is coated and patterned to form a photosensitive film 20 to cover a portion of the n-type doped polycrystalline silicon pattern 100, and then the photosensitive film 20, the storage electrode line 220, and the like. The high concentration p-type ions are implanted using the mask to form the p-type conductive region 107 adjacent to the drain region 103.

As shown in FIG. 8E, the interlayer insulating film 3 is deposited and etched to form a contact hole C1 exposing the source region 101. Next, after the metal layer for data wiring is deposited, the data line 310 connected to the source region 101 is formed through the contact hole C1.

In the forming of the contact hole C1, the contact hole exposing the drain region 103 and the p-type conductive region 107 is formed, respectively, and the drain region 103 and the P in the step of patterning the data line 310. It is also possible to pattern the metal pattern connecting the type conductive region 107 through the contact hole.

Next, as shown in FIG. 8F, the protective film 4 is deposited and patterned to form a contact hole C2 exposing the drain electrode 103.

As shown in FIG. 8G, the ITO material is deposited and patterned on the passivation layer 4 to connect the drain region 103 and the contact hole C2 to partially overlap the storage electrode line 220. Form.

As such, the n-type doped drain region and the p-type doped conductive region are formed adjacent to each other on the outside of the holding region 105 overlapping the storage electrode line 220 to form the storage capacitor, and the conductive region is driven. By forming in the process of forming the p-type thin film transistor of the circuit, a separate ion implantation process for forming the storage capacitor can be omitted.

As described above, the liquid crystal display and the manufacturing method thereof according to the present invention do not require a separate ion implantation process for forming the storage capacitance, so the process is reduced. In addition, since the common voltage is used to form the storage capacitor, there is no need to provide a separate voltage source, the electrical stress generated at the gate insulating film region near the formation of the storage capacitor is small, and the variation in the storage capacitance is small. Therefore, stable image quality can be realized.

1 is a cross-sectional view of a liquid crystal display having a storage capacitor according to an embodiment of the present invention;

2 is a waveform diagram illustrating a data signal voltage applied to a drain region of FIG. 1 and a signal voltage applied to a sustain electrode line.

3 is a graph illustrating a value of a storage capacitor according to a voltage applied between the drain region and the storage electrode line of FIG. 1;

4 is a plan view of a liquid crystal display having a storage capacitor according to another embodiment of the present invention;

5 is a cross-sectional view taken along line VV ′ of FIG. 4;

6 is a waveform diagram illustrating a signal voltage applied between a data signal voltage applied to the drain region of FIG. 4 and a sustain electrode line;

FIG. 7 is a graph illustrating values of the storage capacitance according to the change of the voltage applied between the drain region and the storage electrode line of FIG. 4.

8A to 8G are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to an exemplary embodiment of the present invention, according to a process sequence.

Claims (7)

Transparent insulation substrate, A doped source and drain region formed on the substrate and heavily doped with n-type, an undoped channel region located between the source and drain regions, an undoped sustain region adjacent to the drain region and the drain region; A polycrystalline silicon layer adjacent to the holding region and including a conductive region heavily doped with a p-type, A gate insulating film covering the polycrystalline silicon layer, A gate electrode formed on the gate insulating layer over the channel region; A storage electrode line formed on the gate insulating film above the storage region; Liquid crystal display comprising a. In claim 1, An interlayer insulating film covering the gate electrode and the storage electrode line; A gate line formed on the interlayer insulating layer and electrically connected to the source region; A protective insulating film formed on the interlayer insulating film, A pixel electrode formed on the protective insulating layer and electrically connected to the drain region; Liquid crystal display further comprising. In claim 2, And a metal pattern connecting the drain region and the conductive region and formed on the interlayer insulating layer. In claim 3, The metal pattern is formed of the same material as the data line. Forming a polycrystalline silicon pattern on the transparent insulating substrate, Forming a gate insulating film on the polycrystalline silicon pattern, Depositing a gate wiring metal film on the gate insulating film; Patterning the gate wiring metal film to form a gate electrode and a sustain electrode line; Applying a first photoresist film covering the gate electrode and the storage electrode line; Patterning the first photoresist layer to form a first photosensitive pattern such that a portion of the gate electrode and the sustain electrode line are exposed; N-type ions are implanted using the first photosensitive pattern as a mask to form a high concentration source and drain region outside the edges of the gate electrode and the storage electrode line in the polycrystalline silicon pattern, and an undoped channel under the gate electrode. Forming an area, Applying a second photoresist film covering the gate electrode and the storage electrode line; Patterning the second photoresist layer to form a second photoresist pattern covering the source and drain regions; Doping a high concentration of p-type ions using the second photosensitive pattern as a mask to form a heavily doped conductive region in the polycrystalline silicon pattern adjacent to the drain region and out of the storage electrode line Method of manufacturing a liquid crystal display comprising a. In claim 5, Depositing an interlayer insulating film covering the gate line and the storage electrode line; Patterning the interlayer insulating film and the gate insulating film to form a first contact hole exposing the source region; Depositing a metal for data wiring on the interlayer insulating film; Patterning the data wire metal to form a data line connected to the source region through the first contact hole; Stacking a protective film covering the data line; Patterning the passivation layer, the interlayer insulating layer, and the gate insulating layer to form a second contact hole exposing the drain region; Method of manufacturing a liquid crystal display device further comprising. In claim 6, Patterning the interlayer insulating film and the gate insulating film to form third and fourth contact holes exposing the drain region and the conductive region; Patterning the metal for data wiring to form a metal pattern connecting the drain region and the conductive region through the third and fourth contact holes; Method of manufacturing a liquid crystal display device further comprising.