KR100247270B1 - A liquid crystal display having a storage capacitor and manufacturing method thereof - Google Patents

Abstract

A silicon layer is formed on a transparent insulating substrate, and a gate insulating film is formed thereon. On the gate insulating film, the gate electrode and the storage electrode line cross the silicon layer by a predetermined length. The width of the storage electrode line is narrower than the width of the silicon layer and the edge of the storage electrode line is formed inside the silicon layer. The silicon layer includes a undoped channel region below the gate electrode, doped source and drain regions on both sides thereof, a doped sustain region adjacent to the drain region and located below the sustain electrode, and a drain region over the upper edge of the sustain region. The doped edge region connected to the doped edge region is located, and the doped edge region, which is isolated from the drain region, is located in the entire lower portion of the lower edge. The charge storage layer is formed by applying a voltage greater than or equal to the threshold voltage of the thin film transistor to the storage region to serve as an electrode. In addition, the charges in the drain region are first moved to the doped edge region and then to the holding region to reduce the resistance of the holding region.

Description

Liquid crystal display device having a storage capacitor and its manufacturing method

The present invention relates to a liquid crystal display device having a storage capacitor and a manufacturing method thereof.

In general, a thin film transistor liquid crystal display device includes a data line for transmitting an image signal, a gate line for transmitting a scan signal, a thin film transistor as a three-terminal switching element, a liquid crystal capacitor, and a storage capacitor. According to the structure of the independent wiring method or the front gate type liquid crystal display device. The former is a case where an independent wiring is formed in a pixel for forming a storage capacitor, and the latter is a case where a gate line of the front end is used.

Next, a driving principle of an independent wiring type liquid crystal display device and a structure of a conventional liquid crystal display device will be described with reference to the accompanying drawings.

1 is an equivalent circuit diagram of a conventional independent wiring type liquid crystal display device.

The plurality of gate lines G1 and G2 in the horizontal direction and the plurality of data lines D1, D2 and D3 in the vertical direction are arranged, and the gate lines G1 and G2 and the data lines D1, D2 and D3 are arranged. The storage electrode wirings COM1 and COM2 are arranged so as to cross each other to form a pixel region and to cross the pixel region. A thin film transistor TFT is formed in the pixel region, and the gate terminal g of the thin film transistor TFT is connected to the gate lines G1 and G2, and the source and drain terminals s and d are respectively provided with data. It is connected to the lines D1, D2, and D3 and the liquid crystal capacitor LC. The storage capacitor STG is connected between the drain terminal d and the storage electrode wirings COM1 and COM2, and a common voltage V _com is applied to the other terminal of the liquid crystal capacitor LC.

When the open voltage is applied to the gate terminal g of the thin film transistor TFT through the gate line G1, the image signals of the data lines D1, D2, and D3 are transferred to the liquid crystal capacitor LC and the thin film transistor TFT. The liquid crystal capacitor LC and the storage capacitor STG are charged into the storage capacitor STG, and the charged charge is maintained until the gate opening voltage is applied to the thin film transistor TFT again in the next cycle. In general, when the gate voltage changes from the open state to the closed state, the pixel voltage falls slightly, and the sustain capacitor STG serves to reduce this variation.

In general, a thin film transistor of a liquid crystal display device has an amorphous silicon layer or a polycrystalline silicon layer as an active layer, and may be divided into a top gate method and a bottom gate method according to relative positions of the gate electrode and the active layer. In the case of a polysilicon thin film transistor, a top gate method in which a gate electrode is located above the semiconductor layer is mainly used.

However, the storage capacitor of the top gate type polysilicon thin film transistor liquid crystal display device according to the related art is composed of a doped storage region of the silicon layer, a storage electrode thereon, and a gate insulating film interposed therebetween. Further, another storage capacitor is formed by an insulating layer composed of the storage electrode, the pixel electrode placed thereon, and the interlayer insulating film and the protective film therebetween. At this time, since the thickness of the interlayer insulating film and the protective insulating film is about 5,000 각각 and much thicker than that of the gate insulating film having a thickness of 500 to 3,000 상대적, a relatively small value of the holding capacitor is formed between the pixel electrode and the sustain electrode, thereby serving as a storage capacitor. can not do.

In this structure, in order to form the storage capacitor by the storage region of the storage electrode and the silicon layer, an ion doping process is required to cause the storage region to serve as an electrode. That is, a process of forming a photoresist film, patterning it using a mask, and then implanting and diffusing ions into the silicon layer through the portion where the photoresist film is removed is necessary.

An object of the present invention is to simplify the manufacturing process by eliminating the photolithography process and the ion doping process for the storage capacitor when forming the thin film transistor and the storage capacitor.

Another object of the present invention is to secure a sufficient storage capacity.

Further, another object of the present invention is to lower the effective resistance of the silicon region serving as one electrode of the storage capacitor.

1 is a circuit diagram of a conventional independent wiring type liquid crystal display device,

2 is a layout view of a liquid crystal display according to a first exemplary embodiment of the present invention;

3 is a cross-sectional view taken along line III-III ′ of FIG. 2,

4 is a layout view illustrating only a silicon layer, a storage line, and a gate electrode in FIG. 2;

5 is a layout view of a liquid crystal display according to a second exemplary embodiment of the present invention.

6 is a cross-sectional view taken along line VI-VI 'of FIG. 5,

7 is a view for explaining the principle that the holding capacitor is formed when the voltage is applied,

8 and 9 are waveform diagrams of signal voltages of the liquid crystal display according to the exemplary embodiment of the present invention.

10 is a graph showing the change of the holding capacitance according to the magnitude of the holding voltage;

11 is a graph showing charging characteristics of a voltage applied to a pixel electrode;

12A to 12J are cross-sectional views illustrating a method of manufacturing a liquid crystal display according to an exemplary embodiment of the present invention according to a process sequence.

13 is an equivalent circuit diagram of a liquid crystal display device according to a first and second embodiment of the present invention.

14 is a layout view of a liquid crystal display according to a third exemplary embodiment of the present invention.

15 is a graph illustrating charging characteristics of voltages applied to pixel electrodes of the liquid crystal display according to the second and third embodiments;

16 is an equivalent circuit diagram of a liquid crystal display according to a third exemplary embodiment of the present invention.

17 is a layout view of a liquid crystal display according to a fourth exemplary embodiment of the present invention.

FIG. 18 is a cross-sectional view taken along line XVIII-XVIII ′ of FIG. 17;

19 is a layout view of a liquid crystal display according to a fifth exemplary embodiment of the present invention.

20 is a cross-sectional view taken along line XX-XX 'of FIG. 19,

21 is an equivalent circuit diagram of a liquid crystal display according to a fifth exemplary embodiment of the present invention.

22 and 23 are layout views of the liquid crystal display according to the sixth and seventh embodiments of the present invention.

24 is a layout view of a liquid crystal display according to an eighth exemplary embodiment of the present invention.

25 is a cross-sectional view taken along line XXV-XXV 'of FIG. 24,

26 is a layout view of a liquid crystal display according to a ninth embodiment of the present invention;

FIG. 27 is a cross sectional view taken along line XXVII-XXVII ′ of FIG. 26;

28 is a layout view of a liquid crystal display according to a tenth exemplary embodiment of the present invention.

FIG. 29 is a cross-sectional view taken along line XXIX-XXIX 'of FIG. 28.

The silicon layer of the liquid crystal display according to the present invention for solving this problem includes a doped source and drain region, an undoped channel region, a holding region for the doped storage capacitor and a border region. Here, the channel region is located between the source and drain regions, and the storage region is adjacent to the drain region and separated from the channel region, and the edge region is adjacent to the edge of the storage region and connected to the drain region. A gate insulating film is formed on the silicon layer, and a gate electrode is formed at a position corresponding to the channel region and a storage electrode is formed at a position corresponding to the storage region on the gate insulating film. Here, the storage region, the storage electrode, and the gate insulating film disposed therebetween form a storage capacitor. The storage region is not doped and thus cannot function as a storage capacitor, but is thin film transistors compared to the maximum value of the image voltage. Applying more than a threshold voltage to the sustain electrode to the sustain electrode to form a charge accumulation layer on the surface of the sustain region can be used as a sustain capacitor. At this time, the edge region becomes part of the charge transfer path, thereby reducing the resistance of the charge storage layer.

Such a liquid crystal display device can be manufactured by forming a silicon layer and a gate insulating film, forming a gate electrode and a sustain electrode thereon, and ion-dope the silicon layer using the gate electrode and the sustain electrode as a mask.

Next, a liquid crystal display according to an exemplary embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

The liquid crystal display according to the exemplary embodiment of the present invention has a structure in which two electrodes of the liquid crystal capacitor, that is, the pixel electrode and the common electrode, are formed on different substrates. Explain.

First, a structure and a driving method of a liquid crystal display device to serve as a storage capacitor without doping a silicon layer under the storage capacitor electrode through the first embodiment will be described.

FIG. 2 is a layout view of a liquid crystal display according to a first exemplary embodiment of the present invention, FIG. 3 is a cross-sectional view taken along line III-III ′ of FIG. 2, and FIG. 4 is an enlarged view of a holding line, a silicon layer, and a gate electrode. It is a layout view.

2 to 3, the polysilicon layer 200 is elongated in the horizontal direction on the transparent insulating substrate 100, and the silicon dioxide is formed on the substrate 100 on which the polycrystalline silicon layer 200 is formed. A gate insulating film 300 made of (SiO ₂ ) or silicon nitride (SiNx) is formed over the entire surface with a thickness of 500 to 3,000 Å.

The gate line 400 is formed in the horizontal direction on the gate insulating layer 300, and a part of the gate line 400 extends in the vertical direction to form the gate electrode 410, and the gate electrode 410 is formed with a portion of the silicon layer 200. Overlaps. In addition, the holding line 430 is formed to be formed in the same layer in the same layer and extends in the horizontal direction in parallel with the gate line 400 and partially overlaps the silicon layer 200, and the holding line 430 of the portion overlapping with the silicon layer 200 is provided. ) Becomes the sustain electrode 420.

In this case, as shown in FIG. 4, the silicon layer 200 is divided into a narrow portion and a large portion, and the gate electrode 410 overlaps the narrow portion and is formed around the gate electrode 410. The left side is narrower and the right side is wider. The holding line 430 overlaps with the large portion of the silicon layer 200, and the width of the holding line 430 extends up and down in the portion of the overlapped portion by the length of L to increase the overlap area. In the present embodiment, the width W ₁ of the holding line 430 in the extension part is larger than the width W ₀ of the silicon layer 200, and the edge thereof is positioned outside the silicon layer 200. The length L of the extension is longer than the width W ₁ .

Meanwhile, a portion of the silicon layer 200 disposed under the gate electrode 410 and the storage electrode 420 is not doped but the remaining portion is doped with n-type impurities, and the doped portion is the gate electrode 410. And the sustain electrode 420 into a plurality of regions. The undoped region under the gate electrode 410 is a channel region 220 in which a channel of the thin film transistor is formed, and the undoped region under the storage electrode 420 serves as an electrode of the storage capacitor together with the storage electrode 420. The doped regions on both sides of the channel region 220 become the source region 210 and the drain region 230, respectively, and the drain region 230 is adjacent to the sustain region 240. In addition to these regions, silicon layer regions 250 and 260 exposed to the outside of the holding line 430 may be formed due to the difference in length and width of the silicon layer 200 and the holding line 430. Adjacent to and separated from the drain region 230.

An interlayer insulating layer 500 is formed on the gate lines such as the gate line 400, the gate electrode 410, and the storage line 430, and the source and drain regions 210, It has contact holes C1 and C2 exposing 230.

The data line 600 is vertically formed on the interlayer insulating layer 500 to intersect the gate line 400 and the storage line 430, and a part of the data line 600 is formed through the contact hole C1. 210). On the opposite side of the data line 600 around the gate electrode 410, a drain electrode 620 formed of a metal pattern for data wiring is connected to the drain region 240 through the contact hole C2.

The interlayer insulating film 500 on which the data line 600 is formed is covered with the protective insulating film 700, and the passivation port C3 exposing the drain electrode 620 is formed in the protective insulating film 700. An indium-tin-oxide (ITO) transparent pixel electrode 800 is formed on the passivation insulating layer 700 inside the pixel region PX defined by the intersection of the data line 600 and the gate line 400 to pass through the opening C3. Is connected to the drain electrode 620 and overlaps the storage electrode 420.

Meanwhile, unlike the present exemplary embodiment, the drain region 230 may be directly connected to the pixel electrode 800. This will be described with reference to FIGS. 5 and 6.

FIG. 5 is a layout view of a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along line VI-VI ′ of FIG. 5, and has no structure for the drain electrode 620. .

5 and 6, a contact hole C4 exposing the drain region 230 is formed in the protective insulating film 700, the interlayer insulating film 500, and the gate insulating film 300, and the contact hole C4 is formed. The pixel electrode 800 is directly connected to the drain region 230 through. Except for this point, it has the same structure as in the first embodiment.

As described above, the storage region 240, the storage electrode 420, and the gate insulating film 300 interposed therebetween form a storage accumulator, where the storage region 240 is not doped and thus, as a conductor itself. Since it cannot play a role, a voltage is applied as follows in order to fully function as an electrode of the holding capacitor.

FIG. 7 is a view for explaining the principle of the formation of the storage capacitor when voltage is applied, and shows a state when the voltage V applied to the storage electrode is applied above the threshold voltage Vth of the thin film transistor compared to the image signal voltage. It is sectional drawing shown typically.

When the open voltage is applied to the gate electrode 410, a channel through which electrons can move is formed in the channel region 220 positioned between the source region 210 and the drain region 230, and through this channel, a source region is provided. The image signal voltage from 210 is applied to the pixel electrode 800 via the data line 600 and the drain region 230.

At this time, when the voltage V _st having a value equal to or higher than the threshold voltage V _th of the thin film transistor relative to the maximum value of the image signal voltage is applied to the sustain electrode 420, the sustain electrode 420 is gated in the conventional field effect transistor. The charge accumulation layer 241 is formed on the upper layer of the undoped storage region 240 adjacent to the drain region 230 and serving as an electrode. The charge accumulation layer 241 formed as described above is a conductive layer and thus may serve as a sustain electrode.

Examples of voltage waveforms applied to sustain electrode 420 are shown in FIGS. 8 and 9. 8 and 9 are waveform diagrams of a common voltage, a gate voltage, an image voltage, and a sustain voltage, wherein the gate voltage V _g and the image voltage V _video are signal voltages applied to one gate line and one data line, respectively. , The common voltage V _com is a signal voltage applied to the common electrode, and the sustain voltage V _st is a voltage applied to the sustain line or the sustain electrode.

The gate open signal is applied to each gate line in turn, and when an open signal is applied to a gate line, an image signal of a pixel connected to the gate line is applied through each data line. This image signal is applied to the liquid crystal capacitor of the pixel through the opened thin film transistor. When the image signals are applied to all the pixels in this way, the gate open signal is applied to each gate line in turn, and the above-described operation is repeated. However, at this time, the image signal has a polarity opposite to that of the previous image signal with respect to the common voltage, that is, an inverted value.

Therefore, in FIGS. 8 and 9, the gate voltage V _g applied to one gate line represents a waveform in which an opening voltage in the form of a pulse is applied at a constant cycle, and the image voltage V _video is a common voltage at a constant cycle. The waveform of the form inverted with respect to (V _com ) is shown.

On the other hand, the common voltage (V _com ) may be a direct current that maintains a constant magnitude as shown in FIG. 8, or may have the form of alternating current repeating low and high values at the same period as the period of the gate voltage (V _g ) as shown in FIG. 9. In addition, the waveform of the sustain voltage V _st may be changed according to the shape of the common voltage V _com . That is, as shown in FIG. 8, when the common voltage V _com is a direct current, the sustain voltage V _st is also a direct current. As shown in FIG. 9, when the common voltage V _com is an alternating current, the sustain voltage V _st is also an alternating current. can do. In the latter case, if the common voltage (V _com ) has a high value, the holding voltage (V _st ) has a high value. On the contrary, if the common voltage (V _com ) has a low value, the holding voltage (V _st ) has a low value. It is desirable to.

In both cases shown in FIGS. 8 and 9, the minimum value of the sustain voltage V _st applied to the sustain electrode 420 should be greater than or equal to the threshold voltage V _th than the maximum value of the image voltage V _ds .

FIG. 10 is a graph showing the change of the holding capacitor C _st according to the size of the holding voltage V _st . When the image voltage V _video is 0 V and the holding voltage V _st is changed, C _st ) shows the change in value.

When the image voltage (V _video ) is 0V, when the value of the holding voltage (V _st ) is about 3.5 V or more, which is the threshold voltage (V _th ) of the thin film transistor, a holding capacity of about 575 Farad is generated. It is the same value as the retention capacity. In addition, when the image voltage V _video is changed to 5V and 10V, respectively, 575F can be obtained by applying "image voltage + V _th " as the sustain voltage V _st .

FIG. 11 is a graph illustrating charging characteristics of a pixel when the sustain voltage V _st is 10 V and 14 V, respectively, when the maximum value of the image voltage V _pixel is 10 V and the threshold voltage of the thin film transistor is 3.5 V. FIG. When the gate open voltage is applied (T ₁ ), it starts to charge and reaches its maximum value, and when the gate close voltage is applied (T ₂ ), the charging voltage is momentarily decreased slightly. This is called the feed through voltage.

When the sustain voltage V _st applied to the sustain electrode 420 is 10V, the maximum voltage 10V is charged to the pixel faster than the case of 14V, but when the gate voltage V _g is turned off, the voltage is 14V. The voltage drop width ΔV2 is greater than the voltage drop width ΔV1 going down to.

This result shows that when the sustain voltage is 14 V, that is, when a sustain voltage greater than or equal to the maximum value of the image voltage is applied, a sustain capacity is generated, the charging time is delayed, and the kickback voltage is reduced. .

As such, since the undoped holding region 240 can be used as one electrode of the storage capacitor by applying an appropriate voltage to the storage electrode 420, a process for doping the storage region 240 is not necessary.

Next, a method of manufacturing the liquid crystal display device according to the first and second embodiments will be described with reference to FIGS. 2 to 6 and 12A to 12J.

The polysilicon layer 200 is formed on the transparent insulating substrate 100. At this time, heat treatment or laser annealing may be performed to increase the crystallinity of the silicon layer 200 (see FIG. 12A).

Silicon dioxide (SiN ₂ ) or silicon nitride is deposited to a thickness of 500 to 3,000 Å to form a gate insulating film 300 (see FIG. 12B).

After the conductive material for the gate wiring is deposited, patterning is performed to form gate wiring such as the gate lines 400 and 410 and the storage electrode lines 420 and 430. As described above, the gate electrode 410, which is a branch of the gate line 400, and the storage electrode 420, which is part of the storage electrode line 430, are positioned on the silicon layer 200 (see FIG. 12C).

Source and drain regions 210 and 230 are formed by implanting and diffusing ions into the silicon layer 20 using the gate wirings 400, 410, 420, and 430 as masks. In this case, the lower portions of the gate electrode 410 and the storage electrode 420 are not doped to form the channel region 220 and the storage region 240, respectively, and the storage region 240 is adjacent to the drain region 230. In addition, as described above, doped regions 250 and 260 adjacent to the storage region 240 and isolated from the drain region 230 are also formed (see FIG. 12D).

The interlayer insulating film 500 is formed thereon to insulate the gate line 400, the gate electrode 410 and the sustain line 430 from the data line and drain electrode to be formed later (see FIG. 12E).

Thereafter, the contact holes C1 and C2 are formed by removing the gate insulating film 300 and the interlayer insulating film 500 on the source and drain regions 210 and 230 of the silicon layer 200. However, in the structure of the second embodiment, it is not necessary to form the contact hole C2 at this stage (see Fig. 12F).

A data line metal such as chromium (Cr) or molybdenum (Mo) is deposited and patterned to form a data line 600 and a drain electrode 620. In this case, a part of the data line 600 and the drain electrode 620 are connected to the source and drain regions 210 and 230 through the contact holes C1 and C2, respectively. However, in the structure of the second embodiment, it is not necessary to form the drain electrode 620 (see Fig. 12G).

After the protective insulating film 700 is applied (see FIG. 12H) on the upper portion, the gas passage C3 is formed by etching the upper portion of the drain electrode 620. However, in the structure of the second embodiment, the contact hole C4 is formed by removing the gate insulating film 300, the interlayer insulating film 500, and the protective insulating film 700 over the drain region 230 (see FIG. 12I).

Finally, a transparent conductive material such as ITO is deposited and patterned to form the pixel electrode 800 on the sustain electrode 420. In this step, the pixel electrode 800 is connected to the drain electrode 620 through the via hole C3. However, in the structure of the second embodiment, the pixel electrode 800 is directly connected to the drain region 230 through the contact hole C4 (see FIG. 12J).

As described above, since the storage region 240 can be used as one electrode of the storage capacitor by adjusting the voltage applied to the storage electrode 420, the number of masks is reduced because there is no need to ion-dope the storage region 240.

However, in FIG. 11, even when the gate opening voltage is applied to the thin film transistor, it is understood that the voltage of the pixel does not suddenly reach the image voltage, but gradually reaches the image voltage value over time, which is a resistance of the wiring and the capacitor. And a phenomenon occurring due to capacitance. Therefore, the equivalent circuit diagram is shown in FIG. 13. In FIG. 13, only the storage capacitor is considered, and the resistance of the storage region 240 is represented by R _st1 , which may be viewed as being connected in series with the storage capacitor STG. The liquid crystal capacitor LC and the liquid crystal capacitor LC are connected to the drain d of the thin film transistor TFT in which the gate g and the source s are connected to the gate line G and the data line D, which are insulated from each other and cross each other. The storage capacitor STG is connected in parallel, and the resistor R _st1 is connected between the drain d and the storage capacitor STG.

At this time, the resistance value of the holding region 240 is determined by the following factors.

When voltage is applied to the drain region 230 and the storage electrode 420, charges in the drain region 230 move to the storage region 240 to accumulate charge. At this time, the length of the path through which charges in the drain region 230 move to the right end of the storage region 240 becomes L, and the resistance R _st1 is proportional to this length. However, since the charge time of the capacitor is proportional to the resistance, it is desirable to reduce the movement distance of the charge.

Thus, an embodiment for reducing the resistance of the holding region 240 by shortening the path through which charge travels is presented.

FIG. 14 is a layout view of a liquid crystal display according to a third exemplary embodiment, showing only a silicon layer, a storage electrode line, and a gate electrode, and may be applied to the structure of FIG. 2 or 5.

As shown in FIG. 13, in the third embodiment, the width W _{3 of the} storage electrode line 430 is smaller than the width W ₂ of the silicon layer 200, and the edge of the storage electrode line 430 is formed of the silicon pattern 200. It is designed to enter inside. In order to make the structure and the storage capacity shown in FIG. 4 the same, the length of the expanded portion is equal to L, and the width W ₃ of the expanded portion is the width of the expanded portion of the silicon layer 200 in FIG. 4. It may be the same as (W ₀ ).

In such a structure, a doped edge region 250 connected to the drain region 230 is formed in the entire upper portion of the upper edge of the holding region 240, and a doped edge region is isolated from the drain region 230 in the entire lower portion of the lower edge. 260).

When the sustain voltage V _st is applied to the sustain electrode 420 of the liquid crystal display, the charge accumulation layer 241 is formed on the sustain region 240. At this time, since the resistance of the doped edge region 250 is smaller than the resistance of the charge accumulation layer 241, the charges of the drain region 230 first move to the edge region 250, and then the holding region 240 is vertically moved. Move W ₃ distance across. However, since the width W ₃ of the extension portion of the holding line 430 is shorter than the length L, the movement distance of the charge is shorter than that of the structure of FIG. 4, and thus the resistance of the holding region 240 is also reduced.

FIG. 15 is a graph illustrating charging characteristics of the pixel voltage V _pixel of the liquid crystal display having the structure of FIG. 4 and the structure of FIG. 13.

In FIG. 15, a charging characteristic curve of the liquid crystal display having the structure of FIG. 4 is indicated by a dotted line, and a charging characteristic curve of the liquid crystal display having the structure of FIG. 14 is b. In both cases, there is no difference in kickback voltage ΔV since there is no difference in holding capacity, but in case of b, the charging time is shorter than a.

In the liquid crystal display according to the third exemplary embodiment, the resistance of the storage area 240 decreases, but the charge is added to the resistance of the storage area 240 by the resistance of the edge area 250. This is shown in FIG. 16 through an equivalent circuit diagram. That is, as shown in FIG. 16, the resistor R ₁ of the edge region 250 is connected between the resistor R _st2 of the sustain region 240 and the drain d.

As can be seen in FIG. 15, the value of the resistance R ₁ of the edge region 250 is smaller than the decrease of the resistance of the holding region 240, but reducing the resistance R ₁ may result in a faster charging time. . Thus, an embodiment in which the resistance of the edge region 250 is reduced is presented.

17 and 17 are cross-sectional views taken along line XVIII-XVIII 'of the layout, and the structure according to the fourth embodiment of the present invention is a liquid crystal display device according to a fourth embodiment of the present invention. Is the same. However, the doped upper edge region 250 of the silicon layer 200 is formed through the gate insulating film 300, the interlayer insulating film 500, and the protective insulating film 700, and contacts the plurality of contact holes C5 arranged in the horizontal direction. It is connected to the ITO pixel electrode 800 therethrough.

In this structure, since the resistance of the pixel electrode 800 is smaller than the resistance of the doped edge region 250, the charges are spread over the entire edge region 250 using the pixel electrode 800 as a path and then back to the holding region 240. As a result, the resistance of the edge region 250 is also relatively small, thereby reducing the charging time.

An example in which this resistance component can be further reduced is provided.

In the fifth embodiment illustrated in FIG. 20, which is a cross-sectional view of the wiring diagram of FIG. 19 and FIG. 19, the XX-XX ′ line, the doped edge region 260 and the pixel electrode 800 positioned below the holding region 240 are formed. The gate insulating layer 300, the interlayer insulating layer 500, and the passivation layer 700 are connected through the contact hole C6. The other structure is similar to that of the third embodiment.

In such a structure, charges from the drain region 230 move not only to the upper edge region 250 but also to the lower edge region 260 through the pixel electrode 800 having a low resistance. Thus, since charges from the upper and lower edge regions 250 and 260 simultaneously move to the holding region 240, the distance at which charges starting from the two regions 250 and 260 actually travel is half the width of the holding region 240. It becomes a distance. The resistance is thus reduced and the charging time is also shortened.

This structure is shown in an equivalent circuit diagram as shown in FIG. 21, and shows only a storage capacitor (STG) and a resistance component for convenience.

In FIG. 21, R ₂ and R ₃ are resistances of the upper edge region 250 and the lower edge region 260, respectively, and R _st3 and R _st4 are the resistances of the upper and lower half regions of the holding region 240, respectively. If the structure of FIG. 19 is the same as that of FIG. 14, R _st3 ≒ R _st4 ≒ ½ R _st2 and R ₂ ≒ R ₁ . If the resistance of the lower edge region 260 is similar to the resistance of the upper edge region 250, since R ₃ ≒ R ₂ ≒ R ₁ , the total resistance becomes ½R ₁ + ¼R _st2 , which is higher than that of the structure of FIG. 14. It can be seen that this is significantly reduced.

In addition to the structure of FIG. 19, the sixth and seventh embodiments of the structure which can further reduce the resistance of the edge regions 250 and 260 will be described.

22 and 23, the doped lower edge region 260 and the ITO pixel electrode 800 may be formed on the gate insulating film 300, the interlayer insulating film 500, and the protective insulating film 700. The ITO pixel electrode 800 and the gate insulating film 300 and the interlayer insulating film 500 are connected to each other through the plurality of contact holes C7 that are bored and arranged in the horizontal direction, or the doped upper and lower edge regions 250 and 260. ) And a plurality of contact holes C5 and C7 drilled through the protective insulating layer 700, thereby lowering the resistance of the edge regions 250 and 260. This is because, as described above, the ITO pixel electrode 800 having a lower resistance than the edge regions 250 and 260 serves as a charge transfer path.

24 to 29 illustrate embodiments in which a metal pattern having a lower resistance than ITO is connected to the edge region instead of connecting the edge region and the ITO pixel electrode to induce a movement path of charge into the metal pattern.

FIG. 24 is a layout view of a liquid crystal display according to an eighth exemplary embodiment of the present invention, and FIG. 25 is a cross-sectional view taken along line XXV-XXV 'of FIG. 24, and the basic structure thereof is the same as those of the foregoing embodiments.

However, a metal pattern 630 is formed on the doped edge regions 250 and 260 and the interlayer insulating layer 500 on the storage electrode 420 to overlap the storage electrode 420, and the pixel electrode 800 is formed of metal. It does not overlap with the pattern 63. The metal pattern 630 contacts the doped upper and lower edge regions 250 and 260 through a plurality of contact holes C8 and C9 formed in the gate insulating layer 300 and the interlayer insulating layer 500.

This structure is basically similar to that of FIG. 23, but the resistance is further reduced because the small-resistance gold pattern 630 is used instead of the pixel electrode 800 having a large resistance.

In addition, since the storage electrode 420, the interlayer insulating film 500, and the metal pattern 630 form another storage capacitor, there is an effect of increasing the storage capacitance.

26 and 27 are a layout view and a cross-sectional view of the liquid crystal display according to the ninth embodiment of the present invention, and XXVII-XXVII ', and formed only on upper portions of the edge regions 250 and 260 doped with the metal patterns 640 and 650. These are connected via a plurality of contact holes C8 and C9 formed in the gate insulating film 300 and the interlayer insulating film 500.

As in the eighth embodiment, the resistance of the edge regions 250 and 260 can be lowered. However, in this case, since the storage electrode 420 and the metal patterns 640 and 650 do not overlap, the storage capacitor by the storage electrode 420 and the metal patterns 640 and 650 is not formed.

28 and 29 are layout views and cross-sectional views taken along line XXVI-XXVI 'of the liquid crystal display according to the tenth exemplary embodiment of the present invention.

The basic structure and effects are the same as those of the eighth embodiment, except that the ITO pixel electrode 800 is formed on the passivation layer 700 on the sustain electrode 240.

According to the method of manufacturing the liquid crystal display device according to the third to tenth embodiments of the present invention, forming the sustain electrode 420 inwardly from the silicon pattern 200 and the metal pattern 630 when forming the data line 600 are described. 640, 650) is the same as the manufacturing method according to the first and / or second embodiment except that it is made together.

As described above, the liquid crystal display and the manufacturing method thereof according to the present invention do not require an ion doping process for a storage capacitor, and can form a storage capacitor that can have a large storage capacitance value without any additional process. In addition, since the resistance of the charge storage layer can be reduced, there is an effect that the time taken to charge the image voltage is reduced.

Claims (17)

Transparent insulation substrate, A silicon layer formed on the substrate, A gate insulating film covering the silicon layer, A gate electrode formed on the gate insulating film, A sustain electrode for a storage capacitor formed on the gate insulating film, The silicon layer is doped with a source region and a drain region, an undoped channel region located between the source region and the drain region, an undoped sustain region adjacent to the drain region and separated from the channel region, and the And a doped first region adjacent to an edge of the storage area and connected to the drain area, wherein the storage electrode is positioned above the storage area. In claim 1, And a voltage greater than a threshold voltage greater than a maximum value of the voltage applied to the drain region. In claim 1, The holding region is formed to extend in a first direction, the drain region is located at one end of the first direction of the holding region, and the first region is formed along the edge of the holding region in the first direction. Device. In claim 3, And a doped second region positioned opposite to the first region with respect to the storage region and adjacent to the storage region and separated from the drain region and the first region. In claim 4, And a transparent pixel electrode electrically connected to the drain region. In claim 5, The pixel electrode is connected to the first region at a plurality of positions along the first direction. In claim 6, And an insulating layer covering the storage electrode, wherein the pixel electrode overlaps the storage electrode through the insulating layer. In claim 6, A plurality of contact holes are formed in the gate insulating layer to expose the first region, and the pixel electrode is connected to the first region through the contact holes. In claim 5, The pixel electrode is connected to the second region. In claim 9, The semiconductor device may further include an insulating layer formed between the sustain electrode and the pixel electrode, wherein the gate insulating layer may include a first contact hole that exposes the second region, and the pixel electrode may be formed through the first contact hole. A liquid crystal display device connected to the second region. In claim 10, In the gate insulating layer, a plurality of second contact holes exposing the first region are formed at a plurality of positions along the first direction, and the pixel electrode is connected to the first region through the second contact holes. Liquid crystal display. In claim 10, And a plurality of first contact holes are formed along the first direction. In claim 5, The pixel electrode is insulated from and overlapped with the sustain electrode. In claim 5, And an interlayer insulating layer covering the sustain electrode and first and second metal patterns formed on the interlayer insulating layer on the sustain electrode and connected to the first and second regions, respectively. The method of claim 14, The first and second metal patterns are connected to each other. The method of claim 14, A plurality of contact holes are formed in the gate insulating layer to expose the first region and the second region, and the first and second metal patterns are connected to the first and second regions through the contact holes. . The method of claim 16, A passivation layer is further formed on the metal pattern, and the pixel electrode is formed on the passivation layer so as to overlap the sustain electrode.