KR100577295B1 - Method for manufacturing of semiconductor device - Google Patents

Method for manufacturing of semiconductor device Download PDF

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KR100577295B1
KR100577295B1 KR1019990003435A KR19990003435A KR100577295B1 KR 100577295 B1 KR100577295 B1 KR 100577295B1 KR 1019990003435 A KR1019990003435 A KR 1019990003435A KR 19990003435 A KR19990003435 A KR 19990003435A KR 100577295 B1 KR100577295 B1 KR 100577295B1
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forming
layer
gate electrode
source
mask
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KR20000055026A (en
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양형모
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 콘택홀 형성시의 식각 공정에서 기판이 손실되는 것을 막아 콘택 저항의 증가를 막을 수 있도록한 반도체 소자의 제조 방법에 관한 것으로, 반도체 기판상에 게이트 전극을 형성하는 공정과,상기 패터닝된 게이트 전극을 마스크로 저농도의 불순물 이온을 주입하여 저농도 불순물 영역을 형성하는 공정과,상기 게이트 전극을 포함하는 전면에 측벽 형성용 물질층을 형성하고 에치백하여 게이트 전극의 측면에 게이트 측벽을 형성하는 공정과,전면에 버퍼 산화막을 형성하고 소오스/드레인 콘택 마스크를 이용하여 선택적으로 제거하는 공정과,선택적으로 패터닝된 버퍼 산화막을 마스크로하여 고농도의 불순물 이온을 주입하여 이온 주입 Rp가 차이나는 고농도 불순물 영역을 형성하는 공정과,전면에 ILD층을 형성하고 소오스/드레인 콘택 영역의 ILD층을 선택적으로 제거하여 소오스/드레인 콘택홀을 형성하는 공정과,상기 콘택홀을 매립하는 베리어 메탈층,금속 전극층을 형성하는 공정을 포함하여 이루어진다.The present invention relates to a method of manufacturing a semiconductor device that prevents an increase in contact resistance by preventing a substrate from being lost in an etching process when forming a contact hole, and further comprising: forming a gate electrode on the semiconductor substrate; Forming a low concentration impurity region by implanting a low concentration of impurity ions using a gate electrode as a mask, and forming a sidewall forming material layer on the entire surface including the gate electrode and etching back to form a gate sidewall at a side of the gate electrode A process of forming a buffer oxide film on the front surface and selectively removing the buffer oxide film using a source / drain contact mask, and a highly concentrated impurity in which a high concentration of impurity ions are implanted using a selectively patterned buffer oxide film as a mask. Forming an area, forming an ILD layer on the front surface, and forming a source / drain contact For the selective removal of the ILD layer it comprises a step of forming a barrier metal layer, a metal electrode layer embedded in the step of the contact holes to form the source / drain contact holes.

콘택저항Contact resistance

Description

반도체 소자의 제조 방법{Method for manufacturing of semiconductor device} Method for manufacturing a semiconductor device

도 1a와 도 1b는 종래 기술의 반도체 소자의 제조 공정 단면도1A and 1B are cross-sectional views of a manufacturing process of a semiconductor device of the prior art.

도 2a내지 도 2d는 본 발명에 따른 반도체 소자의 제조 공정 단면도2A to 2D are cross-sectional views of a manufacturing process of a semiconductor device according to the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

21. 반도체 기판 22. 저농도 불순물 영역21. Semiconductor substrate 22. Low concentration impurity region

23. 고농도 불순물 영역 24. 게이트 전극23. High concentration impurity region 24. Gate electrode

25. 게이트 캡층 26. 게이트 측벽25. Gate Cap Layer 26. Gate Sidewalls

27. 버퍼 산화막 28. 포토레지스트층27. Buffer Oxide 28. Photoresist Layer

29. ILD층 30. 베리어 메탈층29. ILD layer 30. Barrier metal layer

31. 금속 전극층31. Metal electrode layer

본 발명은 반도체 소자에 관한 것으로, 특히 콘택홀 형성시의 식각 공정에서 기판이 손실되는 것을 막아 콘택 저항의 증가를 막을 수 있도록한 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device in which a substrate is prevented from being lost in an etching process during contact hole formation, thereby preventing an increase in contact resistance.

이하, 첨부된 도면을 참고하여 종래 기술의 반도체 소자의 제조 공정에 관하여 설명하면 다음과 같다.Hereinafter, a manufacturing process of a semiconductor device of the prior art will be described with reference to the accompanying drawings.

도 1a와 도 1b는 종래 기술의 반도체 소자의 제조 공정 단면도이다.1A and 1B are cross-sectional views of a manufacturing process of a semiconductor device of the prior art.

종래 기술의 반도체 소자 제조 공정은 먼저, 반도체 기판(1)상에 게이트 산화막(5a),게이트 형성용 물질층,캡 형성용 물질층을 차례로 형성한다.In the semiconductor device manufacturing process of the prior art, first, a gate oxide film 5a, a gate forming material layer, and a cap forming material layer are sequentially formed on the semiconductor substrate 1.

그리고 상기 적층 형성된 캡 형성용 물질층,게이트 형성용 물질층을 선택적으로 식각하여 게이트 전극(5b), 게이트 캡층(5c)을 형성한다.The gate layer 5b and the gate cap layer 5c may be formed by selectively etching the stacked cap forming material layer and the gate forming material layer.

이어, 상기 패터닝된 게이트 전극(5b)을 마스크로 저농도의 불순물 이온을 주입하여 LDD 영역(2)을 형성한다.Subsequently, a low concentration of impurity ions are implanted using the patterned gate electrode 5b as a mask to form the LDD region 2.

그리고 상기 패터닝된 게이트 전극(5b), 게이트 캡층(5c)을 포함하는 전면에 측벽 형성용 물질층을 형성하고 에치백하여 게이트 전극(5b),게이트 캡층(5c)의 측면에 게이트 측벽(4)을 형성한다.A sidewall forming material layer is formed on the entire surface including the patterned gate electrode 5b and the gate cap layer 5c and etched back to form a gate sidewall 4 at the side of the gate electrode 5b and the gate cap layer 5c. To form.

이어, 상기 게이트 측벽(4)을 포함하는 게이트 전극(5b)을 마스크로하여 고농도의 불순물을 주입하여 소오스/드레인 영역(3)을 형성한다.Subsequently, a high concentration of impurities are implanted using the gate electrode 5b including the gate sidewall 4 as a mask to form a source / drain region 3.

그리고 도 1b에서와 같이, 전면에 ILD(InterLayer Dielectric)층(6)을 형성하고 소오스/드레인 영역상의 일부를 제거하여 콘택홀을 형성한다.As shown in FIG. 1B, an ILD layer 6 is formed on the entire surface and a portion of the source / drain region is removed to form a contact hole.

이어, 상기 콘택홀에 의해 노출된 반도체 기판(1)의 표면 및 콘택홀의 표면에 베리어 금속층(7)을 형성하고 콘택홀을 완전 매립하는 금속 전극층(8)을 형성한다.Subsequently, a barrier metal layer 7 is formed on the surface of the semiconductor substrate 1 exposed by the contact hole and the surface of the contact hole, and a metal electrode layer 8 completely filling the contact hole is formed.

이와 같은 종래 기술의 반도체 소자의 제조 공정은 채널 길이가 스케일 다운 되면서 필연적으로 나타나게 되는 쇼트 채널 효과를 억제하기 위한 여러가지 방법중의 하나로 소오스/드레인 이온 주입시의 에너지를 낮추어 진행하므로써 샐로우 접합(Shallow Junction)을 형성한다.Such a manufacturing process of the semiconductor device of the prior art is one of several methods for suppressing the short channel effect which is inevitably shown as the channel length is scaled down, and proceeds by lowering the energy during source / drain ion implantation. To form a junction.

샐로우 접합을 형성하게 되면 소자의 쇼트 채널 효과에 의한 소자의 신뢰성 저하는 어느 정도 개선되지만, 이후의 소오스/드레인 콘택을 형성하기 위한 건식 식각 공정시에 고농도로 도핑된 소오스/드레인 도팬트가 상당 부분 식각될 가능성이 크다.The formation of a shallow junction improves the reliability of the device due to the short channel effect of the device to some extent, but the heavily doped source / drain dopant is considerably large during the subsequent dry etching process to form the source / drain contact. It is likely to be partially etched.

이와 같은 종래 기술의 반도체 소자에 있어서는 다음과 같은 문제가 있다.Such a semiconductor device of the prior art has the following problems.

콘택 공정에서의 식각시에 고농도로 도핑된 소오스/드레인 영역의 손상으로 불순물 농도가 감소하게 되면, 콘택 저항이 증가하는 문제가 있다.When the impurity concentration decreases due to damage of the heavily doped source / drain regions during etching in the contact process, there is a problem in that the contact resistance increases.

콘택 저항의 증가는 소자 동작시에 전류를 감소시키는데, 특히 pMOS Tr.에서는 전류 감소에 의한 동작특성 저하 문제가 더 심각하다.Increasing contact resistance reduces current during device operation, especially in pMOS Tr.

동작 특성 저하에서 오믹 콘택의 특성을 잃어버리고 쇼트키 콘택(Shottky Contact)특성을 보이게 된다.In the deterioration of operating characteristics, the ohmic contact loses its characteristics and shows the Schottky Contact characteristic.

만약, 이러한 문제를 해결하기 위하여 콘택 형성시에 오버 에치 타임을 줄이게 되면 언더 에치 불량이 발생하게 된다.If the over-etch time is reduced during contact formation to solve this problem, under-etch defects may occur.

본 발명은 이와 같은 종래 기술의 반도체 소자의 제조 공정의 문제를 해결하기 위하여 안출한 것으로, 콘택홀 형성시의 식각 공정에서 기판이 손실되는 것을 막아 콘택 저항의 증가를 막을 수 있도록한 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve such a problem of the manufacturing process of the semiconductor device of the prior art, the manufacturing of a semiconductor device to prevent the increase of the contact resistance by preventing the loss of the substrate in the etching process at the time of forming the contact hole The purpose is to provide a method.

이와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 제조 방법은 반도체 기판상에 게이트 전극을 형성하는 공정과,상기 패터닝된 게이트 전극을 마스크로 저농도의 불순물 이온을 주입하여 저농도 불순물 영역을 형성하는 공정과,상기 게이트 전극을 포함하는 전면에 측벽 형성용 물질층을 형성하고 에치백하여 게이트 전극의 측면에 게이트 측벽을 형성하는 공정과,전면에 버퍼 산화막을 형성하고 소오스/드레인 콘택 마스크를 이용하여 선택적으로 제거하는 공정과,선택적으로 패터닝된 버퍼 산화막을 마스크로하여 고농도의 불순물 이온을 주입하여 이온 주입 Rp가 차이나는 고농도 불순물 영역을 형성하는 공정과,전면에 ILD층을 형성하고 소오스/드레인 콘택 영역의 ILD층을 선택적으로 제거하여 소오스/드레인 콘택홀을 형성하는 공정과,상기 콘택홀을 매립하는 베리어 메탈층,금속 전극층을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 한다.The semiconductor device manufacturing method of the present invention for achieving the above object is a step of forming a gate electrode on a semiconductor substrate, and a step of forming a low concentration impurity region by implanting a low concentration of impurity ions using the patterned gate electrode as a mask And forming a sidewall forming material layer on the front surface including the gate electrode and etching back to form a gate sidewall on the side of the gate electrode, and forming a buffer oxide layer on the front surface and selectively using a source / drain contact mask. A process of forming a high concentration impurity region having a different ion implantation Rp by implanting a high concentration of impurity ions using a selectively patterned buffer oxide film as a mask, and forming an ILD layer on the front surface and source / drain contact regions Selectively removing the ILD layer of the source to form a source / drain contact hole; Including a step of forming a barrier metal layer, a metal electrode layer embedded in the contact hole characterized in that formed.

이하, 첨부된 도면을 참고하여 본 발명에 따른 반도체 소자의 제조 공정에 관하여 상세히 설명하면 다음과 같다.Hereinafter, a manufacturing process of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a내지 도 2d는 본 발명에 따른 반도체 소자의 제조 공정 단면도이다.2A to 2D are cross-sectional views illustrating a process of manufacturing a semiconductor device according to the present invention.

본 발명에 따른 반도체 소자 제조 공정은 먼저, 도 2a에서와 같이, 반도체 기판(21)상에 게이트 산화막,게이트 형성용 물질층,캡 형성용 물질층을 차례로 형성한다.In the semiconductor device manufacturing process according to the present invention, first, as shown in FIG. 2A, a gate oxide film, a gate forming material layer, and a cap forming material layer are sequentially formed on the semiconductor substrate 21.

그리고 상기 적층 형성된 캡 형성용 물질층,게이트 형성용 물질층을 선택적 으로 식각하여 게이트 전극(24), 게이트 캡층(25)을 형성한다.The gate electrode 24 and the gate cap layer 25 may be formed by selectively etching the stacked cap forming material layer and the gate forming material layer.

이어, 상기 패터닝된 게이트 전극(24)을 마스크로 저농도의 불순물 이온을 주입하여 저농도 불순물 영역(22)을 형성한다.Subsequently, low concentration impurity ions are implanted using the patterned gate electrode 24 as a mask to form a low concentration impurity region 22.

그리고 상기 패터닝된 게이트 전극(24), 게이트 캡층(25)을 포함하는 전면에 측벽 형성용 물질층을 형성하고 에치백하여 게이트 전극(24),게이트 캡층(25)의 측면에 게이트 측벽(26)을 형성한다.The sidewall forming material layer is formed on the front surface including the patterned gate electrode 24 and the gate cap layer 25 and etched back to form gate sidewalls 26 on the side of the gate electrode 24 and the gate cap layer 25. To form.

이와 같이 게이트 측벽(26)의 형성 공정이 완료되면 전면에 버퍼 산화막(27)을 형성한다.As such, when the process of forming the gate sidewall 26 is completed, the buffer oxide layer 27 is formed on the entire surface.

이어, 도 2b에서와 같이, 상기 버퍼 산화막(27)상에 포토레지스트층(28)을 형성한다.Subsequently, as shown in FIG. 2B, a photoresist layer 28 is formed on the buffer oxide layer 27.

그리고 콘택 마스크를 이용하여 소오스/드레인 콘택 영역상의 포토레지스트층(28)이 선택적으로 제거되도록 패터닝하여 패터닝된 포토레지스트층(28)을 마스크로하여 노출된 버퍼 산화막(27)을 습식 또는 건식 식각 방식으로 선택적으로 제거한다.The photoresist layer 28 on the source / drain contact region is selectively removed using a contact mask to wet or dry etch the exposed buffer oxide layer 27 using the patterned photoresist layer 28 as a mask. To be removed.

그리고 도 2c에서와 같이, 상기 포토레지스트층(28)을 제거하고 선택적으로 패터닝된 버퍼 산화막(27)을 마스크로하여 고농도의 불순물 이온을 주입하여 고농도 불순물 영역(23)을 형성한다.As shown in FIG. 2C, the high concentration impurity region 23 is formed by removing the photoresist layer 28 and implanting a high concentration of impurity ions using the selectively patterned buffer oxide layer 27 as a mask.

이때, 버퍼 산화막(27)이 제거되지 않은 부분과 제거된 부분(콘택 형성 부위)간에는 이온 주입 Rp가 차이가 난다.At this time, the ion implantation Rp is different between the portion where the buffer oxide film 27 is not removed and the portion where the buffer oxide film 27 is removed (contact forming portion).

버퍼 산화막(27)이 제거된 부분의 Rp가 상대적으로 더 깊다.Rp of the portion where the buffer oxide film 27 is removed is relatively deeper.

그리고 도 2d에서와 같이, 전면에 ILD층(29)을 형성하고 소오스/드레인 콘택 영역(23)의 ILD층(29)을 선택적으로 제거하여 소오스/드레인 콘택홀을 형성한다.As shown in FIG. 2D, the ILD layer 29 is formed on the entire surface and the ILD layer 29 of the source / drain contact region 23 is selectively removed to form source / drain contact holes.

상기 콘택홀 바닥면 및 측면 그리고 콘택홀 에지부분의 ILD층(29)일부에 걸쳐서 베리어 메탈층(30),금속 전극층(31)을 형성한다.The barrier metal layer 30 and the metal electrode layer 31 are formed on the bottom and side surfaces of the contact hole and a part of the ILD layer 29 at the edge portion of the contact hole.

이와 같은 본 발명의 반도체 소자 제조 공정은 소오스/드레인 콘택 부분에 고농도 불순물 주입 깊이를 선택적으로 깊게하여 기판 손상에 따른 콘택 저항의 증가를 막는다.The semiconductor device fabrication process of the present invention selectively deepens the depth of implantation of high concentration impurities into the source / drain contact portions, thereby preventing an increase in contact resistance due to substrate damage.

이와 같은 본 발명에 따른 반도체 소자의 제조 공정은 다음과 같은 효과가 있다.Such a manufacturing process of a semiconductor device according to the present invention has the following effects.

버퍼 산화막의 두께를 조정할 경우 소오스/드레인 접합 깊이를 얕게 또는 깊게하는 것이 가능하여 공정의 용이성을 확보하는 효과가 있다.When the thickness of the buffer oxide film is adjusted, the source / drain junction depth can be made shallow or deep, thereby ensuring the ease of the process.

이는 소자의 특성 열화없이 콘택 저항을 개선할 수 있다는 것을 의미한다.This means that the contact resistance can be improved without deteriorating the characteristics of the device.

그리고 콘택 형성을 위한 식각 공정시에 오버에치를 충분히 할 수 있어 언더에치에 의한 콘택 오픈을 막는다.In addition, during the etching process for forming the contact, sufficient over-etching can be performed to prevent contact opening by under-etching.

Claims (3)

반도체 기판상에 게이트 전극을 형성하는 공정과,Forming a gate electrode on the semiconductor substrate, 상기 패터닝된 게이트 전극을 마스크로 저농도의 불순물 이온을 주입하여 저농도 불순물 영역을 형성하는 공정과,Implanting low concentration impurity ions using the patterned gate electrode as a mask to form a low concentration impurity region; 상기 게이트 전극을 포함하는 전면에 측벽 형성용 물질층을 형성하고 에치백하여 게이트 전극의 측면에 게이트 측벽을 형성하는 공정과,Forming a sidewall forming material layer on the entire surface including the gate electrode and etching back to form a gate sidewall on the side of the gate electrode; 전면에 버퍼 산화막을 형성하고 소오스/드레인 콘택 마스크를 이용하여 선택적으로 제거하는 공정과,Forming a buffer oxide film on the entire surface and selectively removing the same using a source / drain contact mask; 선택적으로 패터닝된 버퍼 산화막을 마스크로하여 고농도의 불순물 이온을 주입하여 이온 주입 Rp가 차이나는 고농도 불순물 영역을 형성하는 공정과,Implanting a high concentration of impurity ions using a selectively patterned buffer oxide film as a mask to form a high concentration impurity region having a different ion implantation Rp; 전면에 ILD층을 형성하고 소오스/드레인 콘택 영역의 ILD층을 선택적으로 제거하여 소오스/드레인 콘택홀을 형성하는 공정과,Forming an ILD layer on the entire surface and selectively removing the ILD layer of the source / drain contact region to form a source / drain contact hole; 상기 콘택홀을 매립하는 베리어 메탈층,금속 전극층을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 제조 방법.A method of manufacturing a semiconductor device comprising the step of forming a barrier metal layer filling the contact hole, a metal electrode layer. 제 1 항에 있어서, 고농도 불순물 영역을 형성하기 위한 이온 주입 공정을 버퍼 산화막이 제거된 부분의 Rp가 상대적으로 더 깊게 되도록 진행하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation process for forming a high concentration impurity region is performed so that the Rp of the portion where the buffer oxide film is removed is relatively deeper. 제 1 항에 있어서, 베리어 메탈층,금속 전극층을 콘택홀 바닥면 및 측면 그리고 콘택홀 에지부분의 ILD층일부에 걸쳐서 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1, wherein the barrier metal layer and the metal electrode layer are formed over the bottom and side surfaces of the contact hole and a part of the ILD layer at the edge portion of the contact hole.
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