KR100570612B1 - Driving apparatus and method of plasma display panel - Google Patents

Abstract

The present invention relates to a driving apparatus and a driving method of a plasma display panel.

In the present invention, the display pattern of the input image data is detected, and the power recovery operation is variably performed according to the detected display pattern to generate an address voltage having a variable pulse width corresponding to the display pattern. Accordingly, the address discharge efficiency can be increased. As a result, the display quality of the plasma display panel is improved.

PDP, address discharge, display pattern, power recovery

Description

Driving device of plasma display panel and driving method thereof {DRIVING APPARATUS AND METHOD OF PLASMA DISPLAY PANEL}

1 is a partial perspective view of an AC plasma display panel.

2 shows an electrode arrangement diagram of a plasma display panel.

3 is a schematic conceptual diagram of a plasma display device according to an exemplary embodiment of the present invention.

4 is a diagram illustrating an address driving circuit according to an exemplary embodiment of the present invention.

5 is a conceptual diagram of a dot on / off pattern.

6 is a conceptual diagram of a line on / off pattern.

7 is a conceptual diagram of a full white pattern.

8 is a flowchart illustrating a driving method according to an embodiment of the present invention.

9 is a driving timing diagram of the power recovery circuit of FIG. 4 according to the first pattern in an embodiment of the inventive concept.

FIG. 10 is a driving timing diagram of the power recovery circuit of FIG. 4 according to the second pattern in an embodiment of the inventive concept.

FIG. 11 is a driving timing diagram of the power recovery circuit of FIG. 4 according to a third pattern in an embodiment of the inventive concept.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel (PDP), and more particularly, to a driving apparatus and a driving method of a plasma display panel for performing a power recovery operation.

A plasma display panel is a flat display device that displays characters or images by using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. The plasma display panel is classified into a direct current type and an alternating current type according to a shape of a driving voltage waveform applied and a structure of a discharge cell.

In the DC plasma display panel, the electrode is exposed without the insulating discharge space, so that the current flows in the discharge space while the voltage is applied, and there is a disadvantage in that a resistance for limiting the current must be made. On the other hand, an AC plasma display panel has an advantage of having a longer lifetime than a DC type because the dielectric layer covers the electrode, thereby limiting the current by forming a natural capacitance component and protecting the electrode from the impact of ions during discharge.

1 is a partial perspective view of an AC plasma display panel.

As shown in FIG. 1, the scan electrode 4 and the sustain electrode 5 covered with the dielectric layer 2 and the protective film 3 are arranged in parallel on the glass substrate 1. On the glass substrate 6, a plurality of address electrodes 8 covered with the insulator layer 7 are provided. The partition 9 is formed on the insulator layer 7 between the address electrodes 8 in parallel with the address electrode 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both side surfaces of the partition wall 9. The glass substrates 1 and 2 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.

2 shows an electrode arrangement diagram of a plasma display panel.

As shown in FIG. 2, the electrodes of the plasma display panel have a matrix form of n × m. Specifically, the address electrodes A ₁ to A _m are arranged in the column direction and the scan electrodes (in the row direction). Y _{1 to} Y _n and sustain electrodes X _{1 to} X _n are arranged. The discharge cell 12 shown in FIG. 2 corresponds to the discharge cell 12 shown in FIG.

In general, the driving method of the AC plasma display panel includes a reset period, an addressing period, a sustain period, and an erase period.

The reset period is a period of initializing the state of each cell in order to perform an addressing operation smoothly on the cell, and the addressing period is obtained by addressing a cell (addressed cell) that is turned on to select a cell that is turned on and a cell that is not turned on. This is the period during which wall charges are accumulated. The sustain period is a period in which discharge for actually displaying an image is performed on the addressed cell by applying a sustain discharge voltage pulse, and the erase period is a period in which the wall discharge of the cell is reduced to end the sustain discharge.

At this time, since the discharge space between the scan electrode and the sustain electrode, the surface where the address electrode is formed, and the surface where the scan and sustain electrode are formed acts as a capacitive load (hereinafter referred to as a panel capacitor), capacitance exists in the panel. Therefore, in order to apply the waveform for addressing, reactive power is required in addition to the power for addressing. Therefore, the address driving circuit of the plasma display panel generally includes a power recovery circuit that recovers and reuses reactive power. As such a power recovery circuit, L.F. There is a circuit proposed by Weber (US Pat. Nos. 4,866,349 and 5,081,400).

In a conventional power recovery circuit, an address voltage for addressing is output in one scan line period. By the way, since the blanking of several hundred nsec normally occurs in an address voltage waveform, the pulse width of an address voltage becomes small. As a result, the address discharge period is shortened and discharge failure occurs, or the address discharge is unstable.

An object of the present invention is to improve address discharge efficiency when driving a plasma display panel.

In addition, the technical problem to be achieved by the present invention is to change the pulse width of the address voltage according to the power recovery operation according to the display pattern.

In order to solve this problem, a plasma panel driving apparatus according to an aspect of the present invention includes a display pattern detection unit for detecting a display pattern of input image data; A signal generator for varying and outputting an address driving control signal according to the display pattern; And an address driver configured to perform an electric power recovery operation according to the address driving control signal to generate an address voltage having a variable pulse width corresponding to the display pattern.

The address driver may include one or more power recovery circuits configured to generate an address voltage by performing a power recovery operation according to the address driving control signal; And a plurality of address selection circuits for selecting one of the address voltage and the first voltage and supplying the selected voltage to the plasma display panel.

In addition, the driving method of the plasma display panel according to another aspect of the present invention, a) detecting the display pattern of the input image data; b) variably performing a power recovery operation according to the display pattern to generate an address voltage having a variable pulse width corresponding to the display pattern; And c) selecting one of the address voltage and the first voltage and applying it to the plasma display panel.

In the driving apparatus and driving method of the plasma display panel of the present invention having the above characteristics, the power recovery operation is not performed when the display pattern of the image data is the first pattern. In this case, the address voltage may be a DC voltage, and the first pattern may be a full white pattern.

In addition, when the display pattern of the image data is a second pattern, the power recovery operation is performed at a first period according to an address driving control signal to generate a first address voltage, and the display pattern of the image data is a third pattern. In this case, the power recovery operation is performed in a second period longer than the first period according to the address driving control signal, thereby generating a second address voltage having a pulse width wider than the pulse width of the first address voltage. Here, the first period may be one scan line period, and the second period may be two scan line periods.

The second pattern may be a dot on / off pattern or a line on / off pattern, and the third pattern may be a monochrome pattern.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification. When a part is connected to another part, this includes not only a direct connection but also an indirect connection between other elements in between.

A plasma display device, a driving device of the plasma display panel, and a driving method according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

3 is a schematic conceptual diagram of a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 3, a plasma display device according to an exemplary embodiment of the present invention includes a plasma display panel 100, an address driver 200, a scan / hold driver 300, and a controller 400. In FIG. 3, the scan and sustain driver 300 is illustrated as one block. However, the scan and sustain driver 300 is generally formed separately from the scan driver and the sustain driver.

The plasma display panel 100 includes a plurality of column address electrode extending in a direction (A ₁ ~A _m), the plurality of scan electrodes extending yirumyeonseo in pairs in the row direction (Y ₁ ~Y _n) and a plurality of sustain electrodes ( X _{1 to} X _n ). The address driver 200 applies an address signal for selecting a discharge cell to be displayed to receive the address driving control signal from the controller 400 to the address electrodes (A ₁ ~A _m). The scan / hold driver 300 receives the sustain discharge control signal from the control fish 400 and alternately inputs a sustain discharge pulse to the scan electrodes Y _{1 to} Y _n and the sustain electrodes X _{1 to} X _n . Perform sustain discharge on the cell. The control unit 400 receives an image signal from the outside, generates an address driving control signal and a sustain discharge control signal, and applies them to the address driver 200 and the scan / sustain driver 300, respectively. In particular, according to an embodiment of the present invention, the control unit 400 generates a signal detecting unit 410 for detecting a display pattern based on the applied image signal and a signal for generating an address driving control signal and a sustain discharge control signal according to the detected display pattern. A portion 420 is included.

In general, a plasma display panel is driven by dividing one frame into a plurality of subfields, and a discharge cell to be discharged is selected among the plurality of discharge cells in an address period of each subfield. At this time, in order to select the discharge cells, in the address period, the selection voltage is sequentially applied to the scan electrodes, and the scan electrodes to which the selection voltage is not applied are biased with a positive voltage. The address (hereinafter, referred to as "address voltage") is applied to an address electrode passing through the discharge cell to be selected from among the plurality of discharge cells formed by the scan electrode to which the selection voltage is applied, and the address is not selected. A reference voltage is applied to the electrode. In general, the address voltage uses a positive voltage and the selection voltage uses a ground voltage or a negative voltage, so that discharge occurs at an address electrode to which the address voltage is applied and a scan electrode to which the selection voltage is applied, thereby selecting the corresponding discharge cell. And ground voltage is often used as a reference voltage.

Hereinafter, an address driving circuit included in the address driver 200 will be described with reference to FIG. 4, assuming that the selection voltage applied to the selected scan electrode and the reference voltage applied to the non-selected address electrode are ground voltages.

4 is a diagram illustrating an address driving circuit according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the address driving circuit according to an exemplary embodiment of the present invention includes a power recovery circuit 210 and a plurality of address selection circuits 220 _{1 to} 220 _m . The address selection circuits 220 _{1 to} 220 _{m are} connected to the plurality of address electrodes A _{1 to} A _m , respectively, and include two switching elements A _H and A _L , respectively. The switching elements A _H and A _L may be made of a field effect transistor having a body diode, or may be made of other switching elements having the same or similar function. The first terminal of the switching device (A _H) is connected between the power recovery circuit 210 and the address electrodes (A ₁ ~A _m), when the switching element (A _H) is turned on to be supplied from the power recovery circuit 210 The address voltage V _p is transmitted to the address electrodes A ₁ -A _m . The switching device (A _L) is an address electrode (A ₁ ~A _m) and is connected between the reference voltage (ground voltage), the switching device (A _L), the ground voltage is an address electrode (A ₁ ~A _m) when the turn-on Delivered.

In this way, the switching elements A _H and A _{L of the} address selection circuits 220 _{1 to} 220 _m respectively connected to the address electrodes A _{1 to} A _m are turned on or turned off by the control signal, thereby causing the address electrodes A ₁ to be turned off. The address voltage V _p or ground voltage is applied to ˜A _m ). That is, the switching element (A _H) during the address period is turned on and address voltage (V _a) is applied to the address electrode is a selection switching element (A _L) is turned on and the ground voltage applied to the address electrode is not a selection .

The power recovery circuit 210 includes switching elements A _a , A _r , A _f , A _g , an inductor L, a diode D ₁ , D ₂ , and a capacitor C. The switching elements A _a , A _r , A _f , A _g may be made of field effect transistors having a body diode, or may be made of other switching elements having the same or similar functions. The switching element A _{a is} connected between a power supply (or a power supply line) for supplying an address voltage V _p and a second terminal of the switching element A _H of the address selection circuit 220 _{1 to} 220 _m . The switching element A _{g is} connected between a power supply (or a power supply line) for supplying a ground voltage and the second terminal of the switching element A _H of the address selection circuit 220 _{1 to} 220 _m .

The capacitor C is connected in series between the power supply for supplying the address voltage V _p and the ground voltage. The first terminal of the inductor L is connected to the second terminal of the switching element A _H of the address selection circuit 220 _{1 to} 220 _m , respectively. The switching element Ar and the diode D ₁ are connected in series between the contact point of the capacitor C and the second terminal of the inductor L, and the diode D ₂ and the switching element A _f are connected in series. It is connected in series. The diodes D ₁ and D ₂ are for preventing current paths that may occur due to the body diodes formed in the switching elements _Ar and A _f , respectively, and may be removed if the body diodes do not exist.

And although shown as being a single power recovery circuit 210 connected to the even address selecting circuit in the 4 (220 ₁ ~220 _m), to the address selection circuit (220 ₁ ~220 _m) into groups each group The power recovery circuit 210 may be connected.

Next, driving of the plasma display panel according to an exemplary embodiment of the present invention will be described with reference to FIGS. 5 through 11.

According to an embodiment of the present invention, the pulse width of the address voltage V _p supplied to the address selection circuits 220 _{1 to} 220 _m is varied by varying the period during which the power recovery operation is performed according to the display pattern of the image signal transmitted from the outside. Variable. More specifically, the power recovery operation is not performed when the pattern of the video signal is a first pattern (for example, a full white pattern) having almost no reactive power consumption. As a result, the address voltage of the DC voltage is supplied to the address selection circuit. Further, when the reactive power consumption of the pattern is a second pattern (for example, a dot on / off pattern or a line on / off pattern) that is larger than or equal to a set value, the power recovery operation is performed in the first period so that the address voltage (the 1 address voltage). In addition, when the reactive power consumption of the pattern is a third pattern (for example, a monochromatic pattern) smaller than the set value, the power recovery operation is performed at a second period to supply an address voltage (second address voltage). Here, the second period is longer than the first period, and the pulse width of the second address voltage is wider than the pulse width of the first address voltage. In this embodiment, one scan line period is set as the first period and two scan line periods as the second period, but the present invention is not limited thereto.

The operation of the address driving circuit will be described below by taking the representative patterns shown in FIGS. 6 to 8 displayed on the screen in one subfield as an example. Such representative patterns include a dot on / off pattern, a line on / off pattern, and an address selection circuit 220 with a large number of switching changes of the address selection circuits 220 _{1 to} 220 _m . _There is a full white pattern with a small switching change of _{1 to} 220 _m ).

5 to 7 are conceptual views of a dot on / off pattern, a line on / off pattern, and a full white pattern, respectively.

The pattern is determined according to an input video signal, and the pattern is determined by switching of the address selection circuits 220 _{1 to} 220 _m . The switching change of the address selection circuit means that the turn-on / turn-off operations of the switching element A _H and the switching element A _L of the address selection circuit are repeated when the scan electrodes are sequentially selected. That is, when the scan electrodes are sequentially selected, when the address voltage and the ground voltage are alternately applied to the address electrodes, a lot of switching changes of the address selection circuit occur.

Referring to FIG. 5, the dot on / off pattern is a display pattern generated by alternately applying an address voltage to odd and even address electrodes when the scan electrodes are sequentially selected. For example, when the first scan electrode Y ₁ is selected, an address voltage is applied to the odd address electrodes A ₁ and A ₃ to select the odd column of the first row, and the second scan electrode Y _2. When () is selected, an address voltage is applied to the even-numbered address electrodes A ₂ and A ₄ to select light emission in the even-numbered column of the second row. That is, when scan electrode Y ₁ is selected, switching element A _H of odd-numbered address selection circuit is turned on, switching element A _L of even-numbered address selection circuit is turned on, and scan electrode Y ₂ is When selected, the switching element A _H of the even-numbered address selection circuit is turned on and the switching element A _L of the odd-numbered address selection circuit is turned on.

Referring to FIG. 6, in the line on / off pattern, when the first scan electrode Y ₁ is selected, address voltages are applied to all the address electrodes A _{1 to} A ₄ and the second scan electrode Y ₂ is selected. When the address voltage is not applied to all the address electrodes A _{1 to} A ₄ , the pattern is repeatedly displayed. That is, when the scan electrode Y ₁ is selected, the switching elements A _H of all the address selection circuits are turned on, and when the scan electrode Y ₂ is selected, the switching elements A _L of all the address selection circuits are turned on. do.

Referring to FIG. 7, the full white pattern is a display pattern generated by continuously applying address voltages to all address electrodes when the scan electrodes are sequentially selected. That is, the switching elements A _H of all the address selection circuits are always turned on.

As described above, the switching element A _L of the address selection circuit is periodically turned on in the dot on / off pattern and the line on / off pattern, but the switching element A _L is not turned on in the full white pattern.

In the following example, a full white pattern is used as the first pattern, and a dot on / off pattern and a line on / off pattern are used as the second pattern, and the remaining patterns except for the first and second patterns are used as the third pattern. Has been heard, but is not limited to such.

8 illustrates a plasma display panel driving method according to an exemplary embodiment of the present invention.

First, as shown in FIG. 8, an image signal input from the outside is input to the controller 400 and processed (S100). In the controller 400, the image signal is digitally converted and then gamma corrected and error diffusion processed, and then input to the pattern detector 410.

The pattern detector 410 examines the input digital image data to determine what pattern it is, and provides the pattern inspection result to the signal generator 420 (S110).

The signal generator 420 varies and outputs the address driving control signals S1 to S4 according to the pattern inspection result. In detail, when the pattern of the image data input as a result of the pattern inspection is the first pattern having almost no reactive power consumption, that is, the full white pattern turn, the address driving control signal is output so that the address voltage of the DC voltage is applied (S120). S130). That is, in the address drive control signal, S1, S2, and S4 are driven off (e.g., output at low level), that is, off, and S3 is driven, i.e., turned on (e.g., output at high level).

9 is a driving timing diagram of the power recovery driving circuit when the display pattern is the first pattern.

In the case of displaying the full white pattern in the circuit of FIG. 4, the switching elements A _H1 and A _H2 of the address selection circuits 220 _2i-1 and 220 _2i are always turned on while the scan electrodes are sequentially selected.

In this state, as shown in FIG. 9, the switching elements A _r , A _f , and A _g are turned off by the address driving control signals S1, S2, and S4, and the switching elements A are turned off by the address driving control signals S3. _a ) is turned on, and _a voltage V _{a is} applied to the address selection circuits 220 _{1 to} 220 _m . Therefore, an address voltage that maintains the V _a voltage state while the scan electrodes are sequentially selected is applied to the address electrode, whereby a full white pattern is displayed. In this case, the power recovery circuit does not operate substantially.

Meanwhile, in operation S140, the signal generator 420 may determine that the display pattern of the image data input as a result of the pattern inspection is a second pattern having a large amount of reactive power, that is, a dot on / off pattern or a line on / off pattern. The power recovery operation is performed in a first cycle, that is, one scan line cycle, to output an address driving control signal to supply an address voltage (S150).

10 is a driving timing diagram of the address driving circuit when the display pattern is the second pattern. Here, the operation change is sequential in four modes M1 to M4, and the mode change is caused by the operation of the switching element. The phenomenon called resonance is not a continuous oscillation but a change in voltage and current due to the combination of the inductor L and the panel capacitor C _p that occur at the turn-on of the switching elements _Ar and A _f .

When the dot on / off pattern is displayed, the turn-on / turn-off operation of the switching elements A _H1 and A _H2 and the switching elements A _L1 and A _L2 of the address selection circuits 220 _2i-1 and 220 _2i continues. Is repeated. It is assumed that before the mode starts, the capacitor C is charged with a voltage of V _a / 2 and the capacitance of the capacitor C is large, and thus serves as a power source for supplying the voltage C _a / 2 to the capacitor C.

In this state, as shown in Fig. 10, in mode 1, the address driving control signals S2, S3, S4 are turned off and S1 is turned on, so that the switching elements A _f , A _a , A _g are turned off and the switching elements ( Only A _r ) is turned on. Accordingly, a resonance path is formed of the capacitor C ₂ , the switching element _Ar , the diode D ₁ , and the inductor L. By this resonance path, the address voltage V _p increases and the capacitor C is discharged. As a result, the address voltage C _p is increased by the voltage V _a .

In mode 2, the address driving control signals S1, S2, S4 are turned off and S3 is turned on, so that the switching elements _Ar , A _f and A _g are turned off and only the switching elements A _a are turned on. Therefore, the address voltage V _p is maintained at the voltage V _a .

Next, in mode 3, the address driving control signals S1, S3, S4 are turned off and S2 is turned on so that the switching elements _Ar , A _a , A _g are turned off and only the switching element A _f is turned on. Therefore, a resonance path is formed by the inductor L, the diode D ₂ , the switching element A _f , and the capacitor C. By this resonance path, the address voltage V _p decreases, the reduced current (energy) is supplied to the capacitor C, and the capacitor C is charged with the voltage. As a result, the address voltage V _p increased to the voltage V _a by the principle of LC resonance is reduced to the ground voltage 0V.

In mode 4 (M4), the address drive control signals S1, S2, S3 are turned off and S4 is turned on so that the switching elements A _r , A _f , A _a are turned off and only the switching elements A _g are turned on. Thus, the address voltage is maintained at the ground voltage.

In this manner, the modes 1 to 4 (M1 to M4) are repeatedly performed in one scan line period to perform the address power recovery operation. The address voltage generated by the power recovery operation is supplied to the corresponding address electrode in accordance with the switching operation of the switching selection circuits 220 _{1 to} 220 _m .

In operation S140, the signal generator 420 may perform an address power recovery operation in a second period when the pattern of the image data input as a result of the pattern inspection is a third pattern having a reactive power smaller than a set value. The address drive control signal is output (S160 to S170).

11 is a driving timing diagram of the power recovery circuit when the display pattern is the third pattern.

As shown in FIG. 11, the address driving control signal is supplied to the power recovery circuit 210 so that the modes 1 to 4 (M1 to M4) are repeatedly performed in two scan line cycles. The switching operation in each mode is made as described above, and only the address drive control signal is switched based on two scan line periods, so that the power address recovery operation is performed in two scan line periods. As a result, as shown in FIG. 11, the address voltage according to the third pattern has a wider pulse width than the address voltage corresponding to the second pattern, resulting in a long address period. Thus, the discharge can be performed more efficiently.

As described above, in the exemplary embodiment of the present invention, the pulse width of the address voltage is varied by varying the period during which the power recovery operation is performed according to the display pattern, so that the pulse width of the address voltage increases when displaying a pattern in which reactive power is generated to some extent. As a result, the address discharge period is increased.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, an address discharge efficiency can be increased by varying a pulse width of an address voltage for addressing according to a display pattern. As a result, discharge failure is prevented and the display quality of the plasma display panel is improved.

Claims (17)

A display pattern detector for detecting a display pattern of input image data; A signal generator for varying and outputting an address driving control signal according to the display pattern; And An address driver configured to generate an address voltage having a variable pulse width corresponding to the display pattern by performing a power recovery operation according to the address driving control signal; Including; When the display pattern of the image data is the first pattern, the power recovery operation is not performed. When the display pattern of the image data is the second pattern, the power recovery operation is performed at a first period to generate a first address voltage. And when the display pattern of the image data is a third pattern, the power recovery operation is performed at a second period different from the first period to generate a second address voltage. The method of claim 1 The address driver At least one power recovery circuit configured to generate an address voltage by performing a power recovery operation according to the address driving control signal; And A plurality of address selection circuits for selecting one of the address voltage and the first voltage to supply the plasma display panel Driving device for a plasma display panel comprising a. The method of claim 2 And the first voltage is a ground voltage. delete The method of claim 1 And the address voltage is a DC voltage. The method of claim 1 And the first pattern is a full white pattern. The method of claim 1 And the second period is longer than the first period, and the second address voltage has a pulse width wider than a pulse width of the first address voltage. The method of claim 7, And the first period is one scan line period and the second period is two scan line periods. The method of claim 7, And the second pattern is a dot on / off pattern or a line on / off pattern. The method of claim 7, And the third pattern is a monochrome pattern. In the driving method of a plasma display panel, a) detecting a display pattern of input image data; b) generating a period in which a power recovery operation is performed according to the display pattern, and generating an address voltage having a variable pulse width according to the variable period; And c) selecting one of the address voltage and the first voltage and applying the same to the plasma display panel; Including, In step b), when the display pattern of the image data is the first pattern, the power recovery operation is not performed. When the display pattern of the image data is a pattern other than the first pattern, the power recovery operation is performed according to the display pattern. A method of driving a plasma display panel in which address periods having different pulse widths are generated by setting different periods to be performed. delete The method of claim 11, Step b) And when the display pattern of the image data is a second pattern, the power recovery operation is performed at a first period to generate a first address voltage. The method of claim 13, And the first period is one scan line period. The method of claim 11, Step b) And when the display pattern of the image data is a third pattern, the power recovery operation is performed in a second period to generate a second address voltage. The method of claim 15 And the second period is two scan line periods. The method according to claim 13 or 15. And a pulse width of the second address voltage is wider than a pulse width of the first address voltage.

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