KR100612347B1 - Plasma display device and driving method thereof - Google Patents

Abstract

The present invention discloses a method of driving a plasma display device. According to the present invention, the scan driving method is selectively applied according to the on / off pattern of the discharge cell. In this way, power loss in the address selection circuit can be reduced by reducing the number of switching of the address selection circuit.

Plasma display, address period, scanning pulse

Description

Plasma display device and driving method thereof {PLASMA DISPLAY DEVICE AND DRIVING METHOD THEREOF}

1 is a diagram schematically illustrating a configuration of a plasma display device according to an exemplary embodiment of the present invention.

2 is an address driving circuit diagram according to an embodiment of the present invention.

3 and 4 are diagrams showing a relationship between an intensity (on / off) pattern and an address signal waveform displayed on a screen in one subfield.

5 is a block diagram of a control unit according to an embodiment of the present invention.

6 is a flowchart illustrating an operation of a controller according to an exemplary embodiment of the present invention.

The present invention relates to a method of driving a plasma display device, and more particularly, to an address driving method of a plasma display device.

PDPs are flat display devices that display characters or images using plasma generated by gas discharge, and dozens to millions or more of pixels are arranged in a matrix according to their size.

According to the conventional PDP driving method, each subfield is composed of a reset period, an address period, and a sustain period.

The reset period serves to erase the wall charge state of the previous sustain discharge and to set up wall charge in order to stably perform the next address discharge. The address period is a period in which wall charges are accumulated on cells (addressed cells) that are turned on by selecting cells that are turned on and cells that are not turned on in the panel. The sustain period is a period in which discharge for actually displaying an image on the addressed cells is performed.

On the other hand, in the related art, in order to shorten the address period, a dual scan method is used in which scan electrodes are divided into two groups and scan pulses are simultaneously applied to two scan electrodes belonging to these groups. However, when the dual scan method is used, a manufacturing cost increases because a scan driver needs to be added.

Therefore, in recent years, in order to lower the manufacturing cost, a single scan method of applying scan pulses to one scan electrode again is used. However, when the single scan method is used, the power consumption in the address period is increased by about twice as much as when the dual scan method is used, and the power and heat generated by the address selection circuit are increased by about four times.

An object of the present invention is to provide a method of driving a plasma display device which can reduce power consumption in an address period.

According to an aspect of the present invention, there is provided a plasma display device including a plurality of address electrodes and a plurality of first electrodes arranged to intersect the address electrodes, wherein the plasma display panel displays image data. A plurality of switches electrically connected to a plurality of address electrodes, respectively, for selecting an address electrode to which an address voltage is applied, and a driving circuit for applying a driving voltage to the address electrode and the first electrode; A control unit for receiving an image signal from the controller and outputting a signal for controlling the address electrode and the first electrode to the driving circuit,

The control unit,

A control signal is applied to the driving circuit to apply a scan pulse to the plurality of first electrodes in one of a first scan method and a second scan method according to the discharge cell on / off pattern of the image signal.

At this time, the control unit,

An image data processor for correcting and outputting the image signal, a subfield data generator for converting the image signal from data in a frame unit to data in a subfield unit, and inspecting an on / off pattern of a discharge cell according to the image signal An on / off pattern detector, a scan method determiner that determines a scan method according to the on / off pattern, and a data converter that converts and outputs an output signal of the subfield data generator based on an output signal of the scan method determiner ,

The scanning method determination unit,

The number of switching per frame of the switch according to the first method currently applied is calculated, and if the calculated number of switching per frame is equal to or greater than a reference value, the switching is applied to the second scanning method.

One of the first scanning method and the first scanning method is a progressive method and the other is an interlaced method.

A driving method of a plasma display device according to an aspect of the present invention includes a plurality of address electrodes, a plurality of first electrodes arranged to intersect the address electrodes, and a driving voltage to the plurality of address electrodes and the plurality of first electrodes. In the driving method of a plasma display device comprising a driving circuit for supplying

The driving circuit includes a plurality of switches electrically connected to the plurality of address electrodes, respectively, for selecting an address electrode to which an address voltage is applied from among the plurality of address electrodes.

The driving method,

a) calculating the number of switching per frame of the switch according to the discharge cell on / off pattern of an image signal input from the outside based on the first scanning driving scheme currently applied; b) the calculated number of switching is a reference value If it is less than or equal to the first scan driving method is maintained, if the reference value is greater than the first scan driving method and the second scan driving method is selected and c) by applying the scan driving method determined in the step b) the plurality of Applying a scan pulse to the first electrode.

One of the first scanning method and the first scanning method is a progressive method and the other is an interlaced method,

In step c),

If the determined scan driving method is the interlace method, the data applied to the address electrode is rearranged.

The number of switching per frame is calculated by the following equation.

Where n _i is the number of switching in the i-th frame and N _d is the number of address frames.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

First, a plasma display device according to an exemplary embodiment of the present invention will be described with reference to FIG. 1.

1 schematically illustrates a configuration of a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the plasma display device according to the first embodiment of the present invention includes a plasma display panel 100, an address driver 200, a scan / sustain driver 300, and a controller 400. In FIG. 3, the scan and sustain driver 300 is illustrated as one block. However, the scan and sustain driver 300 is generally formed separately from the scan driver and the sustain driver.

The plasma display panel 100 includes a plurality of column address electrode extending in a direction (A ₁ ~A _m), the plurality of scan electrodes extending yirumyeonseo in pairs in the row direction (Y ₁ ~Y _n) and a plurality of sustain electrodes ( X _{1 to} X _n ). The address driver 200 applies an address signal for selecting a discharge cell to be displayed to receive the address driving control signal from the controller 400 to the address electrodes (A ₁ ~A _m). The scan / hold driver 300 receives the sustain discharge control signal from the controller 400 and alternately inputs a sustain discharge pulse to the scan electrodes Y _{1 to} Y _n and the sustain electrodes X _{1 to} X _n to discharge cells selected. Perform a maintenance discharge on. The control unit 400 receives an image signal from the outside, generates an address driving control signal and a sustain discharge control signal, and applies them to the address driver 200 and the scan / sustain driver 300, respectively.

The address driver 200, the scan / sustain driver 300, and the controller 400 are generally manufactured in the form of a printed circuit board (PCB) and mounted on a chassis base (not shown). The chassis base is disposed on the opposite side of the surface on which the image is displayed on the plasma display panel 100 so as to be coupled to the plasma display panel 100.

Hereinafter, an address driver circuit included in the address driver 200 will be described with reference to FIG. 3.

2 is a diagram illustrating an address driving circuit according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the address driving circuit according to the embodiment of the present invention includes a power recovery circuit 210 and a plurality of address selection circuits 220 _{1 to} 220 _m . The address selection circuits 220 _{1 to} 220 _{m are} connected to the plurality of address electrodes A _{1 to} A _m , respectively, and include two switches A _H and A _L for driving and grounding, respectively. For the switches A _H and A _L , a field effect transistor having a body diode may be used, or may be composed of other switches having the same or similar functions.

The first terminal is a power recovery circuit 210 of the driving switch (A _H), a second terminal is connected to the address electrodes (A ₁ ~A _m) of the panel capacitor (Cp), a driving switch (A _H) is turned on When an address voltage (V _a) is supplied from the power recovery circuit 210 is transmitted to the address electrodes (a ₁ ~A _m). The ground switch A _{L is} connected between the address electrodes A ₁ -A _m and the ground voltage (ground voltage in FIG. 6). When the ground switch A _L is turned on, the ground voltage A ₁ -A m is turned on. A _m ). In principle, since the driving switch A _H and the ground switch A _L are not turned on at the same time, it can be generally considered as a switching switch.

As described above, both switches A _H and A _{L of the} address selection circuits 220 ₁ to 220 _m respectively connected to the address electrodes A _{1 to} A _m are turned on or turned off by a control signal, thereby causing the address electrodes A to be turned off. ₁ ~A _m) an address voltage (Va) or a ground voltage is applied to. That is, in the address period, the address electrode to which the driving switch A _H is turned on and the address voltage Va is applied is selected, and the address electrode to which the ground voltage is applied is not selected because the ground switch A _L is turned on. Do not.

The power recovery circuit 210 includes switches Ar, Af, Aa, Ag, inductors L, diodes D1 and D2, and capacitors Ca. The switches Ar, Af, Aa, and Ag may be made of field effect transistors having body diodes, or may be made of other switches having the same or similar functions. The switches Aa and Ag are connected in series between a power supply (or a power supply line) supplying an address voltage Va and a power supply supplying a ground voltage, and the contacts of the switches Aa and Ag are connected to an address selection circuit 220 _1. It is connected to the 1st terminal of the drive switch _{AH of} (-220 _m ), and the 1st end of the inductor L. The switches Ar and Af are connected between the capacitor Ca and the second end of the inductor L to form a charge path and a discharge path, respectively. Diodes D1 and D2 are respectively connected on the charge path and the discharge path to prevent current from flowing back.

FIG address selection circuit, 2 (220 ₁ ~220 _m) to been shown as being a single power recovery circuit 210 connected to an address selection circuit for each group is divided into groups a (220 ₁ ~220 _m) The power recovery circuit 210 may be connected.

And although shown as being a single power recovery circuit 210 connected to the even address selecting circuit in 2 (220 ₁ ~220 _m), the address selecting circuits each group by dividing the (220 ₁ ~220 _m) into groups Each power recovery circuit 210 may be connected.

Meanwhile, a typical single scan driving method includes a progressive method of applying scan pulses in the order in which the scan electrodes are arranged from the top of the panel to the downward direction, and divides the scan electrodes into odd-numbered and even-numbered groups. There is an interlace method in which scan pulses are sequentially applied to groups and then scan pulses are sequentially applied to even-numbered groups.

However, since these systems have different order of the scan electrodes applying the scan pulses, the number of switching of the address selection circuit is different even if the same pattern is addressed.

In the following, the relationship between the contrast (on / off) pattern displayed on the screen and the address signal waveform in one subfield will be described along with the operation of the address driving circuit by taking the representative patterns shown in FIGS. 3 and 4 as an example. Such representative patterns include a dot on / off pattern or a line on / off pattern with a large change in the switching state of the address selection circuits 220 _{1 to} 220 _m .

3A, 3B, 4A, and 4B are conceptual views of a dot on / off pattern and a line on / off pattern, respectively.

This pattern is determined by the switching of the address selection circuits 220 _{1 to} 220 _m , and the switching elements A _a , A _g , A _r , and A _f of the power recovery circuit 210 are implemented in any case. The drive timing is the same. The change in the switching state of the address selection circuit means that the turn-on / turn-off operations of both switching elements A _H and A _L of the address selection circuit are repeated when the scan electrodes are sequentially selected. That is, when the scan electrodes are sequentially selected, when the address voltage and the ground voltage are alternately applied to the address electrodes, a large change in the switching state of the address selection circuit occurs.

First, the dot on / off pattern shown in FIG. 3A is even with the odd-numbered address electrodes A ₁ and A ₃ when the scan electrodes Y ₁ , Y ₂ , Y ₃ , and Y ₄ are sequentially selected according to the progressive method. The contrast display pattern is generated by alternately applying an address voltage to the first address electrodes A ₂ and A ₄ . For example, when the first scan electrode Y ₁ is selected, an address voltage is applied only to the odd address electrodes A ₁ and A ₃ so that the odd column of the first row is selected, and the second scan electrode Y ₂ is selected. ) Is selected, the address voltage is applied only to the even-numbered address electrodes A ₂ and A ₄ so that light emission is selected in the even-numbered column of the second row. That is, when the scan electrode Y ₁ is selected, all of the driving switching elements A _{H of the} odd-numbered address selection circuit are turned on and all of the ground switching elements A _L of the even-numbered address selection circuit are turned on. When (Y ₂ ) is selected, the driving switching element A _H of the even-numbered address selection circuit is turned on and the ground switching element A _L of the odd-numbered address selection circuit is turned on. As described above, since the switching element A _H and the switching element A _L repeatedly turn on / off the operation alternately, power loss in the address selection circuit is large.

On the other hand, when the scan electrodes are selected according to the interlace method, when the odd scan electrodes Y ₁ and Y ₃ are selected, the address voltage is applied only to the odd address electrodes A ₁ and A ₃ so that the first row and the third scan electrodes are selected. When the odd-numbered column of the first row is selected and the even-numbered scan electrodes Y ₂ and Y ₄ are selected, the address voltage is applied only to the even-numbered address electrodes A ₂ and A ₄ so that the second and fourth rows Light emission is selected in even columns. That is, when the scan electrodes Y ₁ and Y ₃ are selected, all of the driving switching elements A _{H of the} odd-numbered address selection circuit are turned on and all of the ground switching elements A _L of the even-numbered address selection circuit are turned on. When the scan electrodes Y ₂ and Y ₄ are selected, the driving switching element A _H of the even-numbered address selection circuit is turned on and the ground switching element A _L of the odd-numbered address selection circuit is turned on. Therefore, power loss in the address selection circuit is smaller than that of the progressive method.

In addition, the dot on / off pattern shown in FIG. 3B has odd-numbered address electrodes A ₁ and A ₃ and even-numbered address electrodes A ₂ and A ₄ when the scan electrode is selected according to the progressive method according to the interlace method. The contrast display pattern is generated by applying address voltage alternately. That is, since the switching element A _H and the switching element A _L repeatedly turn on / off the operation alternately, the power loss in the address selection circuit is large.

On the other hand, when the scan electrodes are selected according to the progressive method, when the scan electrodes Y ₁ and Y ₂ are selected, the address voltage is applied only to the odd-numbered address electrodes A ₁ and A ₃ , and the scan electrodes Y ₃ , When Y ₄ ) is selected, an address voltage is applied only to even-numbered address electrodes A ₂ and A ₄ . Therefore, power loss in the address selection circuit is smaller than that of the interlace method.

Next, in the line on / off pattern shown in FIG. 4A, when a scan pulse is applied in a progressive manner, address voltages are applied to all address electrodes A _{1 to} A ₄ when the first scan electrode Y ₁ is selected. However, when the second scan electrode Y ₂ is selected, the display pattern in which the address voltage is not applied to all the address electrodes A _{1 to} A ₄ is repeated. That is, the scan electrodes (Y ₁₎ all of the driving switching element (A _H) of the address selecting circuit is turned on, the scan electrode (Y ₂₎ All ground switching of the address selecting circuit elements (A _L), when this is driven when the driven Is turned on. Therefore, the power loss in the address selection circuit is large.

However, when the scan pulse is applied according to the interlace method, when the odd scan electrodes Y ₁ and Y ₃ are selected, the address voltage is applied to all the address electrodes, and the even scan electrodes Y ₂ and Y ₄ are applied. When this is selected, no address voltage is applied to all address electrodes. Therefore, power loss in the address selection circuit is smaller than that of the progressive method.

In addition, the line on / off pattern shown in FIG. 4B repeats an operation in which no address voltage is applied or no address voltage is applied to all address electrodes when the scan electrode is selected according to the progressive method according to the interlace method. That is, since the switching element A _H and the switching element A _L repeatedly turn on / off the operation alternately, the power loss in the address selection circuit is large.

On the other hand, when the scan electrodes are selected according to the progressive method, when the scan electrodes Y ₁ and Y ₂ are selected, the address voltage is applied to all the address electrodes, and when the scan electrodes Y ₃ and Y ₄ are selected, The address voltage is not applied to the address electrode. Therefore, power loss in the address selection circuit is smaller than that of the interlace method.

Therefore, the scan driving method according to the embodiment of the present invention selects a single scanning method having a small number of switching of the address selection circuit according to the on / off pattern of the discharge cell, and applies a scan pulse to the scan electrode, thereby losing power in the address selection circuit. Reduce

5 is a block diagram of the control unit 400 according to an embodiment of the present invention.

As shown in FIG. 5, the controller 400 according to an exemplary embodiment of the present invention includes an image data processor 410, a subfield data generator 420, a data pattern detector 430, and a scan method determiner 440. And a data converter 450.

The image data processor 410 corrects and outputs an image signal, and the subfield data generator 420 converts the corrected frame-specific image signal into data for driving the panel in units of subfields. The data pattern detection unit 430 examines the on / off pattern of the video signal data for each subfield, and the scanning method determination unit 440 selects a preferred scanning method according to the on / off pattern of the video signal data for each subfield. The data converter 450 converts the output signal of the subfield data generator 420 according to the determination result of the scan method determiner 440 and outputs the output signal to the driver.

6 is a flowchart illustrating an operation process of the controller 400 according to an exemplary embodiment of the present invention.

As shown in FIG. 6, first, the image data processor 410 corrects an image signal input from the outside (S601), and the subfield data generator 420 converts the corrected image signal for each frame into subfield units. In operation S602, the data pattern detector 430 detects an on / off pattern of image signal data for each subfield (S603).

Next, the scanning method determination unit 440 determines the average number of switching per frame of the address selection circuit when the scanning method currently applied to the on / off pattern of the data for each subfield output from the data pattern detection unit 430 is continuously applied. To calculate (S604). If the calculated number of switching is greater than or equal to the predetermined value, the scan driving method is changed (S606). In this case, the scanning method applied during the initial driving may be arbitrarily set to any one of a progressive method and an interlace method.

The number of switching of the address selection circuit per frame is calculated by the following equation.

Where n _i is the number of switching in the i-th frame and N _d is the number of address frames.

That is, when the progressive method is being applied, if the number of switching per frame k is less than the reference switching number M, the progressive method is continuously applied, and if k is larger than M, the interlace method is switched.

Similarly, if k is less than M when the current interlacing method is being applied, the progressive method is continuously applied, and if k is greater than M, the progressive mode is switched.

In addition, the scan method determination unit 440 outputs scan data according to the set scan method to the scan driver in the scan / sustain driver 300 (S607), and the scan driver determines the scan method according to the determination result of the scan method determiner 440. Scan pulses are applied to the scan electrodes to conform to the progressive or interlaced methods. In this case, the scan driver is designed to operate in the progressive mode or the interlaced mode, which will be omitted by the person skilled in the art.

Next, the data converter 450 rearranges data to be applied to the address electrode according to the determination result of the scanning method determination unit 440. That is, when the progressive method is applied, the address data generated in step S602 is output to the address driver 200 as it is, and when the interlace method is applied, the address data is rearranged so as to correspond to the order in which the scan pulses are applied. Output to the driver 200 (S609).

By selectively using the scan driving method in accordance with the on / off pattern of the discharge cell, the number of switching of the address selection circuit is reduced, so that power loss in the address selection circuit can be reduced.

Although the preferred embodiment of the present invention has been described in detail above, the present invention is not limited thereto, and various other changes and modifications are possible.

As described above, according to the exemplary embodiment of the present invention, power loss in the address selection circuit can be reduced by selectively using the scan driving method according to the on / off pattern of the discharge cell to reduce the number of switching of the address selection circuit.

Claims (8)

A plasma display panel including a plurality of address electrodes and a plurality of first electrodes arranged to intersect the address electrodes, the plasma display panel displaying image data; A driving circuit electrically connected to each of the plurality of address electrodes, the plurality of switches for selecting an address electrode to which an address voltage is applied, the driving circuit applying a driving voltage to the address electrode and the first electrode; And A control unit for receiving an image signal from an external device and outputting a signal for controlling the address electrode and the first electrode to the driving circuit; The control unit, An image data processor to correct and output the image signal; A subfield data generator for converting the video signal from data in frame units to data in subfield units; An on / off pattern detector for inspecting an on / off pattern of a discharge cell according to the image signal; The number of switching per frame of the switch according to the first scanning method currently applied to the output of the on / off pattern detection unit is calculated, and if the calculated number of switching per frame is equal to or greater than a reference value, it is converted into the second scanning method. Scanning method determination unit, and A data converter converting and outputting an output signal of the subfield data generator based on the output signal of the scan method determination unit; Plasma display panel device comprising a. delete delete The method of claim 1, One of the first scanning method and the second scanning method is a progressive method and the other is an interlaced method. Plasma display device. A plurality of address electrodes, a plurality of first electrodes arranged to intersect the address electrodes, and a driving circuit for supplying driving voltages to the plurality of address electrodes and the plurality of first electrodes; In the method, The driving circuit includes a plurality of switches electrically connected to the plurality of address electrodes, respectively, for selecting an address electrode to which an address voltage is to be applied, The driving method, a) calculating the number of switching per frame of the switch according to a discharge cell on / off pattern of an image signal input from the outside based on a first scanning driving scheme currently applied; b) maintaining the first scan driving method when the calculated number of switching for each frame is equal to or less than a reference value, and selecting a second scan driving method different from the first scan driving method when the calculated number of switching for each frame is equal to or less than a reference value; And c) applying a scan pulse to the plurality of first electrodes by applying the scan driving method determined in step b); Method of driving a plasma display device comprising a. The method of claim 5, One of the first scanning method and the second scanning method is a progressive method and the other is an interlaced method. Method of driving a plasma display device comprising a. The method of claim 6, In step c), Rearranging data applied to the address electrode when the determined scan driving method is the interlace method; A method of driving a plasma display device. The method of claim 5, The number of switching per frame is calculated by the following equation.

Where n _i is the number of switching in the i-th frame and N _d is the number of address frames.

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