KR100563106B1 - 보상 버퍼 제어 방법 및 장치 - Google Patents

보상 버퍼 제어 방법 및 장치 Download PDF

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Publication number
KR100563106B1
KR100563106B1 KR1020027004795A KR20027004795A KR100563106B1 KR 100563106 B1 KR100563106 B1 KR 100563106B1 KR 1020027004795 A KR1020027004795 A KR 1020027004795A KR 20027004795 A KR20027004795 A KR 20027004795A KR 100563106 B1 KR100563106 B1 KR 100563106B1
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South Korea
Prior art keywords
compensation value
compensation
digital
integrated circuit
value
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Expired - Fee Related
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KR1020027004795A
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English (en)
Korean (ko)
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KR20020060712A (ko
Inventor
포슬리브라이언
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인텔 코오퍼레이션
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Application filed by 인텔 코오퍼레이션 filed Critical 인텔 코오퍼레이션
Publication of KR20020060712A publication Critical patent/KR20020060712A/ko
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Publication of KR100563106B1 publication Critical patent/KR100563106B1/ko
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Non-Silver Salt Photosensitive Materials And Non-Silver Salt Photography (AREA)
  • Record Information Processing For Printing (AREA)
  • Developing Agents For Electrophotography (AREA)
KR1020027004795A 1999-10-15 2000-09-27 보상 버퍼 제어 방법 및 장치 Expired - Fee Related KR100563106B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/418,762 1999-10-15
US09/418,762 US6300798B1 (en) 1999-10-15 1999-10-15 Method and apparatus for controlling compensated buffers

Publications (2)

Publication Number Publication Date
KR20020060712A KR20020060712A (ko) 2002-07-18
KR100563106B1 true KR100563106B1 (ko) 2006-03-27

Family

ID=23659472

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Application Number Title Priority Date Filing Date
KR1020027004795A Expired - Fee Related KR100563106B1 (ko) 1999-10-15 2000-09-27 보상 버퍼 제어 방법 및 장치

Country Status (8)

Country Link
US (1) US6300798B1 (https=)
JP (1) JP2003512753A (https=)
KR (1) KR100563106B1 (https=)
AU (1) AU7722200A (https=)
DE (1) DE10085097B4 (https=)
GB (1) GB2371694B (https=)
TW (1) TW517454B (https=)
WO (1) WO2001029967A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6545522B2 (en) * 2001-05-17 2003-04-08 Intel Corporation Apparatus and method to provide a single reference component for multiple circuit compensation using digital impedance code shifting
US6535047B2 (en) * 2001-05-17 2003-03-18 Intel Corporation Apparatus and method to use a single reference component in a master-slave configuration for multiple circuit compensation
US6633178B2 (en) 2001-09-28 2003-10-14 Intel Corporation Apparatus and method for power efficient line driver
JP4502177B2 (ja) * 2003-10-14 2010-07-14 ルネサスエレクトロニクス株式会社 出力回路
US7009894B2 (en) * 2004-02-19 2006-03-07 Intel Corporation Dynamically activated memory controller data termination

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4079456A (en) 1977-01-24 1978-03-14 Rca Corporation Output buffer synchronizing circuit having selectively variable delay means
JPH0792492B2 (ja) 1986-11-28 1995-10-09 日立電子エンジニアリング株式会社 電子デバイス駆動回路
US4975598A (en) * 1988-12-21 1990-12-04 Intel Corporation Temperature, voltage, and process compensated output driver
JPH0583111A (ja) * 1991-09-24 1993-04-02 Nec Ic Microcomput Syst Ltd Ｃｍｏｓ集積回路
US5303191A (en) * 1992-01-23 1994-04-12 Motorola, Inc. Memory with compensation for voltage, temperature, and processing variations
US5334885A (en) 1993-01-13 1994-08-02 At&T Bell Laboratories Automatic control of buffer speed
US5444406A (en) * 1993-02-08 1995-08-22 Advanced Micro Devices, Inc. Self-adjusting variable drive strength buffer circuit and method for controlling the drive strength of a buffer circuit
KR100302890B1 (ko) 1993-06-08 2001-11-22 클라크 3세 존 엠. 프로그램가능한cmos버스및전송라인드라이버
JPH0722597A (ja) 1993-06-23 1995-01-24 Kawasaki Steel Corp 半導体集積回路装置
US5548201A (en) 1994-09-13 1996-08-20 Norand Corporation Battery charging method and apparatus with thermal mass equalization
DE4441523C1 (de) * 1994-11-22 1996-05-15 Itt Ind Gmbh Deutsche Digitale Treiberschaltung für eine integrierte Schaltung
US5640122A (en) * 1994-12-16 1997-06-17 Sgs-Thomson Microelectronics, Inc. Circuit for providing a bias voltage compensated for p-channel transistor variations
US5594373A (en) * 1994-12-20 1997-01-14 Sgs-Thomson Microelectronics, Inc. Output driver circuitry with selective limited output high voltage
US5883801A (en) 1996-05-14 1999-03-16 Microwave Science, Llc Method and apparatus for managing electromagnetic radiation usage
US5870001A (en) 1996-10-22 1999-02-09 Telefonaktiebolaget L M Ericsson (Publ) Apparatus, and associated method, for calibrating a device
US5959481A (en) * 1997-02-18 1999-09-28 Rambus Inc. Bus driver circuit including a slew rate indicator circuit having a one shot circuit
US5869983A (en) * 1997-03-24 1999-02-09 Intel Corporation Method and apparatus for controlling compensated buffers
US6031385A (en) 1997-03-24 2000-02-29 Intel Corporation Method and apparatus for testing compensated buffer circuits
US5898321A (en) 1997-03-24 1999-04-27 Intel Corporation Method and apparatus for slew rate and impedance compensating buffer circuits
US6092030A (en) * 1997-04-02 2000-07-18 Credence Systems Corporation Timing delay generator and method including compensation for environmental variation
JPH1117516A (ja) 1997-06-10 1999-01-22 Ind Technol Res Inst 制御されたスルーレートを有する高速及び低速出力バッファー
US5912569A (en) * 1997-09-22 1999-06-15 Cypress Semiconductor Corp. Methods, circuits and devices for improving crossover performance and/or monotonicity, and applications of the same in a universal serial bus (USB) low speed output driver

Also Published As

Publication number Publication date
JP2003512753A (ja) 2003-04-02
AU7722200A (en) 2001-04-30
GB2371694B (en) 2004-07-21
WO2001029967A1 (en) 2001-04-26
DE10085097B4 (de) 2008-12-18
HK1044639A1 (en) 2002-10-25
US6300798B1 (en) 2001-10-09
GB2371694A (en) 2002-07-31
GB0210910D0 (en) 2002-06-19
DE10085097T1 (de) 2002-09-19
TW517454B (en) 2003-01-11
KR20020060712A (ko) 2002-07-18

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