KR100554137B1 - Filter circuit - Google Patents
Filter circuit Download PDFInfo
- Publication number
- KR100554137B1 KR100554137B1 KR1019980038483A KR19980038483A KR100554137B1 KR 100554137 B1 KR100554137 B1 KR 100554137B1 KR 1019980038483 A KR1019980038483 A KR 1019980038483A KR 19980038483 A KR19980038483 A KR 19980038483A KR 100554137 B1 KR100554137 B1 KR 100554137B1
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- voltage source
- analog voltage
- digital
- digital voltage
- filter circuit
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
- H03H1/0007—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network of radio frequency interference filters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
Abstract
1.청구범위에 기재된 발명이 속한 기술분야1. Technical field to which the invention described in the claims belongs
본 발명은 아날로그 전압원과 디지털 전압원을 동시에 사용하는 전원전압 회로의 잡음 제거를 위한 필터 회로에 관한 것이다.The present invention relates to a filter circuit for noise reduction of a power supply voltage circuit using an analog voltage source and a digital voltage source at the same time.
2.발명이 해결하려고 하는 기술적 과제2. Technical problem that the invention tries to solve
디지털 전압원에 의한 아날로그 전압원의 잡음을 제거함.Eliminates noise from analog voltage sources by digital voltage sources.
3.발명의 해결방법의 요지3. Summary of the solution of the invention
본 발명은 아날로그 전압원과 디지털 전압원간에 잡음 제거를 위한 필터 회로를 접속함.The present invention connects a filter circuit for noise cancellation between an analog voltage source and a digital voltage source.
4.발명의 중요한 용도4. Important uses of the invention
잡음 제거 회로.Noise Canceling Circuit.
Description
본 발명은 아날로그 전압원(AVcc)과 디지털 전압원(DVcc)을 공용으로 사용하는 전원전압(Vcc) 회로의 잡음(Noise) 제거를 위한 필터 회로에 관한 것이다.The present invention relates to a filter circuit for noise cancellation of a power supply voltage (Vcc) circuit using an analog voltage source (AVcc) and a digital voltage source (Dvcc) in common.
도 1은 레지스터 듀얼 인라인 메모리 모듈(Dual Inline Memory Module; 이하, DIMM이라 함)에서 위상 동기(Phase Locked Loop; 이하, PLL이라 함) 회로의 블록도이다. PLL 회로(1)는 아날로그 전압원(AVcc)에 의해 구동되고, 레지스터 또는 에스디램(SDRAM)(2)은 디지털 전압원(DVcc)에 의해 각각 구동된다. 그러나, 레지스터 DIMM에서 PLL을 사용하는 데 있어서, 디지털 전압원(DVcc)에 의한 잡음이 PLL의 아날로그 전압원(AVcc)에 그대로 전달되어 PLL의 전원전압 마진(Vcc margine)과 지터(Jitter)를 흔들어 놓는 문제가 레지스터 DIMM을 설계하는데 있어서 가장 큰 문제점으로 대두 되어왔다.1 is a block diagram of a phase locked loop (hereinafter referred to as a PLL) circuit in a register dual inline memory module (hereinafter referred to as a DIMM). The PLL circuit 1 is driven by an analog voltage source AVcc, and the resistor or SDRAM SDRAM 2 is driven by a digital voltage source DVcc, respectively. However, when using a PLL in a resistor DIMM, noise caused by the digital voltage source (DVcc) is transmitted to the analog voltage source (AVcc) of the PLL as it is, causing the power supply voltage margin (Vcc margine) and jitter of the PLL to be shaken. Has become the biggest problem in designing register DIMMs.
따라서, 본 발명은 아날로그 전압원(AVcc)과 디지털 전압원(DVcc)간에 잡음 제거를 위한 필터 회로를 구성함으로써, 상기한 단점을 해결할 수 있는 필터 회로를 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a filter circuit that can solve the above disadvantages by configuring a filter circuit for noise cancellation between an analog voltage source AVcc and a digital voltage source DVcc.
상술한 목적을 달성하기 위한 본 발명은 상기 아날로그 전압원 및 상기 디지털 전압원간에 접속되며 상기 디지털 전압원의 전압 변화 폭을 줄여 상기 아날로그 전압원으로 공급하는 저항과, 상기 아날로그 전압원 및 접지단자 간에 접속되며 중간 주파수 및 고주파 성분의 잡음을 제어하기 위한 제 1 및 제 2 캐패시터와, 상기 아날로그 전압원 및 접지단자간에 접속되며 저주파 성분의 잡음을 제거하기 위한 제 3 캐패시터와, 상기 디지털 전압원 및 상기 접지단자간에 병렬로 접속되며 상기 디지털 전압원으로 유입되는 중간 주파수 및 고주파 성분의 잡음을 제거하기 위한 제 4 및 제 5 캐패시터를 포함하여 구성된 것을 특징으로 한다. The present invention for achieving the above object is connected between the analog voltage source and the digital voltage source, the resistance of the voltage change of the digital voltage source is supplied to the analog voltage source, and connected between the analog voltage source and the ground terminal, the intermediate frequency and A first capacitor and a second capacitor for controlling noise of a high frequency component, a third capacitor connected between the analog voltage source and a ground terminal, and a third capacitor for removing noise of a low frequency component, and connected in parallel between the digital voltage source and the ground terminal. And fourth and fifth capacitors for removing noise of intermediate frequency and high frequency components introduced into the digital voltage source.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2는 본 발명에 따른 필터 회로도이다. PLL 회로(1)에는 아날로그 전압원(AVcc)이 접속된다. 또한, 레지스터 또는 에스디램(SDRAM)(2)에는 디지털 전압원(DVcc)이 접속된다. 상기 아날로그 전압원(AVcc)과 상기 디지털 전압원(DVcc)간에는 저항(R)이 접속된다. 상기 아날로그 전압원(AVcc) 및 접지단자(Vss)간에는 제 1 내지 제 3 캐패시터(C1 내지 C3)가 병렬로 접속된다. 상기 디지털 전압원(DVcc) 및 접지단자(Vss)간에는 제 4 및 제 5 캐패시터(C4 및 C5)가 병렬로 접속된다.2 is a filter circuit diagram according to the present invention. The analog voltage source AVcc is connected to the PLL circuit 1. In addition, a digital voltage source DVcc is connected to the resistor or SDRAM 2. A resistor R is connected between the analog voltage source AVcc and the digital voltage source DVcc. First to third capacitors C1 to C3 are connected in parallel between the analog voltage source AVcc and the ground terminal Vss. Fourth and fifth capacitors C4 and C5 are connected in parallel between the digital voltage source DVcc and the ground terminal Vss.
제 3 캐패시터(C3)는 저주파 잡음(Low frequency noise)을 제거하기 위한 디커플링 캐패시터(Decoupling Cap.)로 10㎌의 큰 용량이 사용된다.The third capacitor C3 is a decoupling capacitor for removing low frequency noise, and a large capacity of 10 Hz is used.
또한, 제 1 및 제 2 캐패시터(C1 및 C2)와 제 4 및 제 5 캐패시터(C4 및 C5)는 중간 주파수 또는 고주파 잡음(MID_HIGH frequency noise)을 제거하기 위한 디커플링 캐패시터(Decoupling Cap.)로, C1:C2:C4:C5의 비율은 1:0.01:0.1:0.01의 비율을 갖는다.In addition, the first and second capacitors C1 and C2 and the fourth and fifth capacitors C4 and C5 are decoupling capacitors for removing intermediate frequency or high frequency noise (MID_HIGH frequency noise). The ratio of: C2: C4: C5 has a ratio of 1: 0.01: 0.1: 0.01.
도 3은 도 2의 등가 회로도이다. 아날로그 전압원(AVcc)과 디지털 전압원(DVcc)의 전압을 각각 3V, 내부저항을 각각 5Ω이라 가정하면, 디지털 전압원(DVcc)의 경우 파워 온(Power on)시, 전압이 2V 정도까지 다운(Down)되게 된다. 즉, 디지털 전압원(DVcc)의 전압이 3V에서 2V로 떨어지면, 아날로그 전압원(AVcc)에서 디지털 전압원(DVcc)으로 저항(R)을 통해 전류가 흐르게 되어 전압 강하가 일어나게 된다. 즉, 파워 온시 PLL 회로에는 5㎃의 전류가 흐르게 된다. 이때, 저항(R) 값을 190Ω으로 가정하면, 저항(R) 양단에 걸리는 전압은 0.95V가 걸리게 된다. 디지털 전압원(DVcc)의 내부 저항에는 0.025V의 전압이 걸리게 된다. 따라서, 제 1 노드(a)에는 2.975V의 전압이 걸리게 된다. 그러므로, 상기 디지털 전압원(DVcc)의 전압이 3V에서 2V의 전압으로 떨어지더라도 저항(R) 값에 의해 실제적으로 제 1 노드(a)에는 3V의 전압에서 2.75V의 전압으로 걸리게되어 전원전압(Vcc)의 변화 폭이 작아지게 된다.3 is an equivalent circuit diagram of FIG. 2. Assuming that the voltages of the analog voltage source (AVcc) and the digital voltage source (DVcc) are 3V and the internal resistance is 5 s, respectively, the voltage is down to about 2V when the power is turned on in the case of the digital voltage source (DVcc). Will be. That is, when the voltage of the digital voltage source DVcc drops from 3V to 2V, a current flows through the resistor R from the analog voltage source AVcc to the digital voltage source DVcc and a voltage drop occurs. That is, a current of 5 mA flows through the PLL circuit at power on. At this time, if the value of the resistor R is assumed to be 190 kV, the voltage across the resistor R is 0.95V. The internal resistance of the digital voltage source DVcc is subjected to a voltage of 0.025V. Therefore, the voltage of 2.975V is applied to the first node a. Therefore, even when the voltage of the digital voltage source DVcc drops from 3V to 2V, the first node a is actually caught from a voltage of 3V to a voltage of 2.75V by the value of the resistor R and thus the power supply voltage Vcc. ), The width of change becomes small.
도 4는 본 발명을 설명하기 위해 도시한 또 다른 도면으로서, 디지털 전압 원(DVcc)의 전압을 4.2V, 아날로그 전압원(AVcc)의 전압을 3.7V의 안정된 전압을 얻고자 할 경우, 도 3의 제 2 노드(b)의 전압은 4.2V, 제 1 노드(a)의 전압은 3.7V로 된다고 가정하면, 저항(R)을 통해 0.5V의 전압을 보상해 주면 된다. 즉, PLL 회로의 턴온(Turn on) 전류가 5㎃ 이므로, 저항(R) 값은 R=0.5V/(0.5×10-2)=100Ω으로 된다. 즉, 100Ω의 저항을 접속함으로써, 디지털 전압원(DVcc)의 전압이 4.2V로 상승되더라도 3.7V 이하의 안정된 아날로그 전압을 얻을 수 있게 된다.FIG. 4 is a diagram for explaining the present invention. When the voltage of the digital voltage source DVcc is 4.2V and the voltage of the analog voltage source AVcc is 3.7V, Assuming that the voltage of the second node (b) is 4.2V and the voltage of the first node (a) is 3.7V, the voltage of 0.5V may be compensated for through the resistor (R). That is, since the turn-on current of the PLL circuit is 5 mA, the resistance R becomes R = 0.5 V / (0.5 × 10 −2 ) = 100 mA. That is, by connecting a resistor of 100 kV, stable analog voltage of 3.7 V or less can be obtained even when the voltage of the digital voltage source DVcc rises to 4.2V.
상술한 바와 같이 본 발명에 의하면 아날로그 전압원과 디지털 전압원간에 잡음 제거를 위한 필터 회로를 접속함으로써, 디지털 전압원에 의한 아날로그 전압원의 잡음을 제거할 수 있는 탁월한 효과가 있다.As described above, according to the present invention, by connecting a filter circuit for noise removal between the analog voltage source and the digital voltage source, there is an excellent effect that can remove the noise of the analog voltage source by the digital voltage source.
도 1은 레지스터 듀얼 인라인 메모리 모듈(DIMM)에서 위상 동기(PLL) 회로의 블록도.1 is a block diagram of a phase locked (PLL) circuit in a register dual inline memory module (DIMM).
도 2는 본 발명에 따른 필터 회로도.2 is a filter circuit diagram according to the present invention;
도 3은 도 2의 등가회로도.3 is an equivalent circuit diagram of FIG. 2.
도 4는 본 발명을 설명하기 위한 도시한 또 다른 도면.4 is yet another diagram illustrating the invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1: 위상 동기 회로 2: 레지스터 또는 SDRAM1: phase-lock circuit 2: register or SDRAM
R: 저항 C1 내지 C5: 캐패시터R: resistors C1 to C5: capacitors
AVcc: 아날로그 전압원 DVcc: 디지털 전압원AVcc: analog voltage source DVcc: digital voltage source
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980038483A KR100554137B1 (en) | 1998-09-17 | 1998-09-17 | Filter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980038483A KR100554137B1 (en) | 1998-09-17 | 1998-09-17 | Filter circuit |
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| Publication Number | Publication Date |
|---|---|
| KR20000020058A KR20000020058A (en) | 2000-04-15 |
| KR100554137B1 true KR100554137B1 (en) | 2006-05-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980038483A KR100554137B1 (en) | 1998-09-17 | 1998-09-17 | Filter circuit |
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| KR (1) | KR100554137B1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04348608A (en) * | 1990-03-29 | 1992-12-03 | Nokia Mobile Phones Ltd | Method of reducing microphonic noise and circuit thereof |
| JPH09284076A (en) * | 1995-09-29 | 1997-10-31 | Nippon Baa Braun Kk | Differential filter circuit and its integrate circuiut structure |
| KR100189961B1 (en) * | 1992-04-09 | 1999-06-01 | 윤종용 | Noise elimination apparatus |
| KR200178361Y1 (en) * | 1995-12-19 | 2000-05-01 | 정몽규 | Power source terminal for automobile electronic control system with noise filter |
-
1998
- 1998-09-17 KR KR1019980038483A patent/KR100554137B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04348608A (en) * | 1990-03-29 | 1992-12-03 | Nokia Mobile Phones Ltd | Method of reducing microphonic noise and circuit thereof |
| KR100189961B1 (en) * | 1992-04-09 | 1999-06-01 | 윤종용 | Noise elimination apparatus |
| JPH09284076A (en) * | 1995-09-29 | 1997-10-31 | Nippon Baa Braun Kk | Differential filter circuit and its integrate circuiut structure |
| KR200178361Y1 (en) * | 1995-12-19 | 2000-05-01 | 정몽규 | Power source terminal for automobile electronic control system with noise filter |
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| Publication number | Publication date |
|---|---|
| KR20000020058A (en) | 2000-04-15 |
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