JP2003195955A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of suppressing voltage fluctuations in step-down voltage. <P>SOLUTION: An internal power supply step-down circuit in the semiconductor integrated circuit comprises an internal voltage generating circuit 1 generating an internal voltage Vint1 from a power supply voltage Vcc, and a comparison circuit 2 controlling the operation of the internal voltage generating circuit 1 so that the internal reference voltage Vmon1 of the internal voltage generating circuit 1 matches the predetermined reference voltage. The comparison circuit 2 has a current mirror circuit 3, a difference amplifier 4, and transistors Q7 and Q8 connected to corresponding gate terminals of transistors Q2 and Q3 in the current mirror circuit 3, respectively. To make gate capacitance of the transistors Q2 and Q3 constituting the current mirror circuit 3 in internal power supply step-down circuits 11a-11d different from one another to correspond the internal power supply step-down circuits 11a-11d respectively, the internal power supply step-down circuits 11a-11d start charging operation one by one on stabilized capacity element Cint at the time of switching from a stand-by state to an operation state. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit including a circuit for generating a step-down voltage obtained by stepping down a power supply voltage and a circuit which operates at the step-down voltage.

[0002]

2. Description of the Related Art As semiconductor memories such as SRAM have been highly integrated, it has become more common to provide a plurality of circuit blocks inside the memory, each circuit block operating at a plurality of power supply voltages having different potentials. It is convenient to generate the power supply voltage used only inside the memory inside the memory. For this reason,
This type of memory is provided with a step-down circuit that generates an internal voltage by using a power supply voltage supplied from the outside.

FIG. 9 is a block diagram showing a schematic configuration of a conventional internal power supply voltage down converter. As shown in the figure, in the conventional internal power supply voltage down circuit, an internal voltage generation circuit 1 that generates an internal voltage Vint from an externally supplied power supply voltage Vcc and an internal reference voltage Vmon of the internal voltage generation circuit 1 are a predetermined reference voltage. And a comparison circuit 2 for controlling the operation of the internal voltage generation circuit 1 so that

The internal voltage generation circuit 1 includes a PMOS transistor Q1 whose source terminal is supplied with a power supply voltage Vcc, resistors R1 and R2 connected in series between the drain terminal of the PMOS transistor Q1 and a ground terminal, and a PMOS transistor Q1. It has a stabilizing capacitor Cint connected between the drain terminal of Q1 and the ground terminal. The PMOS transistor Q1 is larger in size than other transistors so that it can drive a large amount of load, and is also called a giant MOS.

The comparison circuit 2 compares the reference voltage between the resistors R1 and R2 with the reference voltage, and outputs a voltage corresponding to the potential difference between the two voltages to PM.
Supply to the gate terminal of the OS transistor Q1.

FIG. 12 is an operation timing chart of the internal power supply voltage down circuit of FIG. In the steady state, the stabilizing capacitive element Cin
Although Vint is held by t, the internal voltage Vin is
t gradually decreases, and accordingly, the internal reference voltage Vmon of the internal voltage generation circuit 1 also decreases (time 0 to t2). At time t2, the output of the comparison circuit 2 is inverted and the PMOS transistor Q1 is turned on. As a result, the internal voltage Vint starts to rise, and the internal reference voltage Vmon also rises accordingly (time t2 to t4).

After time t4, as before time t1,
The charging / discharging of the consumed current is repeated, and the internal voltage Vint gradually decreases.

As the speed of the memory increases, charging and discharging at a higher frequency are repeated, and it becomes more difficult to maintain a constant internal power supply Vint. Therefore, a plurality of internal power supply voltage down circuits are usually provided in the chip.

FIG. 11 is a circuit diagram showing a conventional example of a comparison circuit 2 provided inside each of a plurality of internal power supply voltage down circuits. As shown, the conventional comparison circuit 2 includes a current mirror circuit 3 including two transistors Q2 and Q3,
The differential amplifier 4 is connected to the current mirror circuit 3 and outputs a voltage according to the potential difference between the internal reference voltage Vmon of the internal voltage generation circuit 1 and the reference voltage Vref. Differential amplifier 4
Are a transistor Q4 whose gate terminal is supplied with an internal reference voltage Vmon, a transistor Q5 whose gate terminal is supplied with a reference voltage Vref, and a bias voltage V
s is supplied to the transistor Q6.

[0010]

Conventionally, the memory main body has a maximum current change due to current consumption when switching from a standby state to an operation state, and at the time when this current change becomes maximum, a plurality of internal power supply voltage step-down circuits are almost connected. Since the operating state was switched to the same timing, the internal voltage Vint temporarily drops, and thereafter, the internal voltage Vint oscillates for a while, and at this time, the temporary drop of Vint is too large to be stable. was there.

FIG. 10 is a voltage waveform diagram showing such a voltage fluctuation of the internal voltage Vint. When the memory body changes from the standby state to the operation state at time t11, the internal voltage Vint, the output voltage Vout of the comparison circuit 2, the PMOS
It can be seen that both the consumption current Iint flowing through the transistor Q1 greatly changes.

Since all the plurality of internal power supply voltage down circuits have the same gate width ratio between the transistors in the comparison circuit 2, the tendency of the voltage fluctuation of the internal voltage Vint is almost the same, and the internal power supply voltage down circuit is Even if the number is increased, the amount of decrease in the potential of the internal power supply Vint cannot be suppressed to a certain level or less.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor integrated circuit capable of suppressing the voltage fluctuation of the step-down voltage.

[0014]

In order to solve the above-mentioned problems, the present invention provides a semiconductor integrated circuit equipped with a circuit that operates at a step-down voltage having a lower potential than the power supply voltage. A voltage generation circuit for generating
A comparison circuit that controls the operation of the voltage generation circuit so that the internal reference voltage of the voltage generation circuit matches a predetermined reference voltage, and the comparison circuit has first and commonly connected gate terminals. A current mirror circuit having a second transistor and connected to the current mirror circuit,
A differential amplifier that outputs a voltage according to a difference voltage between the internal reference voltage of the voltage generation circuit and the reference voltage; and a gate capacitance setting circuit that sets the gate capacitances of the first and second transistors. .

Further, a first voltage step-down circuit which operates in the first operation mode and the second operation mode to generate a step-down voltage having a lower potential than the power supply voltage, and an operation in the second operation mode. A plurality of second voltage step-down circuits that individually generate the step-down voltage, and each of the plurality of second voltage step-down circuits generates a step-down voltage from the power supply voltage. Circuit, so that the internal reference voltage of the voltage generation circuit matches a predetermined reference voltage,
A comparison circuit for controlling the operation of the voltage generation circuit, wherein the comparison circuit has a first gate terminal connected in common.
A current mirror circuit including a second transistor, a differential amplifier connected to the current mirror circuit, and outputting a voltage according to a difference voltage between an internal reference voltage of the voltage generation circuit and the reference voltage, And a gate capacitance setting circuit for setting the gate capacitances of the first and second transistors, wherein the gate capacitance setting circuit has gate capacitances of the first and second transistors in the corresponding current mirror circuit, respectively. The gate capacitance is set to be different from the gate capacitance of the first and second transistors in the other current mirror circuit.

[0016]

DETAILED DESCRIPTION OF THE INVENTION A semiconductor integrated circuit according to the present invention will be specifically described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit of FIG. 1 is built in, for example, an SRAM.
Internal voltage V lower than the power supply voltage Vcc by operating when AM is in the standby state and the operation state
an internal power supply voltage down circuit 10 that generates int1 and a plurality of internal power supply voltage down circuits 11a that operate only when the SRAM is in an operating state to generate an internal voltage Vint1 (VINT in the conventional example).
11b, 11c, 11d and the internal power supply voltage down circuit 1
A step-down circuit control circuit 12 that switches whether or not to operate 1a to 11d and a reference potential generation circuit 13 that supplies a reference voltage to the internal power supply step-down circuits 11a to 11d are provided.

The internal power supply voltage down circuits 11a to 11d are provided around the memory cell block 14, for example, as shown in FIG. 2, and supply the internal voltage Vint1 to the different memory cell blocks 14, respectively. Since the internal power supply voltage down circuit 10 mainly operates in the standby state (also operates in the operation state), it is formed in a smaller size than the internal power supply voltage down circuits 11a to 11d.

FIG. 3 is a circuit diagram showing the detailed structure of the internal power supply voltage down circuits 11a to 11d. As shown in the figure, the internal power supply voltage down circuits 11a to 11d have an internal voltage generation circuit 1 that generates an internal voltage Vint1 from a power supply voltage Vcc supplied from the outside, and an internal reference voltage Vmon1 of the internal voltage generation circuit 1 that is a predetermined reference. The comparison circuit 2 controls the operation of the internal voltage generation circuit 1 so as to match the voltage. Internal power supply voltage down circuits 11a to 11d in FIG. 3 are common to FIG. 9 except that the internal configuration of comparison circuit 2 is different.

FIG. 4 is a circuit diagram of an embodiment of the comparison circuit 2. The comparison circuit 2 of FIG. 4 has a current mirror circuit 3 and a differential amplifier 4 which are configured in the same manner as the comparison circuit 2 of FIG.
And the transistors Q2 and Q in the current mirror circuit 3.
Transistor Q connected to the gate terminals of 3 respectively
7 and Q8.

These newly added transistors Q
7 and Q8 are transistors Q in the current mirror circuit 3.
This is for setting the gate capacitances of 2 and Q3. Transistors Q2 and Q3 in each comparison circuit 2 included in each of the four internal power supply voltage down circuits 11a to 11d shown in FIG.
Has a proportional gate capacitance (for example, the internal power supply step-down circuit 11
When the gate capacitances of the transistors Q2 and Q3 corresponding to a to 11d are set to "1", the gate capacitances of the transistors Q2 and Q3 corresponding to the content power supply step-down circuit become "2", "3", and "4" respectively. It is set.

As a method of proportionally setting the gate capacitances of the transistors Q2 and Q3, for example, the gate width of the transistors in each comparison circuit 2 may be adjusted.

The larger the gate capacitance of the transistors Q2 and Q3 in the comparison circuit 2, the later the timing at which the gate voltage changes. Therefore, when switching from the standby state to the operation state, the transistor Q2
The gate voltage of Q3 changes gently, and the timing at which the output voltage Vout1 of the comparison circuit 2 decreases is also delayed.

FIG. 5 shows internal power supply voltage down circuits 11a to 1 of FIG.
It is a voltage waveform diagram of 1d. In the steady state, the internal voltage Vin
t1 and the output Vout1 of the comparison circuit 2 gradually decrease (time t20
~ T22), at time t22, the internal voltage Vint1 and the internal reference voltage Vmon1 start to rise. However, the transistor Q2 that constitutes the current mirror circuit 3 in the comparison circuit 2
When the gate capacitance of Q3 is large, the output Vou of the comparison circuit 2
The potential of t1 does not drop immediately and continues to drop even after time t22, which makes it difficult to contribute to the charging of the internal power supply Vint1. After that, it rises at time t24, and after time t25, Vint1 is also stabilized by the charging and discharging of the consumption current of the memory body.
It gradually decreases from the stable state due to nt.

As described above, by adjusting the gate capacitances of the transistors Q2 and Q3 in the current mirror circuit 3, the output change timing of the internal voltage Vint1 at the time of switching from the standby state to the operation state can be variably adjusted.

In this embodiment, by proportionally changing the gate capacitances of the transistors forming the current mirror circuit 3 in the internal power supply voltage down circuits 11a to 11d of FIG.
The timing at which the output Vout1 of each comparison circuit 2 changes is shifted. As a result, the internal power supply voltage step-down circuits 11a to 11d start charging the stabilizing capacitance element Cint one by one in response to the maximum current change when the SRAM changes from the standby state to the operation state. Therefore, a plurality of internal power supply voltage step-down circuits 11a to 1 as in the prior art.
1d simultaneously charges the stabilizing capacitance element Cint with almost the same operation, and as a result, the problem that the internal voltage Vint drops sharply does not occur.

FIG. 6 shows the internal voltage Vin of this embodiment before and after switching from the standby state to the operation state.
It is a figure which shows the voltage change of t1 and the conventional internal voltage Vint. As shown in the figure, it can be seen that the voltage drop of the internal voltage Vint1 is smaller than that in the conventional case.

FIG. 7 shows the internal voltage V of the internal power supply voltage step-down circuits 11a to 11d having transistors having the smallest gate capacitance.
It is a figure which shows the voltage change of the internal voltage Vint1 of the internal power supply voltage | voltage fall circuits 11a-11d which have a transistor with the largest int1 and gate capacity. As shown in the figure, the larger the gate capacitance, the smaller the voltage drop of Vout1 immediately after switching from the standby state to the operation state, and thus Vin
It can be seen that the voltage drop at t1 is also small.

As described above, in this embodiment, the gate capacitances of the transistors Q2 and Q3 forming the current mirror circuit 3 in the internal power supply voltage down circuits 11a to 11d are made different for each of the internal power supply voltage down circuits 11a to 11d. Therefore, when switching from the standby state to the operation state, the internal power supply voltage step-down circuits 11a to 11d sequentially start the operation of charging the stabilizing capacitive element Cint.
Therefore, the plurality of internal power supply voltage down circuits 11a to 11d do not perform the charging operation at the same time, the voltage drop amount of the internal voltage Vint1 can be reduced, and the voltage oscillation amount can be reduced to shorten the time until the internal voltage Vint1 stabilizes. . Therefore, the operation of the circuit inside the chip using the internal voltage Vint1 can be stabilized.

In the embodiment described above, the transistor Q
An example in which the gate capacitances of the transistors Q2 and Q3 in the current mirror circuit 3 are increased by adding 7 and Q8 has been described.
As shown in FIG. 8, the gate capacitance may be increased by adding a capacitor element C1 between the gate terminals of the transistors Q2 and Q3 and the ground terminal. In this case, the capacitance value of the capacitor element may be changed for each of the internal power supply voltage down circuits 11a to 11d.

In the above-described embodiments, an example in which the present invention is applied to SRAM has been described. However, the present invention is applicable to various semiconductor integrated circuits including a semiconductor memory other than SRAM and a circuit for stepping down power supply voltage Vcc. It can be applied to circuits.

[0032]

As described in detail above, according to the present invention, the first current mirror circuit in the comparison circuit is constructed.
Since the circuit for setting the gate capacitance of the second transistor is provided, the timing at which the output of the comparison circuit changes can be shifted, and the reduction amount of the step-down voltage at the time of mode switching can be suppressed.

Further, for each of the plurality of second voltage step-down circuits, the gate capacitances of the first and second transistors forming the current mirror circuit in the comparison circuit in each voltage step-down circuit are made different from each other. There is no possibility that the voltage step-down circuit of 2 will switch modes at the same time.
It is possible to suppress the reduction amount of the step-down voltage when the mode is switched.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a schematic layout diagram of a semiconductor chip.

FIG. 3 is a circuit diagram showing a detailed configuration of internal power supply voltage down circuits 11a to 11d.

FIG. 4 is a circuit diagram of an embodiment of a comparison circuit 2.

5 is a voltage waveform diagram of internal power supply voltage down circuits 11a to 11d in FIG.

FIG. 6 is a diagram showing a voltage change between an internal voltage Vint1 of the present embodiment and a conventional internal voltage Vint before and after switching from a standby state to an operation state.

FIG. 7 shows the internal voltage Vint of the internal power supply voltage down circuits 11a to 11d of the conventional example having no extra gate capacitance and the internal power supply voltage down circuits 11a to 11d having transistors having minimum and maximum gate capacitances. The figure which shows the voltage change of voltage Vint1.

FIG. 8 shows a transistor Q2 with the addition of a capacitor element.
The figure which shows the example which sets the gate capacity of Q3.

FIG. 9 is a circuit diagram showing a schematic configuration of a conventional internal power supply voltage down circuit.

10 is an operation timing chart of the internal power supply voltage down circuit of FIG.

FIG. 11 is a circuit diagram showing a conventional example of a comparison circuit 2 provided inside each of a plurality of internal power supply voltage down circuits.

FIG. 12 is a voltage waveform diagram showing a voltage fluctuation of an internal voltage Vint.

[Explanation of symbols]

1 Internal voltage generation circuit 2 Comparison circuit 3 Current mirror circuit 4 differential amplifier 10, 11a to 11d Internal power supply voltage down circuit 12 Step-down circuit control circuit 13 Reference potential generation circuit 14 memory cell blocks

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Masami Masuda             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside F-term (reference) 5B015 JJ15 KB64 KB65 KB73 QQ03                       QQ11                 5H430 BB01 BB05 BB09 BB11 EE04                       FF02 FF13 GG08 HH03 KK04                 5J066 AA01 AA12 AA58 CA11 FA19                       HA09 HA17 HA25 HA29 KA00                       KA06 KA09 KA11 KA17 MA22                       ND01 ND14 ND22 ND23 PD01                       TA01 TA06                 5J500 AA01 AA12 AA58 AC11 AF19                       AH09 AH17 AH25 AH29 AK00                       AK06 AK09 AK11 AK17 AM22                       AT01 AT06 DN01 DN14 DN22                       DN23 DP01                 5M024 AA91 BB29 BB40 FF03 HH09                       HH11 PP01 PP02 PP03 PP07

Claims (5)

[Claims] 1. A semiconductor integrated circuit including a circuit that operates at a step-down voltage having a potential lower than a power supply voltage, wherein a voltage generation circuit that generates the step-down voltage from the power supply voltage and an internal reference voltage of the voltage generation circuit A comparison circuit for controlling the operation of the voltage generation circuit so as to match a predetermined reference voltage, wherein the comparison circuit has a first and a second transistor whose gate terminals are commonly connected. A differential amplifier that is connected to the current mirror circuit and outputs a voltage according to the potential difference between the internal reference voltage of the voltage generation circuit and the reference voltage; and sets the gate capacitance of the first and second transistors. And a gate capacitance setting circuit for performing the same. 2. A first voltage step-down circuit which operates in a first operation mode and a second operation mode to generate a step-down voltage having a lower potential than a power supply voltage, and an operation in a second operation mode. And a plurality of second voltage step-down circuits that individually generate the step-down voltage, wherein each of the plurality of second voltage step-down circuits generates a step-down voltage from the power supply voltage. A comparison circuit that controls the operation of the voltage generation circuit so that the internal reference voltage of the voltage generation circuit matches a predetermined reference voltage, and the comparison circuit has a gate terminal commonly connected. A current mirror circuit including first and second transistors, and a differential amplifier that is connected to the current mirror circuit and outputs a voltage according to a potential difference between the internal reference voltage of the voltage generation circuit and the reference voltage. And a gate capacitance setting circuit that sets the gate capacitances of the first and second transistors, wherein the gate capacitance setting circuit respectively includes the first and second gate capacitance setting circuits in the corresponding current mirror circuit. A semiconductor integrated circuit, wherein a gate capacitance of a transistor is set so that the gate capacitance of the transistor is different from that of the first and second transistors in the other current mirror circuit. 3. The gate capacitance setting circuit is provided corresponding to each of the first and second transistors in the current mirror circuit, and each gate terminal is a gate terminal of each of the first and second transistors. The semiconductor integrated circuit according to claim 1, further comprising a third transistor and a fourth transistor which are commonly connected. 4. The gate capacitance setting circuit is provided corresponding to each of the first and second transistors in the current mirror circuit, and each gate terminal is a gate terminal of each of the first and second transistors. And third and fourth transistors commonly connected to the one of the third and fourth transistors in the one current mirror circuit.
The ratio of the gate width to the gate length of the other transistor is different from the ratio of the gate width to the gate length of the third and fourth transistors in the other current mirror circuit. Semiconductor integrated circuit. 5. Each of the gate capacitance setting circuits has a capacitor element having one end connected to both gate terminals of the first and second transistors in the current mirror circuit and the other end grounded. 3. The semiconductor integrated circuit according to claim 2, wherein the capacitance value of the capacitor element in the current mirror circuit is different from the capacitance value of the capacitor element in the other current mirror circuit.