KR100550873B1 - A crystal oscillator - Google Patents

Abstract

The present invention relates to a crystal oscillator, wherein in a crystal oscillator having a crystal piece and an IC chip, the crystal piece is embedded in an inner space of the upper ceramic laminate in which a plurality of ceramic layers are stacked, and an upper portion of the upper ceramic laminate is formed. A crystal assembly to seal as a cover; A chip assembly having the IC chip embedded in an inner space of a lower ceramic laminate in which a plurality of ceramic layers are stacked, and sealing an upper portion of the lower ceramic laminate as the upper ceramic laminate; and cutting at each corner of the cover. And a plurality of contact terminals for input / output formed at each corner of the upper ceramic laminate to be exposed to the outside through the cutout.

According to the present invention, the data input and output by contacting the probe and the contact terminal by distributing the input and output contact terminals used to input and output data to the IC chip of the chip assembly in the corner of the cover covering the upper part of the assembly It is possible to achieve more smoothly, and the effect of enabling a compact design of the product without fear of a short accident is obtained.

Crystal Oscillator, Crystal Piece, IC Chip, Ceramic Laminate, I / O Contact Terminal, Probe

Description

Crystal Oscillator {A CRYSTAL OSCILLATOR}             

1 is a perspective view of a general crystal oscillator.

2 is a perspective view of a crystal oscillator according to the present invention.

3 is a perspective view of a crystal oscillator according to the present invention.

Figure 4 is a crystal assembly employed in the crystal oscillator according to the present invention

a) is a plan view,

b) is a front view,

c) is the rear view.

Figure 5 (a) is a chip assembly employed in the crystal oscillator according to the present invention

a) is a plan view when the IC chip is mounted by wire bonding method,

b) is a plan view when the IC chip is mounted by flip bonding.

6 is a use state diagram of reading / writing operation using a data input / output device in a crystal oscillator according to the present invention.

      Explanation of symbols on the main parts of the drawings

10: crystal assembly 11, 12: first and second ceramic layer

13: upper ceramic laminated body 18a, 18b, 18c, 18d: terminal pad

20: chip assembly 21, 22, 23: first and second ceramic layer

24: lower ceramic laminate 27: wire

28a, 28b, 28c, 28d: upper electrode 30: conductive line

31,32,33,34: Contact terminal 35a, 35b, 35c, 35d: Conductive top via hole

36a, 36b, 36c, 36d: connection pattern 37a, 37b, 37c, 37d: conductive lower via hole

 B ....... Edition I ....... IC Chip

The present invention relates to a crystal oscillator, and more particularly, the input and output contact terminals used to input and output data to the IC chip of the chip assembly are distributed to the edge of the cover covering the top of the assembly of the probe and the contact terminal The present invention relates to a crystal oscillator that performs data input and output by contact more smoothly and enables a compact design of a product without fear of a short accident.

In general, a crystal oscillator employing crystal as a piezoelectric vibrator (piezoelectric component) changes the resistance value of the thermistor according to the temperature, so that the voltage applied to the varicap diode changes, and the capacitance of the capacitor changes due to the change of the voltage. It is a device that generates frequency according to the change of temperature.

This crystal oscillator is small and stable frequency can be obtained against external environment change, so it is used for character composition and color composition circuit in computer, communication equipment, etc. Oscillators (TCXOs), thermostatically controlled crystal oscillators (OCXOs), etc. are often used as core components for all signals in space satellites and instruments.

Recently, the development of information communication and digital technology is used in the high frequency domain, and the demand for fast data processing speed and new materials, components, modules, and boards is increasing, especially in the case of mobile communication components, miniaturization and multiplexing. In accordance with the trend of banding and high frequency, miniaturization, high integration and high frequency of crystal oscillator are required.

The crystal oscillator has a mainstream of 0.024CC (5.0mm (L) * 3.2mm (W) * thickness1.5mm (T)), but as the miniaturization of parts is accelerated, its length, width and thickness become short and narrow. Thinner 0.008CC (3.2mm (L) * 2.5mm (W) * 1.0mm (T)) and 0.004CC (2.5mm (L) * 2.0mm (W) * 0.8mm (T)) will dominate . For this purpose, miniaturization of crystal oscillator parts, innovation of manufacturing method, and light and small size should be realized.

1 is an exploded perspective view of a typical crystal oscillator, the conventional crystal oscillator 100, as shown in Figure 1, the crystal assembly 110 and the oscillation circuit, including the crystal (B) for causing the oscillation, temperature compensation The chip assembly 120 including an IC chip I including an integrated circuit, a circuit portion such as a voltage regulating circuit, and a memory portion such as EEPROM or RAM is formed in a dual structure in which the top and bottom are integrated.

That is, the crystal piece assembly 110 has a second ceramic layer 112 stacked along an edge of the first ceramic layer 111 and the first ceramic layer 111 on which a circuit pattern (not shown) is formed. It consists of a multi-layer ceramic substrate 113, a crystal piece (B) disposed therein and a cover 114 for sealing a space in which the crystal piece (B) is disposed, of the crystal piece (B) On the surface, a predetermined pattern electrode is formed.

The crystal piece (B) is one end is raised horizontally by a die bonding method through a metal bump (not shown) so that power is supplied from the outside to one side of the upper surface of the first ceramic layer 111, the other end is free It is provided with a stage.

In addition, the chip assembly 120 includes a ceramic substrate including a first ceramic layer 121 having a circuit pattern (not shown) formed on an upper surface thereof, and second and third ceramic layers 122 and 123 stacked along an edge thereof. 124 and an IC chip I bonded and fixed on the first ceramic layer 121.

In addition, the left and right sides of the ceramic substrate 124 are electrically connected to the internal circuit parts of the IC chip I to be input and adjusted by inputting data into the memory, and outputting the adjusted data to the outside. A plurality of dragon contact terminals 128a to 128d are formed.

The IC chip (I) in which various circuit parts and memory parts are integrated is a step which protrudes in a step shape when stacked vertically while being fixed to the upper surface of the first ceramic layer 121, which is the bottom surface of the ceramic substrate 124. Wire bonding as a wire 126 between a plurality of bonding pads 125 mounted on the protrusion 122a of the ceramic layer 122 and a plurality of pads 126a mounted on the upper surface of the IC chip I. While electrically connecting them to each other, the internal space in which the IC chip (I) is disposed is filled with the epoxy and molded.

The assembled crystal assembly 110 and the chip assembly 120 as described above are the chip assembly 120 as a lower part, and the chip assembly 110 as an upper part in another assembly line. The solder pad 127 formed on the upper surface of the ceramic substrate 124 of 120 and the pads formed on the lower surface of the ceramic substrate 113 of the quartz crystal assembly 110 are integrally bonded to each other via solder balls. As a result, the crystal oscillator 100 having a dual structure consisting of the crystal assembly 110 having the crystal piece B and the chip assembly 120 having the IC chip I was assembled.

On the other hand, the crystal oscillator 100 having such a structure is designed to be miniaturized as the miniaturization of the components to be mounted on the product and the complex modularization between the adjacent parts proceeds to reduce the volume, the ceramic constituting the chip assembly 120 The length, width, and thickness of the substrate 124 are shortened, narrowed, and thinned, and at the same time, a pair of input and output contact terminals 128a, 128b, and 128c are provided on the left and right outer walls of the chip assembly 120, respectively. An interval D between the 128 d may also be reduced according to the reduction ratio of the crystal oscillator 100.

However, in accordance with the miniaturization of the crystal oscillator 100, the process of reducing the size of the input / output contact terminals 128a, 128b, 128c, and 128d in which the chip assembly 120 is formed in a via hole shape on the outer wall in a semicircular section. There is a phase limit.

In addition, the data input / output 200 having a pair of probes 201 and 202 is disposed on the left and right sides of the crystal oscillator 100, and the input and output contact terminals 128a and 128b of the chip assembly 120 are disposed. Since the space D between the input / output terminals 128a and 128b adjacent to each other and the other input / output terminals 128c and 128d is narrow when inputting / outputting data through (128c) and 128d, The risk of occurrence of a short accident between the terminals and between the probes 201 and 202 becomes very high.

In addition, the interval D1 between the probes 201 and 202 used for inputting and outputting data by contacting the tip portions with the input / output terminals 128a, 128b, 128c, and 128d is also reduced in accordance with the reduced interval between the terminals. In order to reduce the distance D1 between the probes 1201 and 202 in accordance with the miniaturization design of the crystal oscillator 100 which is miniaturized due to the rapid trend, the structure of the data input / output 200 is changed or remanufactured. It is difficult to do so, and excessive cost is required when restructuring and remanufacturing.

Accordingly, the present invention has been proposed to solve the conventional problems as described above, the object of which is to more smoothly perform the input and output using the data input and output without fear of short-circuit, and can overcome the limitations of the compact design To provide a crystal oscillator.

As a technical configuration for achieving the above object, the present invention,

In a crystal oscillator having a crystal piece and an IC chip,

A crystal piece assembly in which the crystal piece is embedded in an inner space of an upper ceramic laminate in which a plurality of ceramic layers are stacked, and seals an upper portion of the upper ceramic laminate as a cover;

A chip assembly having the IC chip embedded in an inner space of a lower ceramic laminate in which a plurality of ceramic layers are stacked, and sealing an upper portion of the lower ceramic laminate as the upper ceramic laminate; and

And a plurality of input / output contact terminals formed at each corner of the upper ceramic laminate to be exposed to the outside through cutouts cut at each corner of the cover.

Preferably, the input / output contact terminals are electrically connected to the IC chips through conductive lines formed in the upper ceramic laminate.

More preferably, the conductive line includes a conductive upper via hole formed in the upper ceramic laminate so that the upper and lower ends of the input and output contact terminals are connected, and one end of the conductive via hole is connected to the ceramic layer of the upper ceramic laminate. A connection pattern printed along a predetermined length, a conductive lower via hole formed in the upper ceramic laminate so that the other end and the upper end of the connection pattern are electrically connected to each other, and a lower end of the conductive lower via hole. And an upper electrode for the contact terminal formed on the lower surface and a lower electrode for the contact terminal formed on the upper surface of the lower ceramic laminate corresponding to the upper electrode and electrically connected to the IC chip.

More preferably, the connection pattern is printed in different lengths on the upper surface of the ceramic layer constituting the upper ceramic laminate.

More preferably, the connection pattern is printed on the upper surface of the ceramic layer constituting the upper ceramic laminate with the same length.

More preferably, the upper and lower electrodes are formed on each side of the upper and lower ceramic laminates that do not overlap with external terminals formed at the top edges of the lower ceramic laminates.

Hereinafter, the present invention will be described in more detail.

2 is a perspective view of a crystal oscillator according to the present invention, in which a crystal oscillator 1 of the present invention inputs data into a storage portion of an IC chip I assembled with a crystal piece B, A plurality of input / output terminals used for outputting the adjusted data from the storage unit to the outside are formed at each corner of the crystal assembly 10. The crystal oscillator 1 includes a crystal assembly 10 and a chip assembly 20. ), And contact terminals 31 to 34 for input / output, which should be understood as being selectively applicable to a voltage controlled crystal oscillator (VCXO), a temperature compensated crystal oscillator (TCXO), a constant temperature controlled crystal oscillator (OCXO), and the like.

That is, the crystal piece assembly 10 has an upper ceramic laminated body 13 having a concave inner space of a predetermined size so that the rectangular crystal piece B is mounted in the inner space and a cover for covering the upper part to seal the inner space ( 14).

The upper ceramic laminated body 13 includes a first ceramic layer 11 having a circuit pattern printed on the upper surface thereof, and a second ceramic layer having a rectangular frame shape that forms at least one vertically stacked concave inner space along an outer edge thereof. (12), the cover (14) of the first ceramic layer 11 of the uppermost layer constituting the upper ceramic laminated body (13) to completely block the internal space in which the crystal piece (B) is accommodated It is joined to the top surface by soldering method.

In addition, each of the corners of the cover 14 cuts 14a, 14b, and 14c to expose the input / output contact terminals 31 to 34 formed at the corners of the upper ceramic layer 13 to the outside. ) 14d is formed by cutting away.

In addition, the chip assembly 20 is composed of a lower ceramic laminated body 24 having a concave inner space of a predetermined size so that the IC chip I having various circuit parts and memory parts integrated thereon, the lower ceramic stacked body ( 24 is a first ceramic layer 21 printed with a circuit pattern on the upper surface and at least one or more second ceramic layers 22, 23 of a rectangular frame shape which are stacked up and down along the outer edge thereof to form a concave inner space. It consists of.

Here, the IC chip I may be mounted in a wire bonding method or a flip chip bonding method in an inner space of the lower ceramic laminate 24.

Accordingly, when the IC chip I is mounted on the lower ceramic laminate 24 by wire bonding, a protrusion 22a is formed in the second ceramic layer 22 to extend into an inner space. A plurality of bonding pads 25 are formed at 22a, and a plurality of terminal pads 26 are formed on the upper surface of the corresponding IC chip I, so that the bonding pads 25 and the terminal pads 26 are formed. Wire-bonded as wires 27 so as to be electrically connected to each other.

In addition, when the IC chip I is mounted on the lower ceramic laminate 24 by a flip chip bonding method, a metal bump (not shown) formed on the upper surface of the first ceramic layer 21, which is the lowest layer, is mediated. Bonding the lower surface of the IC chip (I).

The upper and lower edges of the lower ceramic laminate 24 have voltage control terminals Vcon, a grounding terminal G, and an output terminal Out as shown in FIGS. ) And a plurality of external terminals 29a, 29b, 29c, and 29d used as power supply terminals Vcc, which supply power to the IC chip I and output a compensated frequency. It is electrically connected to the bonding pad 25 which is connected via the IC chip (I) and the wire (27).

Here, the terminal pads are formed at the lower edges of the upper ceramic laminates 13 and the outer terminals 29a, 29b, 29c, and 29d formed on the upper edges of the lower ceramic laminates 24, respectively. 18a, 18b, 18c and 18d are formed so that they are connected via solder balls.

On the other hand, the input and output contact terminals 31, 32, 33, 34 to the outside through the cut-out portion (14a ~ 14d) cut in each corner of the cover 14 of the quartz crystal assembly 10 It is a terminal portion formed at each corner of the uppermost ceramic layer 12 constituting the upper ceramic laminate 13 so as to be exposed.

Here, the input / output terminals 31, 32, 33, 34 perform any one of a data input / output contact terminal (DIO) for inputting a desired input constant, a reading or writing to an IC chip. It is a chip select contact terminal (CS) indicating whether to do it, a utility contact terminal (UTIL) used for mode selection, and a clock signal contact terminal (SCLK) for inputting a clock frequency.

As shown in FIGS. 3 and 4, the input and output contact terminals 31, 32, 33, and 34 are connected to the IC chip via conductive lines 30 formed on the upper ceramic laminate 13. Each of the conductive lines 30 may be electrically connected to (I), and the conductive lines 30 may include via holes, patterns, and electrodes formed in the ceramic layers 11 and 12 constituting the upper ceramic laminate 13.

That is, the conductive line 30 is connected to the input terminal 31, 32, 33, 34 for the input and output contact terminals 31, 32, 33, 34 formed at each corner of the upper surface of the upper ceramic laminate 13 so that the upper ends thereof are electrically connected. Conductive upper via holes 35a, 35b, 36b and 36c are formed in the corners of the ceramic layer 12 constituting the upper ceramic laminate 13, respectively.

The lower ends of the conductive upper via holes 35a, 35b, 36b, and 36c may be printed along a side of the upper surface of another ceramic layer 11 constituting the upper ceramic laminate 13. Electrically connected to one end of the connection patterns 36a, 36b, 36b, 36d.

The other end of each of the connection patterns 36a, 36b, 36b, and 36d is formed of the conductive lower via holes 37a, 37b, 37c, and 37d formed through the ceramic layer 12 on which the connection pattern is printed. The lower via holes 37a, 37b, 37c, and 37d are electrically connected in contact with the upper end, and the upper electrodes 38a and 38b for contact terminals formed on the lower surface of the upper ceramic laminate 13, respectively. Electrically connected with (38c) (38d).

The upper electrodes 38a, 38b, 38c, and 38d are formed on the lower ceramic layers 23 of the chip assembly 20 so as to be electrically connected to the IC chip I. (C) 28c (28d) and one-to-one correspondence with each other, and is bonded through the solder ball during the vertical assembly of the crystal assembly 10 and the chip assembly 20.

Here, the connection patterns 36a, 36b, 36b, and 36d printed on the upper surface of the ceramic layer constituting the upper ceramic laminate 13 are upper electrodes formed on the lower surface of the crystal assembly 10. Depending on the formation positions of (38a) 38b (38c) 38d, they may be printed in different lengths, or may be printed in the same length.

In addition, the upper and lower electrodes 38a, 38b, 38c, 38d, 28a, 28b, 28c, and 28d are external terminals formed at upper edges of the lower ceramic laminate 24. The upper and lower surfaces of the upper and lower ceramic laminates 13 and 24 are preferably formed at edges of the upper and lower ceramic laminates 13 and 24 so as not to overlap with the upper and lower surfaces of the upper and lower surfaces 29a, 29b, 29c and 29d.

In addition, the terminal pads 18a, 18b, 18c, and 18d formed at the corners of the lowermost ceramic layer 11 of the crystal assembly 10 may have the uppermost ceramic layer 23 of the chip assembly 20. The external terminals 29a, 29b, 29c, and 29d formed at the corners of each other face to face one-to-one correspondence with each other, and mediate solder balls during the vertical assembly of the crystal piece assembly 10 and the chip assembly 20. Is bonded.

The crystal oscillator 1 having the above-described configuration is a state in which the crystal assembly 10 is placed on the upper surface of the crystal chip assembly 20 in the state in which the IC chip I mounted on the lower ceramic laminate 24 is exposed upward. The upper and lower layers of the ceramic laminate 14 as the upper part, and the stacked crystal assembly 10 and the chip assembly 20 are disposed on the first ceramic layer 11 which is the lowermost layer of the crystal assembly 10. Arranged between the formed terminal pads 18a, 18b, 18c, and 18d and the external terminals 29a, 29b, 29c, and 29d formed on the uppermost second ceramic layer 23 of the chip assembly 20, respectively. It is joined together by solder balls.

At the same time, the upper electrodes 38a, 38b, 38c, 38d formed on the lower surface of the crystal assembly 10 and the lower electrodes 28a, 28b formed on the upper surface of the chip assembly 20 ( 28c) and 28d are also integrally joined via the solder balls arranged thereon.

In this case, the input and output terminals 31, 32, 33, 34 formed on the upper surface of each corner portion of the crystal piece assembly 10 are connected to the conductive via holes 35a, 35b, 35c, 35d, and the like. Conductive line 30 consisting of patterns 36a, 36b, 36c, 36d, conductive lower via holes 37a, 37b, 37c, 37d, and upper electrodes 38a, 38b, 38c, 38d. The lower electrode 28a, 28b, 28c, and 28d electrically connected to the IC chip I of the chip assembly 20 has a circuit configuration.

Therefore, the operation of inputting and adjusting data in the storage unit of the IC chip I and outputting the adjusted data externally are shown in FIG. 6 in a state where voltage is applied through an external terminal for voltage control and an external terminal for power supply. Similarly, four probes 41, 42, 43 are disposed on the top of the quartz assembly 10 and extend directly below the lower surface of the data I / O 40. 44 is an input / output contact terminal 31, 32, 33 exposed to the outside through the cutouts 14a, 14b, 14c, and 14d formed on the cover 14 of the crystal assembly 10. Correlate with 34 one-to-one.

Subsequently, the data input / output 40 is lowered toward the crystal assembly assembly 10 so that the tip portions of the probes 41, 42, 43, 44 and corresponding input / output terminals 31, 32, 32 (34) are in contact with each other, to check the frequency output through the output external terminal, to find the desired output frequency of the plurality of input and output contact terminals 31, 32, 33, 34 of the desired Input into the IC chip (I) through a data input and output contact terminal (DIO) for inputting an input constant, the adjusted data is external to any one of the input and output terminals 31, 32, 33, 34 It is outputted to the operator and can be monitored.

According to the present invention having the above-described configuration, input and output contact terminals used for inputting data in accordance with the characteristics to the storage unit provided in the IC chip and outputting data to the outside, one for each corner portion of the crystal piece assembly With this arrangement, a compact design of the product can be achieved without fear of short-circuit due to the reduction of the distance between the contact terminals and the reduction of the distance between the probes, and the effect of safely and smoothly performing data input / output operations is obtained.

While the invention has been shown and described with respect to specific embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit or scope of the invention as set forth in the claims below. I would like to clarify that knowledge is easy to know.

Claims (6)

In a crystal oscillator having a crystal piece and an IC chip, A crystal piece assembly in which the crystal piece is embedded in an inner space of an upper ceramic laminate in which a plurality of ceramic layers are stacked, and seals an upper portion of the upper ceramic laminate as a cover; A chip assembly having the IC chip embedded in an inner space of a lower ceramic laminate in which a plurality of ceramic layers are stacked, and sealing an upper portion of the lower ceramic laminate as the upper ceramic laminate; and And a plurality of contact terminals for input / output formed at each corner of the upper ceramic laminate to be exposed to the outside through cutouts cut at each corner of the cover. The input / output contact terminals are electrically connected to the IC chip through conductive lines formed on the upper ceramic laminate, and the conductive lines are formed on the upper ceramic laminate so that the upper and lower ends of the input / output contact terminals are connected to each other. A conductive upper via hole, one end of which is connected to the conductive via hole, a connection pattern printed at a predetermined length along a side of the ceramic layer of the upper ceramic laminate, and the upper ceramic so that the other end and the upper end of the connection pattern are electrically connected to each other. A conductive lower via hole formed in the laminate, an upper electrode for a contact terminal formed on a lower surface of the upper ceramic laminate to be connected to a lower end of the conductive lower via hole, and an upper surface of the lower ceramic laminate corresponding to the upper electrode; And a lower electrode for contact terminal which is formed and electrically connected to the IC chip. Crystal oscillator. delete delete The method of claim 1, The crystal pattern oscillator, characterized in that printed on the upper surface of the ceramic layer constituting the upper ceramic laminated body with different lengths. The method of claim 1, The crystal pattern oscillator, characterized in that printed on the upper surface of the ceramic layer constituting the upper ceramic laminated body with the same length. The method of claim 1, The upper and lower electrodes are crystal oscillators, characterized in that formed on each side of the upper, lower ceramic laminates do not overlap with the external terminal formed on the edge of the upper surface of the lower ceramic laminate.

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