KR100533390B1 - Method For Forming The Metal Line Pattern Of Semiconductor Device - Google Patents
Method For Forming The Metal Line Pattern Of Semiconductor Device Download PDFInfo
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- KR100533390B1 KR100533390B1 KR10-1999-0032633A KR19990032633A KR100533390B1 KR 100533390 B1 KR100533390 B1 KR 100533390B1 KR 19990032633 A KR19990032633 A KR 19990032633A KR 100533390 B1 KR100533390 B1 KR 100533390B1
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- hard mask
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- metal wiring
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- 239000002184 metal Substances 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 10
- 239000003989 dielectric material Substances 0.000 claims abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 8
- 238000010030 laminating Methods 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 19
- 238000001312 dry etching Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 230000003667 anti-reflective effect Effects 0.000 claims 1
- 239000011368 organic material Substances 0.000 claims 1
- 230000007261 regionalization Effects 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 abstract description 5
- 229920000642 polymer Polymers 0.000 abstract description 5
- 235000012431 wafers Nutrition 0.000 abstract description 2
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 abstract 1
- 238000001465 metallisation Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910018182 Al—Cu Inorganic materials 0.000 description 1
- 229910017758 Cu-Si Inorganic materials 0.000 description 1
- 229910017931 Cu—Si Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은, 반도체소자의 금속배선패턴 형성방법에 관한 것으로서, 소자하부구조에 반사방지막, 금속층 및 확산방지막을 적층한 후, 유기계 저유전 물질로 된 제1하드마스크를 적층하고, 그 상부면에 규소산화막 혹은 질화막을 적층한 후, 패턴을 갖는 감광막을 적층하여 저유전물질인 제1하드마스크를 통하여 금속배선패턴을 식각으로 형성하므로 폴리머(Polymer) 부족으로 인하여 금속배선패턴의 내측벽면이 손상되는 것을 방지하여 소자의 전기적인 특성을 향상시키도록 하는 매우 유용하고 효과적인 발명이다. 또한, 종래의 공정에 비하여 매우 얇은 감광막을 사용하므로 마스크공정의 안정성을 증대시키며, 패턴의 해상도를 향상시켜 보다 미세한 패턴을 가공할 수 있도록 하여 소다 공정을 안정적으로 진행하면서도 소자의 크기를 축소하므로 웨이퍼당 발생되는 소자의 페일(Fail)을 감소시켜 소자의 수율을 증대하도록 하는 장점을 지닌다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring pattern of a semiconductor device, comprising: laminating an antireflection film, a metal layer, and a diffusion barrier film on a device lower structure, and then laminating a first hard mask made of an organic low dielectric material, After the silicon oxide layer or the nitride layer is laminated, the photosensitive layer having the pattern is laminated and the metal wiring pattern is etched through the first hard mask, which is a low dielectric material, so that the inner wall surface of the metal wiring pattern is damaged due to the lack of polymer. It is a very useful and effective invention which prevents the improvement to improve the electrical characteristics of the device. In addition, the use of a very thin photoresist film compared to the conventional process increases the stability of the mask process, improve the resolution of the pattern to process a finer pattern, so that the process of the soda process, while reducing the size of the device wafers It has the advantage of increasing the yield of the device by reducing the fail (fail) of the device generated sugar.
Description
본 발명은 하드마스크(Hard Mask)를 이용하여 금속배선패턴을 식각하는 방법에 관한 것으로서, 특히, 소자하부구조에 반사방지막, 금속층 및 확산방지막을 적층 한 후, 유기계 저유전 물질로 된 제1하드마스크를 적층하고, 그 상부면에 규소산화막 혹은 질화막을 적층한 후, 패턴을 갖는 감광막을 적층하여 식각을 통하여 금속배선패턴을 형성하므로 금속배선패턴의 손상을 방지하여 소자의 전기적인 특성을 향상시키도록 하는 반도체소자의 금속배선패턴 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of etching a metal wiring pattern using a hard mask, and in particular, after laminating an antireflection film, a metal layer, and a diffusion barrier film on a device substructure, a first hard material made of an organic low dielectric material. After the mask is laminated, and the silicon oxide film or nitride film is laminated on the upper surface, a photosensitive film having a pattern is laminated to form a metal wiring pattern through etching, thereby preventing damage to the metal wiring pattern to improve electrical characteristics of the device. The present invention relates to a method for forming a metal wiring pattern of a semiconductor device.
일반적으로, 반도체소자의 고집적화에 따라 회로의 선폭과 간격의 축소가 지속적으로 진행되고 있다. 특히, 금속배선패턴의 경우 금속층 두께는 일정한 데 반하여 선폭과 간격의 지속적인 축소로 인하여 종횡비(Aspect Ratio)가 증대되고 있는 실정이다. 또한, 금속배선패턴의 선폭 축소에 따라 패턴을 형성하는 마스크공정의 마아진(Margin)이 점차적으로 감소하고 있으며, 이를 보완하기 위하여 감광막의 적층 두께가 점차적으로 낮아지고 있어서 식각시 선택비가 큰 문제로 대두되고 있다.In general, reduction in line width and spacing of circuits is continuously progressed due to high integration of semiconductor devices. In particular, in the case of the metal wiring pattern, the thickness of the metal layer is constant, but the aspect ratio is increasing due to the continuous reduction of the line width and the gap. In addition, as the line width of the metallization pattern is reduced, the margin of the mask process for forming the pattern is gradually decreasing. In order to compensate for this, the stack thickness of the photoresist film is gradually lowered. It is becoming.
상기 금속층의 식각은 감광막을 적층하여 패턴을 형성한 후 건식식각(Dry Etch)으로 식각 하므로써 소정의 금속배선패턴을 형성하게 되는 것으로서, 이 금속배선패턴을 식각 할 때, 금속배선패턴의 측벽면이 손상받는 것을 방지하도록 폴리머(Polymer)를 금속배선패턴 내벽면에 도포하게 된다.The etching of the metal layer is to form a pattern by stacking a photoresist film and then etching by dry etching to form a predetermined metal wiring pattern. When etching the metal wiring pattern, the sidewall surface of the metal wiring pattern is To prevent damage, a polymer is applied to the inner wall of the metallization pattern.
도 1(a) 내지 도 1(c)는 종래의 금속배선패턴 형성방법을 순차적으로 보인 도면이다.1 (a) to 1 (c) are views sequentially showing a conventional metal wiring pattern forming method.
종래의 금속배선패턴 형성방법을 살펴 보면, 도 1(a)에 도시된 바와 같이, 소정의 구조를 갖는 소자하부구조(1)에 반사방지막(2), 금속층(3) 및 확산방지막(4)을 적층한 후, 그 위에 재차 규소 산화막 혹은 질화막으로 된 하드마스크(5)를 적층하도록 한다.Referring to the conventional method of forming the metallization pattern, as shown in FIG. 1A, the antireflection film 2, the metal layer 3, and the diffusion barrier 4 are formed on the device substructure 1 having a predetermined structure. After stacking, the hard mask 5 made of a silicon oxide film or a nitride film is again stacked thereon.
그리고, 상기 하드마스크(5) 상에 감광막(6)을 적층한 후, 패턴(Pattern)을 형성하도록 한다.After the photoresist film 6 is laminated on the hard mask 5, a pattern is formed.
도 1(b)에 도시된 바와같이, 상기 감광막(6)으로 하드마스크(5)를 식각하여 콘택부위를 형성하도록 한다.As shown in FIG. 1B, the hard mask 5 is etched with the photosensitive film 6 to form a contact portion.
그리고, 도 1(c)에 도시된 바와 같이, 계속하여 식각을 진행하여 확산방지막 (4), 금속층(3) 및 반사방지막(2)을 식각하여 콘택부위(7)를 형성하므로 금속배선패턴을 최종적으로 형성하게 된다.As shown in FIG. 1 (c), the etching process is continuously performed to etch the diffusion barrier film 4, the metal layer 3, and the antireflection film 2 to form the contact portion 7, thereby forming a metal wiring pattern. Finally formed.
그런데, 상기한 바와 같이, 상기 금속배선패턴의 측벽면을 보호하기 위하여 CF계열의 가스를 첨가하는 방법과, 감광막에서 발생되는 C를 이용하는 방법이 있는 데, 주로 감광막에서 발생되는 C를 이용하는 방법이 사용된다.However, as described above, there are methods of adding a CF-based gas and a method of using C generated in the photosensitive film to protect the sidewall surface of the metal wiring pattern, and a method using mainly C generated in the photosensitive film. Used.
상기 감광막을 사용하여 금속배선패턴의 측벽면에 폴리머를 형성하는 방법은, 감광막의 식각이 지나치게 느리면, 총분한 폴리머가 생성되지 못하여 금속배선패턴의 선폭이 감소하고 심할 경우에는 도 2에 도시된 바와 같이, 금속배선패턴이 부러지게 되어 전기적으로 쇼트(Short)를 유발하게 되어 소자의 전기적인 페일(Fail)을 유발하는 문제점을 지닌다.In the method of forming a polymer on the sidewall surface of the metallization pattern using the photoresist layer, if the etching of the photoresist layer is too slow, a thin polymer is not produced and the line width of the metallization pattern is reduced and is severe as shown in FIG. 2. Likewise, the metal wiring pattern is broken to cause a short circuit, thereby causing an electrical fail of the device.
또한, 상기와는 반대로 식각이 지나치게 빠르게 진행되는 경우, C의 방출과 폴리머의 형성이 촉진되어서 금속배선패턴의 선폭이 증가하게 되므로 금속배선패턴의 형성이 제대로 이루어지지 않아서 소자의 치명적인 페일을 유발하는 문제를 지닌다.In addition, in contrast to the above, when the etching proceeds too fast, the release of C and the formation of the polymer are promoted to increase the line width of the metallization pattern, thereby preventing the formation of the metallization pattern so as to cause a fatal failure of the device. I have a problem.
본 발명적은 이러한 점을 감안하여 안출한 것으로서, 소자하부구조에 반사방지막, 금속층 및 확산방지막을 적층한 후, 유기계 저유전 물질로 된 제1하드마스크를 적층하고, 그 상부면에 규소산화막 혹은 질화막을 적층한 후, 패턴을 갖는 감광막을 적층하여 식각을 통하여 금속배선패턴을 형성하므로 금속배선패턴의 손상을 방지하여 소자의 전기적인 특성을 향상시키는 것이 목적이다. The present invention has been made in view of this point, and after laminating an antireflection film, a metal layer and a diffusion preventing film on the lower structure of the device, a first hard mask made of an organic low dielectric material is laminated, and a silicon oxide film or a nitride film on the upper surface thereof. After the lamination, the photosensitive film having the pattern is laminated to form a metal wiring pattern through etching, thereby preventing damage to the metal wiring pattern to improve electrical characteristics of the device.
이러한 목적은 소자하부 구조 상에 반사방지막, 금속층 및 확산방지막을 순차적으로 적층하는 단계와; 상기 결과물 상에 저유전체물질인 하부하드마스크를 적층하는 단계와; 상기 하부하드마스크 상에 상부하드마스크를 적층한 후, 그 위에 감광막을 적층하여 패턴을 형성하는 단계와; 상기 단계 후에 상부하드마스크를 식각하여 제1콘택을 형성한 후, 잔류된 상부하드마스크를 제거하는 단계와; 상기 단계 후에 제1콘택을 통하여 하부하드마스크를 식각하여 제2콘택을 형성하는 단계와; 상기 단계 후에 제2콘택을 통하여 확산방지막, 금속층 및 반사방지막을 식각하여 제3콘택을 형성하는 단계를 포함하여 반도체소자의 금속배선패턴 형성방법을 제공함으로써 달성된다.This object is achieved by sequentially stacking an antireflection film, a metal layer, and a diffusion barrier film on a device lower structure; Stacking a lower hard mask, which is a low dielectric material, on the resultant material; Stacking an upper hard mask on the lower hard mask and then laminating a photoresist on the lower hard mask to form a pattern; After the forming of the first contact by etching the upper hard mask, and removing the remaining upper hard mask; Etching the lower hard mask through the first contact to form a second contact after the step; After the step is achieved by forming a third contact by etching the diffusion barrier, the metal layer and the anti-reflection film through a second contact to provide a method for forming a metal wiring pattern of a semiconductor device.
그리고, 상기 하부하드마스크는, 탄소가 결합된 유기계열의 물질로서, 10000 ∼ 15000Å의 두께로 적층하는 것이 바람직 하다.In addition, the lower hard mask is an organic-based material bonded to carbon, and is preferably laminated at a thickness of 10000 to 15000 kPa.
또한, 상기 상부하드마스크는, 규소 산화물 혹은 질화물을 PE-CVD(Plasma-Enhanced Chemical Vapor Deposition)법으로 증착하고, 500 ∼ 2000Å의 두께로 적층하는 것이 바람직 하다.In addition, the upper hard mask is preferably deposited by depositing silicon oxide or nitride by a Plasma-Enhanced Chemical Vapor Deposition (PE-CVD) method and having a thickness of 500 to 2000 GPa.
상기 감광막은, 2000 ∼ 5000Å의 두께로 적층하는 것이 바람직 하다.It is preferable to laminate | stack the said photosensitive film in thickness of 2000-5000 kPa.
상기 상부하드마스크는, 플라즈마 건식식각법으로 식각하고, 50 ∼ 200 mTorr / 500 ∼ 800 Watt / 0 ∼ 50 Gauss / 5 ∼ 30 CHF3 / 5 ∼ 30 CF4 / 100 ∼ 200 Ar의 조건 혹은, 5 ∼ 20 mTorr / 1000 ∼ 2000 WSP(Source Power) / 200∼ 600 WBP(Bias Power) / 5 ∼ 30 CHF3 / 0 ∼30 CF4 / 50 ∼ 200 Ar의 조건으로 식각하는 것이 바람직 하다.The upper hard mask is etched in a plasma dry etching method, and, 50 ~ 200 mTorr / 500 ~ 800 Watt / 0 ~ 50 Gauss / 5 ~ 30 CHF 3/5 ~ 30 CF 4/100 ~ 200 Ar conditions or, 5 It is preferable to etch under conditions of -20 mTorr / 1000-2000 WSP (Source Power) / 200-600 WBP (Bias Power) / 5-30 CHF 3 /0-30 CF 4 /50-200 Ar.
그리고, 상기 하부하드마스크는, 플라즈마 건식식각법으로 식각하고, 50 ∼ 200 mTorr / 500 ∼ 1000 Watt / 0 ∼ 50 Gauss / 10 ∼ 50 H2 / 20 ∼ 100N2 / 5 ∼ 10 O2 / 5 ∼ 10 CHF3 / 50 ∼ 200 Ar의 조건 혹은, 10 ∼ 50 mTorr / 500 ∼ 1000 WSP / 200∼ 600 WBP / 10 ∼ 50 H2 / 20 ∼ 100 N2 / 5 ∼ 10 O2 / 5 ∼ 10 CHF3 / 50 ∼ 100 Ar의 조건으로 식각하는 것이 바람직 하다.In addition, the lower hard mask is etched in a plasma dry etching method, and, 50 ~ 200 mTorr / 500 ~ 1000 Watt / 0 ~ 50 Gauss / 10 ~ 50 H 2/20 ~ 100N 2/5 ~ 10 O 2/5 ~ 10 CHF 3/50 ~ 200 Ar or condition, 10 ~ 50 mTorr / 500 ~ 1000 WSP / 200~ 600 WBP / 10 ~ 50 H 2/20 ~ 100 N 2/5 ~ 10 O 2/5 ~ 10 CHF 3 It is preferable to etch on the conditions of 50-50 Ar.
상기 제1콘택을 형성한 후, 잔류된 상부하드마스크를 제거할 때, 100 ∼ 200 mTorr / 500 ∼ 800 Watt / 0 ∼ 50 Gauss / 5 ∼ 30 CHF3 / 5 ∼ 30 CF4 / 100 ∼ 200 Ar의 조건 혹은, 10 ∼ 30 mTorr / 1000 ∼ 2000 WSP / 200 ∼ 600 WBP / 5 ∼ 30 CHF3 / 0 ∼30 CF4 / 50 ∼ 200 Ar의 조건으로 식각하는 것이 바람직 하다.After the formation of the first contact, to remove the remaining upper hardmask, 100 ~ 200 mTorr / 500 ~ 800 Watt / 0 ~ 50 Gauss / 5 ~ 30 CHF 3/5 ~ 30 CF 4/100 ~ 200 Ar It is preferable to etch on the conditions of or 10-30 mTorr / 1000-2000 WSP / 200-600 WBP / 5-30 CHF 3 / 0-30 CF 4 / 50-200 Ar.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 일실시예에 대해 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 3(a) 내지 도 3(f)는 본 발명에 따른 반도체소자의 금속배선패턴 형성방법을 순차적으로 보인 도면이다.3 (a) to 3 (f) are views sequentially showing a method for forming a metal wiring pattern of a semiconductor device according to the present invention.
도 3(a)에 도시된 바와 같이, 소자하부 구조(10) 상에 반사방지막(20), 금속층 (30) 및 확산방지막(40)을 순차적으로 적층하도록 한다. 상기 금속층(30)은 Al-Cu층 혹은 Al-Cu-Si층을 사용하도록 한다.As shown in FIG. 3A, the antireflection film 20, the metal layer 30, and the diffusion barrier film 40 are sequentially stacked on the device lower structure 10. The metal layer 30 uses an Al-Cu layer or an Al-Cu-Si layer.
도 3(b)에 도시된 바와같이, 상기 결과물 상에 저유전체물질인 하부하드마스크(50)를 적층하도록 한다. 이 하부하드마스크(50)는, 탄소(Carbon)가 결합된 유기계열의 물질로서, 10000 ∼ 15000Å의 두께로 적층하도록 한다.As shown in FIG. 3 (b), the lower hard mask 50, which is a low dielectric material, is laminated on the resultant. The lower hard mask 50 is an organic-based material to which carbon is bonded, and is laminated to a thickness of 10000 to 15000 kPa.
도 3(c)에 도시된 바와 같이, 상기 하부하드마스크(50) 상에 상부하드마스크 (60)를 적층한 후, 그 위에 2000 ∼ 5000Å의 두께로 적층되는 감광막(65)을 적층하여 패턴(Pattern)을 형성하도록 한다.As shown in FIG. 3 (c), after the upper hard mask 60 is laminated on the lower hard mask 50, a photosensitive film 65 laminated at a thickness of 2000 to 5000 m is laminated thereon to form a pattern ( Pattern).
이 때, 상기 상부하드마스크(60)는, 규소 산화물 혹은 질화물을 PE-CVD법으로 증착하고, 500 ∼ 2000Å의 두께로 적층하는 것이 바람직 하다.At this time, the upper hard mask 60 is preferably deposited with a thickness of 500 to 2000 GPa by depositing silicon oxide or nitride by PE-CVD.
도 3(d)에 도시된 바와 같이, 상기 감광막(65)으로 하드마스크(60)을 식각 함으로써 상부하드마스크(60)에 제1콘택(70)을 형성하도록 한다.As shown in FIG. 3D, the hard mask 60 is etched with the photosensitive film 65 to form the first contact 70 in the upper hard mask 60.
이 때, 상기 상부하드마스크(60)는, 플라즈마 건식식각법으로 식각하고, 50 ∼ 200 mTorr / 500 ∼ 800 Watt / 0 ∼ 50 Gauss / 5 ∼ 30 CHF3 / 5 ∼ 30 CF4 / 100 ∼ 200 Ar의 조건 혹은, 5 ∼ 20 mTorr / 1000 ∼ 2000 WSP / 200∼ 600 WBP / 5 ∼ 30 CHF3 / 0 ∼30 CF4 / 50 ∼ 200 Ar의 조건으로 식각하도록 한다.At this time, the upper hard mask 60, and etched in a plasma dry etching method, 50 ~ 200 mTorr / 500 ~ 800 Watt / 0 ~ 50 Gauss / 5 ~ 30 CHF 3/5 ~ 30 CF 4/100 ~ 200 conditions of Ar, or, 5 ~ 20 mTorr / 1000 ~ to be etched under the condition of 2000 WSP / 200~ 600 WBP / 5 ~ 30 CHF 3/0 ~30 CF 4/50 ~ 200 Ar.
도 3(e)에 도시된 바와 같이, 상기 단계 후에 제1콘택(70)을 형성한 후, 잔류된 감광막(65) 및 상부하드마스크(60)를 제거한 후, 제1콘택(70)을 통하여 하부하드마스크(50)에 제2콘택(80)을 형성하는 상태를 도시하고 있다.As shown in FIG. 3E, after the first contact 70 is formed after the step, the remaining photoresist film 65 and the upper hard mask 60 are removed, and then through the first contact 70. A state in which the second contact 80 is formed in the lower hard mask 50 is illustrated.
상기 제1콘택(70)을 형성한 후, 상부하드마스크(60)를 제거할 때, 100 ∼ 200 mTorr / 500 ∼ 800 Watt / 0 ∼ 50 Gauss / 5 ∼ 30 CHF3 / 5 ∼ 30 CF4 / 100 ∼ 200 Ar의 조건 혹은, 10 ∼ 30 mTorr / 1000 ∼ 2000 WSP / 200∼ 600 WBP / 5 ∼ 30 CHF3 / 0 ∼30 CF4 / 50 ∼ 200 Ar의 조건으로 식각하는 것이 바람직 하다.After the formation of the first contact 70, to remove the upper hardmask (60), 100 ~ 200 mTorr / 500 ~ 800 Watt / 0 ~ 50 Gauss / 5 ~ 30 CHF 3/5 ~ 30 CF 4 / It is preferable to etch under conditions of 100-200 Ar or 10-30 mTorr / 1000-2000 WSP / 200-600 WBP / 5-30 CHF 3 / 0-30 CF 4 / 50-200 Ar.
상기 하부하드마스크(50)는, 플라즈마 건식식각법으로 식각하고, 50 ∼ 200 mTorr / 500 ∼ 1000 Watt / 0 ∼ 50 Gauss / 10 ∼ 50 H2 / 20 ∼ 100N2 / 5 ∼ 10 O2 / 5 ∼ 10 CHF3 / 50 ∼ 200 Ar의 조건 혹은, 10 ∼ 50 mTorr / 500 ∼ 1000 WSP / 200∼ 600 WBP / 10 ∼ 50 H2 / 20 ∼ 100 N2 / 5 ∼ 10 O2 / 5 ∼ 10 CHF3 / 50 ∼ 100 Ar의 조건으로 식각하는 것이 바람직 하다.The bottom hard mask 50, and etched in a plasma dry etching method, 50 ~ 200 mTorr / 500 ~ 1000 Watt / 0 ~ 50 Gauss / 10 ~ 50 H 2/20 ~ 100N 2/5 ~ 10 O 2/5 -10 CHF 3 /50-200 Ar or 10-50 mTorr / 500-1000 WSP / 200-600 WBP / 10-50 H 2 /20-100 N 2 /5-10 O 2 /5-10 CHF It is preferable to etch on the conditions of 3 / 50-100 Ar.
도 3(f)에 도시된 바와 같이, 상기 단계 후에 제2콘택(80)을 통하여 확산방지막(40), 금속층(30) 및 반사방지막(20)을 식각하여 제3콘택(90)을 형성하도록 한다.As shown in FIG. 3 (f), after the step, the diffusion barrier film 40, the metal layer 30, and the anti-reflection film 20 are etched through the second contact 80 to form the third contact 90. do.
상기한 바와 같이, 본 발명에 따른 반도체소자의 금속배선패턴 형성방법을 이용하게 되면, 소자하부구조에 반사방지막, 금속층 및 확산방지막을 적층 한 후, 유기계 저유전 물질로 된 제1하드마스크를 적층하고, 그 상부면에 규소산화막 혹은 질화막을 적층한 후, 패턴을 갖는 감광막을 적층하여 저유전물질인 제1하드마스크를 통하여 금속배선패턴을 식각으로 형성하므로 폴리머 부족으로 인하여 금속배선패턴의 내측벽면이 손상되는 것을 방지하여 소자의 전기적인 특성을 향상시키도록 하는 매우 유용하고 효과적인 발명이다.As described above, when the method for forming a metal wiring pattern of the semiconductor device according to the present invention is used, the antireflection film, the metal layer, and the diffusion barrier are laminated on the lower structure of the device, and then the first hard mask made of an organic low dielectric material is laminated. After the silicon oxide film or the nitride film is laminated on the upper surface, the photosensitive film having the pattern is laminated and the metal wiring pattern is etched through the first hard mask which is a low dielectric material. It is a very useful and effective invention which prevents the damage and improves the electrical characteristics of the device.
또한, 종래의 공정에 비하여 매우 얇은 감광막을 사용하므로 마스크공정의 안정성을 증대시키며, 패턴의 해상도를 향상시켜 보다 미세한 패턴을 가공할 수 있도록 하여 소자 공정을 안정적으로 진행하면서도 소자의 크기를 축소하므로 웨이퍼당 발생되는 소자의 페일(Fail)을 감소시켜 소자의 수율을 증대하도록 하는 장점을 지닌다. In addition, the use of a very thin photoresist film compared to the conventional process increases the stability of the mask process, improve the resolution of the pattern to process a finer pattern to reduce the size of the device while proceeding the device process stable, wafers It has the advantage of increasing the yield of the device by reducing the fail (fail) of the device generated sugar.
도 1(a) 내지 도 1(c)는 종래의 금속배선패턴 형성방법을 순차적으로 보인 도면이고,1 (a) to 1 (c) are views sequentially showing a conventional metal wiring pattern forming method,
도 2는 종래의 방법으로 금속배선패턴을 식각할 때, 금속배선패턴이 부러진 상태를 보인 사진이며,2 is a photograph showing a state in which a metal wiring pattern is broken when the metal wiring pattern is etched by a conventional method;
도 3(a) 내지 도 3(f)는 본 발명에 따른 반도체소자의 금속배선패턴 형성방법을 순차적으로 보인 도면이다.3 (a) to 3 (f) are views sequentially showing a method for forming a metal wiring pattern of a semiconductor device according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10 : 소자하부구조 20 : 반사방지막10: device substructure 20: antireflection film
30 : 금속층 40 : 확산방지막30: metal layer 40: diffusion barrier
50 : 제1하드마스크 60 : 제2하드마스크50: first hard mask 60: second hard mask
70 : 제1콘택 80 : 제2콘택70: first contact 80: second contact
90 : 제3콘택 90: third contact
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| JPH10163202A (en) * | 1996-12-03 | 1998-06-19 | Toshiba Corp | Manufacture of semiconductor device |
| KR19990088513A (en) * | 1998-05-28 | 1999-12-27 | 가네꼬 히사시 | Semiconductor device and method of manufacturing the same capable of reducing deterioration of low dielectric constant film |
| KR20000019171A (en) * | 1998-09-09 | 2000-04-06 | 윤종용 | Method for forming metal wire using photosensitive polymer |
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| JPH10163202A (en) * | 1996-12-03 | 1998-06-19 | Toshiba Corp | Manufacture of semiconductor device |
| KR19990088513A (en) * | 1998-05-28 | 1999-12-27 | 가네꼬 히사시 | Semiconductor device and method of manufacturing the same capable of reducing deterioration of low dielectric constant film |
| KR20000019171A (en) * | 1998-09-09 | 2000-04-06 | 윤종용 | Method for forming metal wire using photosensitive polymer |
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| KR100876898B1 (en) * | 2007-08-31 | 2009-01-07 | 주식회사 하이닉스반도체 | Method for manufacturing of hard mask layer of semiconductor device |
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