KR100487414B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR100487414B1 KR100487414B1 KR10-2000-0081214A KR20000081214A KR100487414B1 KR 100487414 B1 KR100487414 B1 KR 100487414B1 KR 20000081214 A KR20000081214 A KR 20000081214A KR 100487414 B1 KR100487414 B1 KR 100487414B1
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- dielectric constant
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- constant material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Abstract
본 발명은 저유전율을 갖는 인터커넥트 구조 형성시키는 방법에 관한 것으로, 본 발명에 따른 반도체 소자 제조방법은 층간 유전체층상에 배선용 금속과 저유전율 재료를 차례로 적층하는 단계와, 상기 저유전율 재료 및 배선용 금속을 선택적으로 제거하여 배선을 형성하는 단계와, 상기 식각된 저유전율 재료를 큐어링하는 단계와, 상기 배선을 포함한 기판 전면 상에 배선간 유전체층을 그 내부에 에어갭이 형성되도록 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention relates to a method for forming an interconnect structure having a low dielectric constant, the method for manufacturing a semiconductor device according to the present invention comprises the steps of laminating a wiring metal and a low dielectric constant material on the interlayer dielectric layer, and the low dielectric constant material and the wiring metal Selectively removing to form a wiring, curing the etched low dielectric constant material, and forming an inter-wire dielectric layer on the entire surface of the substrate including the wiring such that an air gap is formed therein; Characterized in that made.
Description
본 발명은 반도체 소자에 관한 것으로 특히, 저유전율을 갖는 인터커넥트 구조 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices and, more particularly, to a method of forming interconnect structures having low dielectric constants.
반도체 소자 제조에 있어 칩의 크기가 갈수록 작아져 칩의 성능은 인터커넥트의 캐패시턴스에 의해 제한이 된다. 즉, 인터커넥트 캐패시턴스는 소자 제조에 있어 RC 딜레이(Delay), AC power, 크로스 토크에 영향을 미쳐 소자 집적의 한계로 작용한다. 이 인터커넥트 캐패시턴스를 줄이기 위해서 저유전율 물질을 제 2 층간절연막으로 적용하거나 산화물을 이용하여 에어 갭(Air gap)을 인위적으로 형성하여 캐패시턴스 값을 줄이기도 한다.In semiconductor device fabrication, the chip size is getting smaller and the performance of the chip is limited by the capacitance of the interconnect. That is, interconnect capacitance affects the RC delay, AC power, and cross talk in device fabrication, which limits device integration. In order to reduce the interconnect capacitance, a low dielectric constant material may be applied as the second interlayer insulating film, or an air gap may be artificially formed by using an oxide to reduce the capacitance value.
이하, 도면을 참조하여 종래 기술에 따른 반도체 소자 제조방법을 상세히 설명한다.Hereinafter, a semiconductor device manufacturing method according to the related art will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자 제조방법을 설명하기 위한 공정단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 1a에 도시된 바와 같이, 층간 유전체층(Inter Layer Dielectric)(101)상에 도전성 금속을 증착시킨 후, 선택적으로 패터닝하여 배선(102)을 형성한다. 상기 층간 유전체층(101)의 재료는 산화물 등이 이용된다.As shown in FIG. 1A, a conductive metal is deposited on an interlayer dielectric layer 101, and then selectively patterned to form a wiring 102. The material of the interlayer dielectric layer 101 is an oxide or the like.
도 1b에 도시된 바와 같이, 상기 배선(102)을 포함한 기판 전면 상에 저유전율을 갖는 산화물을 적층시켜 금속간 유전체층(Inter Metal Dielectric)(103)을 형성시킨다. 이때, 금속간 유전체층(103) 내부에는 에어갭(Air gap)(104)이 형성되어 캐패시턴스를 줄이는 역할을 수행하게 된다.As shown in FIG. 1B, an oxide having a low dielectric constant is stacked on the entire surface of the substrate including the interconnection 102 to form an intermetal dielectric layer 103. At this time, an air gap 104 is formed inside the intermetallic dielectric layer 103 to reduce capacitance.
도 1c에 도시된 바와 같이, 상기 금속간 유전체층(103) 내부에 형성되어 있는 에어 갭(104)이 드러나도록 평탄화공정을 수행한다. 상기 평탄화공정은 CMP(Chemical Mechanical Polishing)공정히 주로 이용된다.As shown in FIG. 1C, the planarization process is performed to reveal the air gap 104 formed in the intermetal dielectric layer 103. The planarization process is mainly used as a chemical mechanical polishing (CMP) process.
그러나 상기와 같은 종래 반도체 소자 제조방법은 다음과 같은 문제점이 있었다. However, the conventional semiconductor device manufacturing method as described above has the following problems.
종래 기술에 따르면 공정이 단순하고 경제적이나, 수평 캐패시턴스(CL : Lateral Capacitance)를 줄일 수 있는 반면 수직 캐패시턴스((CV : Vertical Capacitance)를 줄일 수 없는 단점이 있다. (도 2 참조)According to the prior art, the process is simple and economical, but the horizontal capacitance (C L : Lateral Capacitance) can be reduced while the vertical capacitance ((C V : Vertical Capacitance) has a disadvantage that can not be reduced (see Fig. 2).
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로, 수직 캐패시턴스를 줄일 수 있는 반도체 소자 제조방법을 제공하는데 목적이 있다.The present invention has been made to solve the above problems, an object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce the vertical capacitance.
상기의 목적을 달성하기 위한 본 발명의 반도체 소자 제조방법은 층간 유전체층상에 배선용 금속과 저유전율 재료를 차례로 적층하는 단계와, 상기 저유전율 재료 및 배선용 금속을 선택적으로 제거하여 배선을 형성하는 단계와, 상기 식각된 저유전율 재료를 큐어링하는 단계와, 상기 배선을 포함한 기판 전면 상에 배선간 유전체층을 그 내부에 에어갭이 형성되도록 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of sequentially laminating a wiring metal and a low dielectric constant material on the interlayer dielectric layer, and selectively removing the low dielectric constant material and the wiring metal to form a wiring; And curing the etched low dielectric constant material, and forming an inter-wire dielectric layer on an entire surface of the substrate including the wiring so that an air gap is formed therein.
본 발명의 특징에 따른 작용은 저유전율 재료를 상기 배선용 금속상에 형성시킴으로써 배선용 금속 좌우 뿐만 아니라 상하 캐패시턴스를 줄일 수 있게 된다.The action according to the characteristics of the present invention is to form a low dielectric constant material on the wiring metal, thereby reducing the upper and lower capacitance as well as the left and right wiring metals.
이하, 도면을 참조하여 본 발명에 따른 반도체 소자 제조방법을 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 3d는 본 발명에 따른 반도체 소자 제조방법을 설명하기 위한 공정단면도이다.3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
도 3a에 도시된 바와 같이, 층간 유전체층(301)상에 배선용 금속(302)과 저유전율 재료(303)를 차례로 적층시킨다. 이어서, 상기 배선용 금속(302)의 식각 배리어(Barrier)로 사용될 저유전율 재료(303)의 식각을 위해 포토레지스트(304)를 도포하여 패터닝한다. 여기서, 상기 저유전율 재료(303)는 실크(Silk), 플레어(Flare), HSG, HOSP, 실리콘 카바이드(SiC), BOSS, 코랄(Coral) 등이 이용된다.As shown in FIG. 3A, the wiring metal 302 and the low dielectric constant material 303 are sequentially stacked on the interlayer dielectric layer 301. Subsequently, the photoresist 304 is coated and patterned to etch the low dielectric constant material 303 to be used as an etch barrier of the wiring metal 302. In this case, the low dielectric constant material 303 may include silk, flare, HSG, HOSP, silicon carbide (SiC), BOSS, coral, or the like.
도 3b에 도시된 바와 같이, 상기 포토레지스트(304)를 마스크로 이용하여 상기 저유전율 재료를 식각한다. 상기 저유전율 재료를 식각한 후, 식각 체임버(Chamber)내에서 큐어링(Curing)을 실시한다. 상기 저유전율 재료의 큐어링은 아르곤(Ar), 헬륨(He), 네온(Ne), 질소(N2) 가스 등으로 20 V 이상의 전압으로 이온충격(Ion Bombarding)을 주어 탄화시킨다.As shown in FIG. 3B, the low dielectric constant material is etched using the photoresist 304 as a mask. After the low dielectric constant material is etched, curing is performed in an etch chamber. Curing of the low dielectric constant material is carbonized by argon (Ar), helium (He), neon (Ne), nitrogen (N 2 ) gas, and the like with ion bombarding at a voltage of 20 V or more.
이어, 도 3c에 도시된 바와 같이, 상기 식각된 저유전율 재료(303)를 마스크로 이용하여 상기 도전성 금속을 식각하여 배선(302)을 형성시킨다. 상기 식각된 저유전율 재료의 장경비(Aspect ratio)는 3:1 이하이다.Subsequently, as shown in FIG. 3C, the conductive metal is etched using the etched low dielectric constant material 303 as a mask to form a wiring 302. The aspect ratio of the etched low dielectric constant material is less than 3: 1.
여기서, 상기 저유전율 재료의 식각은 상기 포토레지스트와의 식각선택비를 담보하기 위하여 식각 체임버(Chamber)의 조건을 저전력(100W)으로 하여 아르곤(Ar), 헬륨(He), 네온(Ne), 크세논(Xe)와 같은 불활성 가스를 이용하여 물리적인 식각을 행한다.Here, the etching of the low dielectric constant material is made of argon (Ar), helium (He), neon (Ne), with the condition of the etching chamber (Chamber) to a low power (100W) to secure the etching selectivity with the photoresist Physical etching is performed using an inert gas such as xenon (Xe).
도 3d에 도시된 바와 같이, 상기 저유전율 재료(303)를 포함한 기판 전면에 금속간 유전체층(305)을 적층시킨다. 이때, 상기 금속간 유전체층(305) 내부에는 에어 갭(306)이 형성되도록 한다. 상기 금속간 유전체층(305)은 산화물 또는 저유전율을 갖는 물질이다.As shown in FIG. 3D, an intermetal dielectric layer 305 is deposited over the substrate surface including the low dielectric constant material 303. In this case, an air gap 306 is formed in the intermetal dielectric layer 305. The intermetal dielectric layer 305 is an oxide or a material having a low dielectric constant.
한편, 상기 금속간 유전체층을 적층시켜 에어갭을 형성시키기 전에 식각배리어로 이용된 저유전율 재료를 식각 체임버IChamber)내에서 NH3, H2O, NH4F, HCl 등을 이용하여 보호막처리를 할 수 있다.On the other hand, the low-k dielectric material used as an etching barrier is subjected to a protective film treatment using NH 3 , H 2 O, NH 4 F, HCl, etc. in the etching chamber IC before the intermetal dielectric layer is laminated to form an air gap. Can be.
이상 상술한 바와 같이, 본 발명에 따른 반도체 소자 제조방법은 다음과 같은 효과가 있다.As described above, the semiconductor device manufacturing method according to the present invention has the following effects.
배선용 금속상에 저유전율 재료를 형성시킴으로써 수평 뿐만 아니라 수직 캐패시턴스(CV : Vertical Capacitance)를 줄일 수 있는 장점이 있다.By forming a low dielectric constant material on the wiring metal, there is an advantage in that not only horizontal but also vertical capacitance (C V ) can be reduced.
도 1a 내지 1c는 종래 기술에 따른 반도체 소자 제조방법을 설명하기 위한 공정단면도.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2는 종래 기술에 따른 반도체 소자의 수평, 수직 캐패시턴스를 설명하기 위한 회로도.2 is a circuit diagram illustrating horizontal and vertical capacitance of a semiconductor device according to the prior art.
도 3a 내지 3d는 본 발명에 따른 반도체 소자 제조방법을 설명하기 위한 공정단면도.3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
301 : 층간 유전체층 302 : 배선용 금속301: interlayer dielectric layer 302: wiring metal
303 : 저유전율 재료 304 : 포토레지스트303: low dielectric constant material 304: photoresist
305 : 금속간 유전체층 306 : 에어 갭305: intermetal dielectric layer 306: air gap
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| KR10-2000-0081214A KR100487414B1 (en) | 2000-12-23 | 2000-12-23 | Manufacturing method of semiconductor device |
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| KR10-2000-0081214A KR100487414B1 (en) | 2000-12-23 | 2000-12-23 | Manufacturing method of semiconductor device |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07326670A (en) * | 1994-05-31 | 1995-12-12 | Texas Instr Inc <Ti> | Semiconductor integrated circuit device |
| JP2000031278A (en) * | 1998-07-10 | 2000-01-28 | Nippon Steel Corp | Semiconductor device and manufacture thereof |
| KR20000017167A (en) * | 1998-08-19 | 2000-03-25 | 포만 제프리 엘 | Methods for making high-aspect ratio holes in semiconductor and its application to a gate damascene process for sub-0.05 micrometer mosfets |
| KR20000054889A (en) * | 1999-02-01 | 2000-09-05 | 윤종용 | Semiconductor device having air gap in interlevel insulating layer and manufacturing method thereof |
| KR20000056157A (en) * | 1999-02-13 | 2000-09-15 | 윤종용 | Process for forming air gaps using a multilayer passivation in a dielectric between interconnections |
| US6162723A (en) * | 1996-06-27 | 2000-12-19 | Nec Corporation | Method of fabricating a semiconductor integrated circuit device having an interlevel dielectric layer with voids between narrowly-spaced wiring lines |
-
2000
- 2000-12-23 KR KR10-2000-0081214A patent/KR100487414B1/en not_active IP Right Cessation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07326670A (en) * | 1994-05-31 | 1995-12-12 | Texas Instr Inc <Ti> | Semiconductor integrated circuit device |
| US6162723A (en) * | 1996-06-27 | 2000-12-19 | Nec Corporation | Method of fabricating a semiconductor integrated circuit device having an interlevel dielectric layer with voids between narrowly-spaced wiring lines |
| JP2000031278A (en) * | 1998-07-10 | 2000-01-28 | Nippon Steel Corp | Semiconductor device and manufacture thereof |
| KR20000017167A (en) * | 1998-08-19 | 2000-03-25 | 포만 제프리 엘 | Methods for making high-aspect ratio holes in semiconductor and its application to a gate damascene process for sub-0.05 micrometer mosfets |
| KR20000054889A (en) * | 1999-02-01 | 2000-09-05 | 윤종용 | Semiconductor device having air gap in interlevel insulating layer and manufacturing method thereof |
| KR20000056157A (en) * | 1999-02-13 | 2000-09-15 | 윤종용 | Process for forming air gaps using a multilayer passivation in a dielectric between interconnections |
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| KR20020052036A (en) | 2002-07-02 |
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