KR100486202B1 - Semiconductor voltage pumping apparatus - Google Patents

Abstract

The present invention relates to a semiconductor boosting device.

According to another aspect of the present invention, there is provided a boosting device, comprising: a first boosting circuit including a first capacitor for charge selectively connected to a reference voltage and a second pumping capacitor selectively connected to the reference voltage and the first capacitor for charging; A second boost circuit comprising a pumping third capacitor selectively connected to the charge first capacitor and the pumping second capacitor of the first boost circuit; And a pulse generator for generating pulse signals for driving the first boost circuit and the second boost circuit.

The boosting apparatus according to the present invention allows the charge capacitor provided in the first boosting circuit installed at the first stage to be shared by the second boosting circuit at the rear stage, and the second boosting circuit performs the pumping operation at the second pumping timing of the first boosting circuit. This allows the boosting effect to be achieved even with a small number of capacitors.

Description

Semiconductor voltage pumping apparatus

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor boosting device, and more particularly, to a boosting device using a smaller number of capacitors than a conventional boosting device.

The boosting device generates a voltage at a level higher than a normal power supply voltage. The boosting device is adopted to weaken the signal and shorten the access time due to the high load generated as the chip size of the semiconductor memory device increases. That is, when the chip size of the semiconductor device increases, there is a problem in that the signal is lost due to the voltage drop (IR drop) caused by the resistance component even before the signal reaches the required place in the chip. In particular, as the load of the word line increases, the time required for the word line enable increases. In addition, since the word line is driven, the bit line and the inverted bit line are charged sharing according to the data stored in the memory cell, thereby increasing the time required for the level transition to occur. Therefore, a boosted voltage is required to shorten the time required for driving the word line.

In addition, even in a micom product for driving a liquid crystal display (hereinafter referred to as LCD), various bias voltages are required to drive the LCD. LCD driving bias generation circuits currently used are power supply voltage dividers using a resistor division method, and use a constant ratio of resistors. In this method, there is a disadvantage in that constant current is always consumed, and when the power supply voltage is lower than the constant voltage, it is difficult to use. Also, as the power supply voltage changes, each bias voltage is changed at a constant rate to affect the external LCD panel. do.

Accordingly, in order to obtain an efficient LCD driving bias voltage, a boost circuit having two to three times the reference voltage is frequently used.

However, in the microcom product for driving a large LCD, it is not enough to drive a large LCD with a voltage boosted by 2 to 3 times, so that several boosting circuits are connected in series. Each boost circuit generates a boost voltage that is required by charge pumping and capacitor storage. Accordingly, as the boosted voltage increases, the number of ports for allowing the external capacitor and the connection thereof is increased.

The present invention has been made to solve some of the above problems, and an object thereof is to provide a boosting device that generates a required boosting voltage while using a smaller number of capacitors than a conventional boosting device.

A boosting circuit according to the present invention for achieving the above object includes a charge first capacitor that can be selectively connected to a reference voltage and a pumping second capacitor that is selectively connected to the reference voltage and the charge first capacitor. A first boost circuit;

A second boost circuit comprising a pumping third capacitor selectively connected to the charge first capacitor and the pumping second capacitor of the first boost circuit; And

And a pulse generator for generating pulse signals for driving the first boost circuit and the second boost circuit.

Here, the first capacitor for charge of the first boost circuit is selectively connected to the reference voltage by a first pulse signal for setting the charge timing, and is charged by the charge provided by the reference voltage at every charge timing. The second capacitor for pumping is selectively connected to the reference voltage and the first capacitor for charge by a second pulse signal for setting a pumping timing, and the charge and charge are provided by the reference voltage at every pumping timing. Pumped by the charge provided by the capacitor,

The pumping third capacitor of the second boosting circuit is connected to the charge first capacitor and the pumping second capacitor by a third pulse signal for setting a pumping timing to pump the second pump of the first boosting circuit. Pumped by the charge provided by the charge first capacitor and the charge provided by the pumping second capacitor at each timing, and

The pulse generator may include a first pulse signal having a predetermined period, a second pulse signal having a period twice that of the first pulse signal, and the second pulse signal by one period of the first pulse signal. A delayed third pulse signal is generated.

The boosting apparatus according to the present invention allows the charge capacitor provided in the first boosting circuit installed at the first stage to be shared by the second boosting circuit at the rear stage, and the second boosting circuit performs the pumping operation at the second pumping timing of the first boosting circuit. This allows the boosting effect to be achieved even with a small number of capacitors.

Hereinafter, the configuration and operation of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram showing the configuration of a conventional boosting device. In Fig. 1, reference numeral 10 denotes a level shifter portion, 12 denotes a substrate bias holding portion, 14, 16, 18 and 20 denote a boosting device, and 22 denotes a well bias holding portion.

The level shifter unit 10 is for level shifting two complementary signals s1b and s2b for driving the apparatus shown in FIG. 1 and includes the level shifters 10a and 10b and the buffers 10c and 10d. do.

The first boost circuit 14 is driven by the complementary first and second pulse signals s1b and s2b. The first boost circuit 14 may include a first node P1 to which the reference voltage Vreg is applied, a second node P2 where a voltage occupied by the reference voltage Vreg, a voltage occupied by the second node, and a reference voltage applied to the first node. A third node P3 showing a voltage doubled by Vreg, a power capacitor C1 connected between the first node and the substrate bias voltage Vss, a charge capacitor Ca connected between the second node P2 and the reference node P0, and a third A capacitor C2 connected between the node P3 and the substrate bias voltage Vss, a second transistor T2 connected between the first node P1 and the reference node P0 and driven by a second pulse signal s2b, between the first node P1 and the second node P2 A third transistor T3 connected to and driven by the first pulse signal s1b, a fourth transistor T4 connected between the second node P2 and the third node P3 and driven by the second pulse signal s2b.

The second to fourth boost circuits 18 to 22 are connected in series between the output terminal of the front boost circuit and the output terminal thereof, and two transistors T5 / T6 driven by the first pulse signal s1b and the second pulse signal s2b, respectively. , T7 / T8, T9 / T10, charge capacitors (Cb, Cc, Cd) connected between the connection point of the two transistors and the reference node P0, and a pumping capacitor (C3) connected between its output terminal and the substrate bias voltage Vss. , C4, C5).

In the apparatus shown in FIG. 1, the charge time is defined when the first pulse signal s1b is low and the pumping time is defined when the second pulse signal s2b is low. The two pulse signals are complementary, so the charge time and pumping time are continuously alternating throughout.

The substrate bias holding unit 12 includes a transistor T1 for maintaining the reference node P0 at the charge time at the substrate bias voltage Vss, and the well bias holding unit 22 maintains the output point P9 at the well bias voltage Vdd. The main includes a transistor T11.

FIG. 2 is a waveform diagram showing waveforms of signals applied to the apparatus shown in FIG. 1. Shown at the top in FIG. 2 is the signal S1b for defining the charge time, and shown at the bottom is a signal s2b for defining the pumping time. The period in which s1a becomes the low level (sections a, c, e, and g of FIG. 2) becomes the charge time, and the period in which s2b becomes the low level (sections b, d, f, and h in FIG. 2) is the pumping time. do.

FIG. 3 is a conceptual diagram for describing an operation of the apparatus illustrated in FIG. 1. FIG. 3 shows the divided sections for each section a-h shown in FIG. 2. First, in section a, the Ca connected between the P1 and P2 nodes is occupied at the Vreg level by the charge provided from the reference voltage Vreg applied through the Vreg terminal.

In section b, C2 is pumped to 2Vreg level by the charges Qa and Ca in charge.

In section c, Cb connected between the P0 node and the P4 node is occupied at 2Vreg level by the electric charge provided from C2.

In section d, C3 is pumped to 3Vreg level by the charges in charges Qa and Cb in C1.

In the e section, Cc connected between the P0 node and the P6 node is occupied at 3Vreg level by the electric charge provided from C3.

In the f section, C4 is pumped to 4Vreg level by the charges Qa and Cc in C1.

In the g section, Cd connected between the P0 node and the P8 node is occupied at 4Vreg level by the electric charge provided from C4.

In section h, C5 is pumped to the level of 5Vreg by the charges Qa and Cd in charge.

In this way, a voltage boosted five times from C5 is obtained. In the apparatus shown in FIG. 1, nine capacitors are required to obtain a voltage boosted five times. As the boost voltage increases, the number of these capacitors increases.

FIG. 4 is a circuit diagram showing an embodiment of the present invention and shows a boosting device for generating a voltage 5Vreg boosted by 5 times the reference voltage Vreg as in the device shown in FIG. 1. The apparatus shown in FIG. 4 includes a pulse generator 40, a first boost circuit 42, a second boost circuit 44, a third boost circuit 46, and a fourth boost circuit 48.

The first booster circuit 42 is driven by the complementary first and second pulse signals chargeb and pump2b. The first boost circuit 42 may include a first node P1 to which the reference voltage Vreg is applied, a second node P2 where a voltage occupied by the reference voltage Vreg, a voltage occupied by the second node, and a reference voltage applied to the first node. A third node P3 showing a voltage doubled by Vreg, a power capacitor C0 connected between the first node and the substrate bias voltage Vss, a first capacitor C1 for charge connected between the second node P2 and the reference node P0, Pumping second capacitor C2 connected between the third node P3 and the substrate bias voltage Vss, the second switching transistor T2 connected between the first node P1 and the reference node P0 and driven by the second pulse signal pumb2, the first node A third switching transistor T3 connected between P1 and a second node P2 and driven by a first pulse signal chargeb, a fourth switching connected between a second node P2 and a third node P3 and driven by a second pulse signal pumb2b Transistor T4.

The second boost circuit 44 is driven by the pumping third capacitor C3 and the third pulse signal pump3 connected between the fourth node P4 and the substrate bias voltage Vss, so that the first boosting circuit 44 is driven at the pumping timing of the first boosting circuit 42. Two switching transistors T5 and T6 are provided to allow paths to nodes, reference nodes, third nodes, second nodes, fourth nodes, and Vss.

The third booster circuit 46 is driven by the fourth pumping capacitor C4 and the fourth pulse signal pumb4 connected between the fifth node P5 and the reference node P0 to be driven by the first node at the pumping timing of the first booster circuit 42. And two switching transistors T7 and T8 allowing paths to the reference node, third node, second node, fourth node, and Vss.

The fourth boosting circuit 48 is driven by the fifth pumping capacitor C5 and the fifth pulse signal pumb5 connected between the sixth node P6 and the reference node P0 to be driven by the first node at the pumping timing of the first boosting circuit 42. And two switching transistors T9 and T10 to allow paths to the reference node, the fourth node, the second node, the fifth node, and Vss.

The substrate bias holding circuit 50 is connected between the reference node P0 and the substrate bias voltage Vss and driven by the first pulse signal chargeb to hold the reference node P0 at the charge timing of the first boosting circuit 42 at the substrate bias voltage Vss. And a first switching transistor T1.

The well bias holding circuit 52 includes an eleventh transistor T11 connected between the second node P2 of the first boosting circuit 40 and the well bias voltage Vdd to maintain the well bias.

In describing the operation of the apparatus shown in FIG. 4, the signals applied to the respective portions are regarded as level shifted by the level shifter as shown in FIG. 1.

FIG. 5 is a timing diagram illustrating timings of the first to fifth pulse signals shown in FIG. 4. In FIG. 4, sections a, c, e, and g are charge sections, and sections b, d, f, and h are pumping sections.

FIG. 6 is illustrated for conceptually describing the operation of the apparatus shown in FIG. 4. FIG. 6 illustrates the divisions of the sections a-h shown in FIG. 5. First, in the section a, C1 connected between the first node P1 and the reference node P0 is occupied at the Vreg level by the charge provided from the reference voltage Vreg applied through the first node P1.

In section b, C2 is pumped to the level of 2Vreg by the charges Qa and C1 in the power capacitor C0.

In section c, as in section a, C1 connected between the first node P1 and the reference node P0 is occupied at the level of Vreg by the charge provided from the reference voltage Vreg applied through the first node P1.

In section d, C3 is pumped to the level of 3Vreg by the charge in C2 and the charge in C1.

In section e, as in section a, C1 connected between the first node P1 and the reference node P0 is occupied at the level of Vreg by the charge provided from the reference voltage Vreg applied through the first node P1.

In the f section, C4 is pumped to the 4Vreg level by the charge in C3 and the charge in C1.

In section g, as in section a, C1 connected between first node P1 and reference node P0 is occupied at the level of Vreg by charges provided from reference voltage Vreg applied through first node P1.

In section h, C5 is pumped to the level of 5Vreg by the charge in C3 and the charge in C1.

In this manner, the voltage boosted by five times in the sixth node P6 is output. It can be seen that the number of capacitors in the apparatus shown in FIG. 4 is six, which is less than three in comparison with the apparatus shown in FIG. This is the result of allowing the charge capacitor C1 to be shared by each boost circuit.

FIG. 7 is a timing diagram illustrating an operation of the pulse generator illustrated in FIG. 4. The pulse generator 40 generates signals of 8KHz and 16KHz through a divider circuit using a 32KHz basic clock, and a pumping signal (pumb2b-pumb5b) driving large switching elements is a combination of signals of 32KHz and 8KHz. And the remaining signals necessary to hold the small well bias Vdd are generated by combining the charge signal chargeb and the pumping signals pumb2b and pumb5b.

Specifically,

chargeb = 32KHz signal (32k) + delay signal of 32KHz signal (32kd)

16k = 16KHz signal

8k = 8KHz signal

16kb = 16KHz inversion signal

8kb = 8KHz inversion signal

32kdb = 32KHz delay inversion signal

32kb = 32KHz inversion signal

pump2b = 32kb + 32kdb + 16k + 8k

pump3b = 32kb + 32kdb + 16kb + 8k

pump4b = 23kb + 32kdb + 16k + 8kb

pump5b = 32 kb + 32 kdb + 16 kb + 8 kb

cb_p2b = chargebpump2b

cb_p23b = chargebpump2bpump3b

p2345b = pump2bpump3bpump4bpump5b

p345b = pump3bpump4bpump5b

p45b = pump3b pump4b pump5b.

Here, + represents an ora operation and · represents an AND operation.

FIG. 8 is a characteristic diagram illustrating an operating characteristic of the apparatus shown in FIG. 4. In FIG. 8, the horizontal axis represents time, and the vertical axis represents voltage. As shown in FIG. 8, it can be seen that a voltage stepped up by Vreg in C2, C3, C4, and C5 is sequentially increased by 5 times to finally increase voltage by 5 times in C5.

As described above, the boosting device according to the present invention allows the charge capacitor provided in the first boosting circuit installed at the first stage to be shared by the second boosting circuit at the rear stage, and the second boosting circuit has a second pumping timing of the first boosting circuit. By performing the pumping operation at, the boosting effect is achieved even with a small number of capacitors.

1 is a circuit diagram showing the configuration of a conventional boosting device.

FIG. 2 is a waveform diagram showing waveforms of signals applied to the apparatus shown in FIG. 1.

FIG. 3 is a conceptual diagram for describing an operation of the apparatus illustrated in FIG. 1.

4 is a circuit diagram showing the configuration of an embodiment of a boosting device according to the present invention.

FIG. 5 is a waveform diagram showing signals applied to the apparatus shown in FIG. 4.

FIG. 6 is a conceptual diagram for describing an operation of the apparatus illustrated in FIG. 4.

FIG. 7 is illustrated to explain the operation of the pulse generator shown in FIG. 4.

FIG. 8 is a characteristic diagram illustrating operating characteristics of the apparatus illustrated in FIG. 4.

Claims (4)

A first boosting circuit having a first capacitor for charge selectively connected to a reference voltage and a second pumping capacitor selectively connected to the reference voltage and the first capacitor for charging; A second boost circuit comprising a pumping third capacitor selectively connected to the charge first capacitor and the pumping second capacitor of the first boost circuit; And A pulse generator for generating pulse signals for driving the first boost circuit and the second boost circuit; Here, the first capacitor for charge of the first boost circuit is selectively connected to the reference voltage by a first pulse signal for setting the charge timing, and is charged by the charge provided by the reference voltage at every charge timing. The second capacitor for pumping is selectively connected to the reference voltage and the first capacitor for charge by a second pulse signal for setting a pumping timing, and the charge and charge are provided by the reference voltage at every pumping timing. Pumped by the charge provided by the capacitor, The pumping third capacitor of the second boosting circuit is connected to the charge first capacitor and the pumping second capacitor by a third pulse signal for setting a pumping timing to pump the second pump of the first boosting circuit. Pumped by the charge provided by the charge first capacitor and the charge provided by the pumping second capacitor at each timing, and The pulse generator may include a first pulse signal having a predetermined period, a second pulse signal having a period twice that of the first pulse signal, and the second pulse signal by one period of the first pulse signal. And generating a delayed third pulse signal. The method of claim 1, A third pumping timing of the first boosting circuit, selectively connected to the charge first capacitor of the first boosting circuit and the third capacitor for pumping of the second boosting circuit by a fourth pulse signal for setting a pumping timing; And a third boosting circuit each including a pumping fourth capacitor pumped by the charge provided by the first capacitor for charge and the charge provided by the third capacitor for pumping the second boost circuit. The pulse generator may include a first pulse signal having a predetermined period, a second pulse signal having a period three times that is complementary to the first pulse signal, and the second pulse signal by one period of the first pulse signal. And boosting the third pulse signal delayed by the third pulse signal and the fourth pulse signal delaying the third pulse signal by one period of the first pulse signal. A first capacitor for charging; Second and third switching transistors connected in series with each other, and both ends of the series connection connected in parallel with the charge first capacitors; A fourth switching transistor connected to one end of the charge first capacitor; And a first boosting circuit including a pumping second transistor connected to the first capacitor for charge through the fourth switching transistor. A pumping third capacitor pumped at a second pumping timing of the first boost circuit; A fifth switching transistor connected between the pumping second capacitor of the first boost circuit and the other end of the charge first capacitor; And a second boosting circuit including a sixth switching transistor connected between one end of the first capacitor of the first boosting circuit and the pumping third capacitor. A pulse generator for generating pulse signals for driving the first boost circuit and the second boost circuit; A substrate bias holding circuit having a first switching transistor for holding the other end of the first capacitor for charge at a substrate bias voltage at a charge timing of the first boost circuit; And A well bias holding circuit configured to hold one end of the first capacitor for charge of the first boosting circuit at a well bias potential, Here, the third transistor of the first boosting circuit selectively connects the first capacitor for charge to the reference voltage by a first pulse signal for setting the charge timing, and the second transistor and the fourth transistor are respectively Selectively connecting the pumping second capacitor to the reference voltage and the charging first capacitor by a second pulse signal for setting a pumping timing, The fifth transistor and the sixth transistor of the second boost circuit selectively select the pumping third capacitor by the third pulse signal for setting a pumping timing, and the first capacitor for the charge of the first boost circuit and Connected to the second capacitor for pumping, A first switching transistor of the substrate bias holding circuit connects a substrate bias voltage to the other end of the first pumping capacitor by a first pulse signal, and The pulse generator may include a first pulse signal having a predetermined period, a second pulse signal having a period twice that of the first pulse signal, and the second pulse signal by one period of the first pulse signal. And generating a delayed third pulse signal. The method of claim 3, A pumping fourth capacitor pumped at a third pumping timing of the first boosting circuit; a seventh switching transistor connecting the other end of the pumping fourth capacitor and the first capacitor for charging the first boosting circuit; And a third boosting circuit including an eighth switching transistor connecting one end of the charge first capacitor of the first boosting circuit to the pumping fourth capacitor, The pulse generator may include a first pulse signal having a predetermined period, a second pulse signal having a period three times that is complementary to the first pulse signal, and the second pulse signal by one period of the first pulse signal. And boosting the third pulse signal delayed by the third pulse signal and the fourth pulse signal delaying the third pulse signal by one period of the first pulse signal.

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