KR100485031B1 - A method of fabricating a semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device is provided to enhance the reliability of contact by performing a reflow process using an element of 12 to 15 group. At least one transistor with a conductive material is formed on a semiconductor substrate(201) of an SOI(Silicon On Insulator) structure. An insulating layer(211) is formed on the substrate. A contact hole(212) for exposing the conductive material of the transistor to the outside is formed in the insulating layer. A metal line material for contacting electrically the conductive material is formed on a bottom of the contact hole. A predetermined layer containing one selected from a group consisting of 12 to 15 group elements is formed on the metal line material. A reflow process is performed on the metal line material by using a heat treatment within a predetermined temperature range of 400°C or less.

Description

A method of fabricating a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device made of aluminum or having a wiring electrode composed mainly of aluminum.

In recent years, with the high density integration of devices, the necessity of manufacturing millions of semiconductor devices on one chip or on the same substrate is increasing. A problem in manufacturing a semiconductor device in large quantities is a production yield, and a poor operation of the semiconductor device greatly reduces the production yield. As one of the main causes of the malfunction of the semiconductor device, a contact (contact) defect has been pointed out.

Contact failure is an operation failure caused when a connection failure occurs in a portion (hereinafter referred to as "contact") that electrically connects the wiring electrode and the semiconductor device. In particular, the need for making an electrical connection through thin holes (contact holes) by the miniaturization technique and the multi-layered wiring technique is increasing, and contact failure is a serious problem.

There are three main causes of poor contact. The first cause is that the conductive film forming the wiring electrode and the source / drain region (semiconductor film) or the extraction electrode (conductive film) are not connected by ohmic contact. This is due to the fact that an insulating film such as a metal oxide is formed on the contact surface.

The second cause is that the coverage of the conductive film forming the wiring electrode is poor and a disconnection occurs in the contact hole. In this case, improvement should be made by the film forming method or the film forming conditions of the wiring electrode.

The third cause is disconnection of the wiring electrode caused by the cross-sectional shape of the contact hole or the like. The cross-sectional shape of the contact hole largely depends on the etching conditions of the insulator (SiN, SiO ₂ , organic resin film, etc.) covered by the contact portion.

In particular, as the aspect ratio of the contact hole becomes high due to the miniaturization of the semiconductor device, contact failure caused by the second and third causes is realized.

The invention disclosed in the present specification aims to reduce an operation failure of a semiconductor device due to a poor contact by solving the above problem. In particular, it is an object of the present invention to provide a technique for eliminating contact defects when a material consisting of aluminum or containing aluminum as a main component is used as a wiring electrode.

It is also an object of the present invention to provide a technique for realizing a semiconductor device or an electro-optical device having high long-term reliability by improving the reliability of the contact. Moreover, the objective of this invention is to raise the yield of a manufacturing process.

According to one aspect of the present invention, there is provided a semiconductor device having a structure having a conductive material and an insulating film formed on the conductive material, the method comprising: forming a contact hole in the insulating film and exposing the conductive material at the bottom of the contact hole; And a step of forming a wiring material made of aluminum or composed mainly of aluminum, which is in electrical contact with the conductive material at least at the bottom of the contact hole, and an element belonging to groups 12 to 15 of the periodic table on the surface of the wiring material. And a step of fluidizing the wiring material by a heat treatment and a step of forming a film containing the main component, wherein the heat treatment is performed at a temperature of 400 ° C. or lower in a hydrogen-containing atmosphere. Is provided.

In the present invention, the fluidization temperature of the wiring material is lowered by adding an element belonging to Groups 12 to 15 to the wiring material mainly made of aluminum (Al) or aluminum, and the wiring material is fluidized by heat treatment. It is a technique for improving the coverage for the contact hole by making it (hereinafter, referred to as a "reflow technique").

The most important feature is that the reflow step can be performed at a temperature of 450 ° C. or lower, preferably 400 ° C. or lower (typically 350 to 400 ° C.) by performing the heat treatment in a hydrogen containing atmosphere. In addition, the inventors anticipate that reflow can be performed at temperatures lower than 350 ° C by optimizing the conditions.

The temperature of 350 ° C is a temperature frequently used for hydrogenation, and this temperature is recognized as a temperature that does not generate hillock in the aluminum wiring. Moreover, the temperature below 400 degreeC is very important in reducing or preventing the thermal deterioration of the wiring or insulating film (for example, organic resin film) formed in another layer.

Further, according to the configuration of the present invention, a good ohmic contact can be ensured by having a structure in which a conductive film such as a titanium (Ti) film is sandwiched between a material made of aluminum or mainly composed of aluminum and a conductive material.

In addition, as the conductive material, a material composed of aluminum or containing aluminum as a main component (for example, a material for forming wiring or the like) or a semiconductor material having conductivity (for example, a semiconductor for forming a source / drain region of a transistor) Material) is representatively pointed out. Of course, metals such as tantalum and tungsten, titanium silicide, and the like are also included in the conductive material.

In addition, elements belonging to Groups 12 to 15 used as catalysts in the reflow process include germanium (Ge), tin (Sn), gallium (Ga), lead (Pb), zinc (Zn), indium (In), and One or more kinds of elements selected from the group consisting of antimony (Sb) are effective.

A contact hole is formed with respect to the insulating film formed on the conductive material, and a titanium film is formed so as to cover the contact hole. Then, a wiring material made of aluminum or containing aluminum as its main component is laminated on the titanium film.

In addition, after the wiring material is formed, a film mainly containing an element belonging to Groups 12 to 15 is preferably laminated without exposure to the atmosphere.

Then, the wiring material is fluidized (reflowed) by performing heat treatment at 400 ° C (typically 350 to 400 ° C) for 0.5 to 2 hours in a hydrogen-containing atmosphere. Since the fluidized wiring material flows into the contact hole to cover the contact hole, even if a disconnection defect or the like is caused during film formation, the defect can be improved by the reflow process.

Example 1

In the present Example, the effect of the reflow process by this invention is shown based on the experiment result. 1 (A) and 1 (B) are photographs showing the inner cross section of the contact hole, wherein the inner diameter of the contact hole is about 2 mu m, and the thickness of the interlayer insulating film is about 0.8 mu m. In addition, the wiring structure embedded in the contact hole is composed of layers of Ti (1000 mW) / Al-Si (5000 mW) / Sn (50 mW) sequentially from the lower layer.

The thick formation of the wiring material (Al-Si) is intended to produce a sample that can more clearly check the reflow effect. In addition, formation of the three-layered wiring is performed continuously using the multi-chamber sputtering apparatus shown to FIG. 5 (A) and FIG. 5 (B).

After the wiring structure having the above structure was formed, a heat treatment was performed at 400 ° C. for 2 hours according to the present invention, followed by a reflow treatment. 1 (A) and 1 (B) show a cross section of a contact hole with a scanning electron microscope (SEM) with respect to a substrate under the following conditions.

(a) Initial state before reflow process

(b) State after reflow process at 400 ° C. for 2 hours in 100% hydrogen atmosphere

First, FIG. 1 (A) shows the cross section of the contact hole in the initial state before the reflow process, and in this state, the disconnection failure of the wiring material is confirmed at the bottom of the contact hole (area close to the sidewall of the contact hole).

Next, FIG. 1 (B) shows the cross section of the contact hole after performing the reflow process of 400 degreeC and 2 hours in 100% hydrogen atmosphere. As apparent from Fig. 1B, the wiring shape becomes uniform and smooth, and it can be confirmed that the contact state of the wiring material in the contact hole is very good.

As mentioned above, comparing FIG. 1 (A) and FIG. 1 (B) shows that the reflow process of the present invention is an obviously effective technique for improving the disconnection failure of the wiring inside the contact hole. In addition, the fact that the reflow process can be performed at a temperature of 400 ° C has a very important meaning in widening the selection range of the insulating film that can be used for the multilayer wiring structure.

In addition, although the reason for promoting fluidization of the wiring when the reflow process is performed in a hydrogen atmosphere is not clearly known, the inventors have found that the natural oxide formed on the surface of the wiring (or the film constituting the catalyst) is reduced by the hydrogen reduction effect. It is expected that this is because it is removed to a degree that does not prevent fluidization of the wiring material.

Example 2

In this embodiment, an example of forming a wiring electrode of a thin film transistor TFT using the reflow technique according to the present invention is shown. It demonstrates based on FIG.2 (A)-FIG.2 (D).

In Fig. 2A, reference numeral 201 denotes a substrate having an insulating surface. In this embodiment, a silicon oxide film deposited on the glass substrate is used. The active layer 202 obtained by patterning the crystalline silicon film is disposed thereon. The crystalline silicon film may be formed directly or may be formed by crystallizing the amorphous silicon film.

Reference numeral 203 denotes a gate insulating film made of a silicon oxide film, and 204 denotes a gate electrode mainly composed of aluminum. Reference numeral 205 denotes an anodization film obtained by anodizing the gate electrode 204 to protect the gate electrode 204.

After the state of FIG. 2A is obtained, impurity ions (phosphorus or boron) which impart one conductivity are added to the active layer 202 in two steps. By these processes, the source region 206, the drain region 207, the low concentration impurity regions 208 and 209, and the channel formation region 210 are formed. In particular, the low concentration impurity region 209 is called an LDD (low concentration doped drain) region.

The technique described in Japanese Patent Application Laid-open No. Hei 7-135318 of the present applicant is used in the above manufacturing processes. For a detailed description thereof, see the above publication.

Next, as the interlayer insulating film 211, a transparent organic resin material (polyimide in this embodiment) is formed to a thickness of 1 탆. By using polyimide as an interlayer insulating film, a level difference, such as wiring, is absorbed and a favorable flat surface is obtained. Therefore, when the wiring material is reflowed in a later step, the film thickness does not become very thin at the stepped portion. Moreover, since a reflow process is performed at the temperature of 400 degrees C or less, polyimide does not deteriorate.

In addition, a silicon nitride film or a silicon oxide film may be used as the interlayer insulating film 211. In this case, as the film forming method, plasma CVD (chemical vapor deposition) method or reduced pressure thermal CVD method may be used. In the case where a silicon nitride film is used, it is preferable to form a thin silicon oxide film on the lowermost layer so as to form an etching stopper in forming a contact hole in a later step.

After the interlayer insulating film 211 is formed, a contact hole 212 is formed. In this embodiment, contact holes were formed by dry etching. Etching by the dry etching method is an indispensable technique for miniaturization because it is possible to form contact holes having a high aspect ratio.

By the above processes, the state shown in FIG. 2 (B) is obtained. After the state of FIG. 2B is obtained, a titanium film 213 is formed on the interlayer insulating film 211 to a thickness of 500 to 1000 GPa. This titanium film 213 has the effect of improving the ohmic contact between the TFT and the wiring electrode.

On it, a wiring material (alloy containing aluminum, scandium, silicon, copper, and the like) 214 having a main component of aluminum is formed to a thickness of 3000 kPa. Then, a metal film 215 composed of elements belonging to Groups 12 to 15 required in a subsequent reflow step is formed to a thickness of 50 to 100 mm 3. It is preferable that this laminated film is formed continuously. In addition, it is preferable to use CVD method or PVD (physical vapor deposition) method as a film-forming method.

Further, in order to effectively carry out the subsequent reflow process, the oxygen concentration in the wiring material 214 is 5 × 10 ¹⁹ atoms / cm ³ or less, preferably 1 × 10 ¹⁹ atoms / cm ³ or less (more preferably, 3 X 10 ¹⁸ atoms / cm ³ or less). This oxygen concentration is a value defined as the minimum value of the measurement value of SIMS (secondary ion mass spectrometry).

In the reflow process, since the oxide on the aluminum surface becomes a factor that hinders fluidization, the fluidization of the wiring material may be hindered by the presence of oxygen. Therefore, it is desirable to reduce the oxygen contained in the wiring material as much as possible. For this purpose, it is preferable to perform the film formation of the wiring material 214 in a chamber cleaned with ultra-high vacuum.

In addition, the elements constituting the metal film 215 include a group consisting of germanium (Ge), tin (Sn), gallium (Ga), zinc (Zn), lead (Pb), indium (In), and antimony (Sb). One or more kinds of elements selected from can be used. According to binary phase diagrams of alloys containing these elements and aluminum, it has been found that these elements function as catalyst elements for lowering the melting point (strictly fluidization temperature) of aluminum. In addition, the metal film 215 need not be composed of a single layer, and may have the form of a laminated film of germanium and tin, for example.

The state at the time of forming the laminated | multilayer film of the above structure is shown in FIG.2 (C). At this time, as shown in Fig. 2C, since the aspect ratio of the contact hole 212 is high, it is difficult to form the wiring material inside the contact hole (particularly, the side wall). Therefore, there is a high probability that disconnection failure occurs at the bottom of the contact hole.

Therefore, in this state, a reflow process for providing fluidity to the wiring material is performed. It is a feature of the present invention to perform the reflow step in a hydrogen atmosphere. In addition, the processing temperature of a reflow process is 400 degrees C or less (typically 350-400 degreeC), and a processing time is 0.5 to 2 hours. In this embodiment, the reflow step is performed by heat treatment at 400 ° C. for 1 hour in a hydrogen atmosphere.

Fluidity is provided to the wiring material 214 by the reflow process, and the wiring material 214 can effectively cover the inside of the contact hole. As a result, the wiring material 214 is formed on the side surface of the contact hole 212 with a sufficient film thickness, and the disconnection failure at the bottom is improved.

In addition, since the reflow process according to the present invention is performed at a temperature of 400 ° C. or less, generation of hillocks or whiskers on the surface of the wiring material mainly composed of aluminum can be suppressed. In addition, in the reflow process, the effect of hydrogenating the active layer can also be expected.

The wiring material obtained by the above reflow process is patterned to form the source wiring 216, the drain wiring 217, and the gate wiring 218. Then, by hydrogenating the whole, a TFT having the structure shown in Fig. 2D is obtained.

In the present embodiment, a planar TFT manufacturing method has been described, but the present invention can be implemented irrespective of the structure of the TFT. That is, the structure of the TFT is not limited to the structure shown in Fig. 2D, and for example, the present invention also applies to a structure such as having a reverse staggered TFT or a salicide structure. It can be easily adapted to your needs.

The TFT formed using the present invention significantly reduces the possibility of contact failure and realizes a very reliable operation. Further, by using the present invention, the production yield of TFTs is greatly improved, and the economic advantages are enormous.

Example 3

This embodiment shows an example in which the present invention is applied to a semiconductor device having a multilayer wiring structure. As an example thereof, FIG. 3 shows a structure in the case of using a transparent organic resin material as the interlayer insulating film.

3 shows a CMOS (complementary metal oxide semiconductor) circuit in which an N-channel TFT 301 and a P-channel TFT 302 formed on a glass substrate are complementarily combined. Since the manufacturing process of TFT is based on a well-known technique, the description is abbreviate | omitted here.

In FIG. 3, a first wiring 304 (including all wirings formed in the same layer) in direct contact with the TFTs 301 and 302 is formed on the first interlayer insulating film 303. First, the present invention can be used when the first wiring 304 is formed.

Next, a transparent organic resin material is deposited thereon as a second interlayer insulating film 305, and a second wiring 306 is formed thereon. The present invention can also be applied to the second wiring 306. This is very important.

As a permeable organic resin material, polyimide, polyamide, polyimide amide, etc. are typical. When the permeable organic resin material is used as the interlayer insulating film, since the film can be formed by the spinning method, the film thickness can be easily increased, and the throughput can be improved. In addition, since the relative dielectric constant is low, parasitic capacitance between wirings can be reduced. However, due to the heat resistance of the permeable organic resin material, the maximum heating temperature after film formation needs to be limited to 450 ° C. or less (preferably 400 ° C. or less).

However, according to the present invention, since the wiring material can be reflowed at 400 ° C. or lower (typically 350 to 400 ° C.), the reflow step is performed without any problem even when a transparent organic resin material is used as the interlayer insulating film. Can be.

Therefore, in Fig. 3, the transparent organic resin material is also used as the third interlayer insulating film 307, on which the third wiring 308 is formed using the present invention, but the interlayer insulating film of the lower layer is deteriorated by heat treatment. It is possible to prevent it from becoming.

In this embodiment, a transparent organic resin material is used as the interlayer insulating film. However, the same applies to the case where a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like is used as the interlayer insulating film.

As described above, by using the present invention, it is possible to use a material having low heat resistance as the interlayer insulating film, so that the design margin in designing the device can be widened.

Example 4

The present invention is applicable to an IGFET (insulated gate type field effect transistor) formed on a single crystal silicon substrate. Moreover, this invention is applicable also to the SOI structure which uses single crystal silicon as an active layer.

4 shows an example in which a BiCMOS circuit is configured as a three-dimensional multilayer semiconductor device using an SOI structure. In this case, a CMOS circuit is shown in which the lower layer is composed of a bipolar transistor and the upper layer is composed of a semiconductor device having an SOI structure.

In Fig. 4, reference numeral 401 denotes a P-type silicon substrate, 402 denotes a buried N + region, 403 denotes a p well formed by epitaxial growth, and p well on buried N + region 402 The n well 404 is inverted to form N to function as a collector. Further, reference numeral 405 denotes a deep N + region constituting the lead electrode from the buried N + region 402. Reference numeral 406 denotes a field oxide film formed by a conventional selective oxidation method.

First, the p− region 407 serving as the active base is formed in the n well 404 constituting the bipolar transistor, and then the p + region 408 serving as the external base and the n + region 409 serving as the emitter region. ) Is placed.

The collector electrode 411, the base electrode 412, and the emitter electrode 413 are formed to form a bipolar transistor. The present invention can be applied to forming these electrodes.

On the bipolar transistor having the above-described configuration, a CMOS circuit having an SOI structure having a single crystal silicon layer obtained by using a wafer paste technique as an active layer is formed. The interlayer insulating film denoted by reference numeral 410 includes a contact surface (indicated by a dotted line). Here, detailed description of the CMOS circuit is omitted.

The BiCMOS structure can be realized by connecting the CMOS circuit and the bipolar transistor by the wirings 414 and 415. At this time, the present invention can be applied to the wirings 416 and 417 constituting the CMOS circuit and the wirings 414 and 415 for connecting the CMOS circuit and the bipolar transistor.

As described above, even in the case of configuring a three-dimensional integrated circuit using an SOI structure, a reflow process can be performed without deterioration of other wirings or interlayer insulating films, and highly reliable contacts can be realized. That is, the present invention is a very effective technique for manufacturing a semiconductor device having a three-dimensional structure.

Moreover, although the example which comprises a BiCMOS circuit was shown in this embodiment, this invention is applicable not only to a BiCMOS circuit but also to logic circuits, such as DRAM (dynamic random access memory) circuit and SRAM (static random access memory), and very much. Highly reliable VLSI circuits (ultra-scale semiconductor integrated circuits) or ULSI circuits (ultra-ultra-scale semiconductor integrated circuits) can be realized.

Example 5

It is also possible to use RTA (Rapid Heat Annealing) as the heat treatment for carrying out the reflow process according to the present invention.

RTA is an annealing method which irradiates a to-be-processed object with strong light, such as infrared rays and an ultraviolet-ray, by a lamp etc. The feature of this method is that the temperature increase rate and the temperature decrease rate are fast, and the processing time is short, from a few seconds to several tens of seconds, so that only the thin film on the uppermost surface can be heated substantially. That is, for example, only the thin film on a glass substrate can be annealed at the very high temperature of about 1000 degreeC.

Application of the RTA technique described in this embodiment enables the heat treatment at a temperature exceeding the heat resistance of the gate electrode, and thus the allowable range of the reflow temperature is widened. Therefore, the selection range of the metal element used in the reflow process can be widened.

In addition, since the RTA process can be executed in a very short time of a few seconds to several tens of seconds, it is also a very effective means in terms of productivity.

Example 6

The present invention has the most important feature in carrying out the reflow process in a hydrogen atmosphere, and hydrogen is present in the molecular state or the atomic state in carrying out the usual heat treatment. In this embodiment, an example of using hydrogen radicals or hydrogen ions in the reflow process is shown.

For this purpose, a plasma is generated in a hydrogen atmosphere, and a reflow step is performed in an atmosphere in which hydrogen is excited. By using hydrogen radicalized or ionized and in the activated state in the reflow process, the efficiency of the reflow process can be improved.

In addition, this embodiment may be combined with the RTA technique described in the fifth embodiment. Thus, further improvement in throughput can be expected.

Example 7

In this embodiment, a film forming apparatus having a multi-chamber (cluster tool) structure having the configuration shown in Figs. 5A and 5B in forming the laminated film constituting the wiring electrode described in the first or second embodiment. The example which uses is shown.

The film forming apparatus of the multi-chamber structure shown in FIGS. 5A and 5B is one example of a sputtering apparatus capable of successively stacking thin films having different compositions (including cases of different elements) in each reaction chamber. to be.

Here, the simple structure of the sputtering apparatus shown to FIG. 5 (A) is demonstrated. Reference numeral 10 denotes a substrate to be processed, 11 denotes a common seal constituting the apparatus main body, and 12 denotes a transfer mechanism for transferring the substrate 10. The board | substrate 10 is carried in and out from the load lock chamber 13 and 14 attached to the apparatus main body 11. As shown in FIG. Reference numerals 15 and 16 denote substrate transfer cassettes provided in the load lock chambers 13 and 14. In addition, the load lock seals 13, 14 may be hermetically shielded from the common seal 11 by the gate valves 17, 18.

The first reaction chamber 19, the second reaction chamber 20, and the third reaction chamber 21 are connected to the common chamber 11, and each of the first to third reaction chambers is a gate valve 22, 23. , 24 can be hermetically shielded from the common seal 11. Further, in each of the first to third reaction chambers, a vacuum exhaust pump (not shown) capable of reducing the pressure to ultra high vacuum (1 × 10 ^-8 Torr or less, preferably 1 × 10 ^-9 Torr or less) is provided. ) Is provided.

Reference numeral 25 denotes a heating chamber which is a chamber for performing heat treatment in the reflow step. It is preferable that this heating chamber 25 is made into the structure which can perform an RTA process in consideration of throughput. Of course, the configuration may be provided with a plasma generating mechanism for generating the hydrogen radicals described in the fifth embodiment. In addition, the heating chamber 25 may also be hermetically shielded from the common chamber 11 by the gate valve 26.

FIG. 5B shows the outline of a cross section of the sputtering apparatus shown in FIG. 5A taken along a dotted line. In addition, since the schematic diagram shown in FIG. 5A is explained in more detail, although the cross section of FIG. 5B does not necessarily correspond with the cross section of FIG. 5A, it is basically a description of the same sputtering apparatus.

The conveyance mechanism 12 arrange | positioned in the common chamber 11 can move up, down, left, and right, and conveys the board | substrate 10 to reaction chamber 19-21 or the heating chamber 25. As shown in FIG. It should be noted here that the conveyance mechanism 12 is in a face down manner in which the substrate 10 is always conveyed with its main surface (device formation surface) facing downward. This approach is desirable to reduce the adhesion of dust to the substrate 10. Of course, a face up manner of facing the major surface of the substrate up may also be used.

The reaction chamber 21 is composed of a target support 31, a target 32, a shutter 33, and a substrate holder 34. Since the substrate holder 34 adopts a face down method, it is designed to support only a few millimeters of the end of the substrate 10, so that the surface of the substrate is not contaminated. In addition, a face up method, a method of vertically disposing a substrate, and the like may be used.

The heating chamber 25 is comprised from the board | substrate holder 35 and the heating lamps 36 and 37. FIG. This substrate holder 35 also employs a face down method. In addition, heating can be performed from both sides of the substrate 10 by the pair of heat lamps 36 and 37. In the case of this apparatus, the heating lamp 37 comprises the main lamp which heats the main surface side of a board | substrate. Of course, a face up method or the like may be used.

Next, an example of forming a laminated structure of thin films of different compositions using the sputtering apparatus configured as described above will be described.

For example, an Al (or Al-Si, Al-Si-Cu, etc.) target is installed in the first reaction chamber 19, and a Ge (or Sn, Ga, etc.) target is installed in the second reaction chamber 20. In the third reaction chamber 21, a Ti (or TiN or the like) target is provided. Subsequently, a film is formed using each target continuously without exposure to the atmosphere, whereby a Ti-Al-Ge laminated structure, a Ti-Al-Ge-Ti laminated structure, or the like can be obtained.

In addition, it is free of an operator to increase or decrease the number of reaction chambers as needed, for example, Ti-Al-Ge-Sn laminated structure etc. can also be obtained by configuring the apparatus which has a 1st-4th reaction chamber.

In the reflow process, the surface shape and surface state of the metal thin film subjected to the reflow process are important factors influencing the reflow process. For example, in the air, a natural oxide is immediately formed on the surface of a thin film mainly composed of aluminum, and the natural oxide is a factor that hinders the reflow process. Moreover, since natural oxide is insulating, it inhibits ohmic contact with another conductive thin film.

However, in the present embodiment, the above-described problems do not occur because metal thin films having different compositions can be laminated without exposure to the atmosphere. In particular, since the aluminum surface is susceptible to oxidation, the effect of this embodiment in which a metal thin film can be laminated without exposure to the atmosphere is very effective.

Example 8

The present invention is applicable to all semiconductor devices requiring a wiring structure. Therefore, the present invention can be applied not only to insulated gate transistors, but also to semiconductor devices such as thin film diodes, bipolar transistors, thyristors, and electrostatic induction transistors.

Incidentally, the semiconductor device in the present specification refers to an overall device functioning using a semiconductor, and includes a transmissive or reflective electro-optical device (liquid crystal display device, EL display device, EC display device, etc.) composed of various semiconductor devices described above, and Applications in which such electro-optical devices are installed are also included in their scope.

In this embodiment, the application will be described based on the illustrated example. Examples of the semiconductor device using the present invention include a TV camera, a head mounted display device, a car navigation system, a projection system (the front type and the rear type), a video camera, a personal computer, and the like. A brief description will be given with reference to Figs. 6A to 6F.

Fig. 6A shows a mobile computer composed of a main body 2001, a camera portion 2002, an image receiving portion 2003, an operation switch 2004, and a display device 2005. Figs. The present invention is applied to the display device 2005 and the integrated circuit 2006 installed inside the device.

Fig. 6B shows a head mounted display device composed of a main body 2101, a display device 2102, and a band portion 2103. Figs. Two display apparatuses 2102 of relatively small size are used.

FIG. 6C shows an automobile navigation system composed of a main body 2201, a display device 2202, an operation switch 2203, and an antenna 2204. The present invention can be applied to the display device 2202 and an integrated circuit inside the device. The display device 2202 is used as a monitor, and the allowable range of resolution is relatively wide because the main purpose of the device is to display a map.

FIG. 6D shows a cellular phone composed of a main body 2301, an audio output unit 2302, an audio input unit 2303, a display device 2304, an operation switch 2305, and an antenna 2306. The present invention is applicable to the display device 2304 and the integrated circuit inside the device.

FIG. 6E shows a video camera composed of a main body 2401, a display device 2402, an audio input unit 2403, an operation switch 2404, a battery 2405, and a water receiving unit 2406. The present invention is applicable to the display device 2402 and an integrated circuit inside the device.

6F illustrates a front projection system consisting of a main body 2501, a light source 2502, a reflective display device 2503, an optical system (including a beam splitter, a polarizer, etc.) 2504, and a screen 2503. Indicates. Since the screen 2505 is a large screen used for presentations in conferences and conference presentations, the display device 2503 is required to have high resolution.

In addition to the electro-optical device shown in this embodiment, the present invention is also applicable to portable information terminal devices such as a rear projection system or a handy terminal. As described above, the application range of the present invention is very wide, and the present invention can be applied to display media of all fields.

In forming a contact on a wiring electrode mainly composed of aluminum, a reliable contact can be formed by the action of the element by performing a reflow step using an element belonging to Groups 12 to 15. As a result, good contacts can be achieved in semiconductor devices of all structures, and the reliability of semiconductor devices can be greatly improved.

Also, in this case, since the reflow process can be carried out at a low temperature of 400 ° C. or lower, typically 350 to 400 ° C., thermal degradation of the wiring and the insulating film of the other layers caused by the reflow process can be prevented. have. In addition, in manufacturing a semiconductor device having a multilayer wiring structure, the selection range of the insulating film material to be used can be widened.

1 (A) and 1 (B) are photographs for explaining the cross-sectional shape of the thin film.

2A to 2D are diagrams illustrating a semiconductor device fabrication process.

3 shows the structure of a semiconductor device;

4 is a diagram showing the structure of a semiconductor device.

5A and 5B show a multi-chamber film forming apparatus.

6A to 6F are diagrams illustrating a semiconductor device as an application product.

* Explanation of symbols for the main parts of the drawings

206: source region 207: drain region 211: interlayer insulating film

212: contact hole 213: titanium film 214: aluminum film

215: germanium films 216, 217, 218: wiring electrodes

Claims (60)

delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete Forming at least one transistor having a conductive material on a semiconductor substrate having an SOI structure; Forming an insulating film on the semiconductor substrate; Forming at least one contact hole through the insulating film to expose the conductive material at the bottom of the contact hole; Forming a wiring material in electrical contact with the conductive material at least at the bottom of the contact hole; Forming a film including an element selected from the group consisting of Group 12 to Group 15 elements on the wiring material; And And fluidizing at least the wiring material by heat treatment at a temperature of 400 ° C. or lower. Forming at least one transistor on the semiconductor substrate having the SOI structure, the conductive materials having at least one silicide material; Forming an insulating film on the semiconductor substrate; Forming at least one contact hole through the insulating film to expose the conductive material at the bottom of the contact hole; Forming a wiring material in electrical contact with the conductive material at least at the bottom of the contact hole; Forming a film including an element selected from the group consisting of Group 12 to Group 15 elements on the wiring material; And And at least said wiring material is fluidized by heat treatment. Forming at least one transistor having a conductive material on the semiconductor substrate; Forming a first insulating film on the semiconductor substrate; Forming a semiconductor layer on the first insulating film to form an SOI structure; Forming a CMOS circuit on the first insulating film; Forming a second insulating film over the CMOS circuit; Forming at least one contact hole through the first and second insulating films to expose the conductive material at the bottom of the contact hole; Forming a wiring material in electrical contact with the conductive material at least at the bottom of the contact hole; Forming a film including an element selected from the group consisting of Group 12 to Group 15 elements on the wiring material; And And fluidizing at least the wiring material by heat treatment at a temperature of 400 ° C. or lower. Forming at least one transistor on the semiconductor substrate, the conductive materials having at least one silicide material; Forming a first insulating film on the semiconductor substrate; Forming a semiconductor layer on the first insulating film to form an SOI structure; Forming a CMOS circuit on the first insulating film; Forming a second insulating film over the CMOS circuit; Forming at least one contact hole through the first and second insulating films to expose the conductive material at the bottom of the contact hole; Forming a wiring material in electrical contact with the conductive material at least at the bottom of the contact hole; Forming a film including an element selected from the group consisting of Group 12 to Group 15 elements on the wiring material; And And at least said wiring material is fluidized by heat treatment. delete Forming at least one transistor on the semiconductor substrate having the SOI structure, the conductive materials having at least one silicide material; Forming an insulating film on the semiconductor substrate; Forming at least one contact hole through the insulating film to expose the conductive material at the bottom of the contact hole; Forming a wiring material in electrical contact with the conductive material at least at the bottom of the contact hole; Forming a film including an element selected from the group consisting of Group 12 to Group 15 elements on the wiring material; And And fluidizing at least the wiring material by heat treatment at a temperature of 400 ° C. or lower. 32. The method of claim 31 wherein the SOI structure comprises single crystal silicon. 32. The method of claim 31, wherein the conductive material is at least one of aluminum and a conductive semiconductor material. 32. The method of claim 31, wherein the silicide material comprises at least one selected from the group consisting of tantalum silicide, tungsten silicide, and titanium silicide. 32. The method of claim 31, wherein the wiring material comprises aluminum. 32. The method of claim 31, wherein said Group 12-15 elements comprise at least one selected from the group consisting of Ge, Sn, Ga, Pb, Zn, In, Sb. 32. A method according to claim 31, wherein the semiconductor device is an EL display device. 32. The method of claim 31, wherein the semiconductor device is at least one electronic device selected from the group consisting of a mobile computer, a head mounted display, a car navigation system, a mobile phone, a video camera, and a projector. . Forming at least one transistor on the semiconductor substrate, the conductive materials having at least one silicide material; Forming a first insulating film on the semiconductor substrate; Forming a semiconductor layer on the first insulating film to form an SOI structure; Forming a CMOS circuit on the first insulating film; Forming a second insulating film over the CMOS circuit; Forming at least one contact hole through the first and second insulating films to expose the conductive material at the bottom of the contact hole; Forming a wiring material in electrical contact with the conductive material at least at the bottom of the contact hole; Forming a film including an element selected from the group consisting of Group 12 to Group 15 elements on the wiring material; And And fluidizing at least the wiring material by heat treatment at a temperature of 400 ° C. or lower. 40. A method according to any one of claims 26 to 29 and 39, wherein said SOI structure comprises single crystal silicon. A method according to any one of claims 26 to 29 and 39, wherein the conductive material is at least one of aluminum and a conductive semiconductor material. 40. A method according to any one of claims 27, 29 and 39, wherein said silicide material comprises at least one selected from the group consisting of tantalum silicide, tungsten silicide and titanium silicide. A method according to any one of claims 26 to 29 and 39, wherein the wiring material comprises aluminum. The method according to any one of claims 26 to 29 and 39, wherein the group 12 to 15 elements include at least one selected from the group consisting of Ge, Sn, Ga, Pb, Zn, In, Sb. A semiconductor device manufacturing method characterized in that. A method according to any one of claims 26 to 29 and 39, wherein the semiconductor device is an EL display device. 40. The semiconductor device according to any one of claims 26 to 29 and 39, wherein the semiconductor device is at least one selected from the group consisting of a mobile computer, a head mounted display, a car navigation system, a mobile phone, a video camera, and a projector. A semiconductor device manufacturing method characterized in that the electronic device. delete Forming at least one transistor on the semiconductor substrate; Forming a first insulating film on the semiconductor substrate; Forming a thin film transistor on the first insulating film; Forming a second insulating film on the thin film transistor; Forming at least one contact hole through the first and second insulating films; Forming a wiring material including aluminum on the second insulating film and in the contact hole; Forming a film comprising an element selected from the group consisting of Group 12 to Group 15 elements in contact with the wiring material; And Heating the wiring material and the film to fluidize the wiring material; And the wiring material is electrically connected to the transistor through the contact hole. 49. A method according to any one of claims 26 to 29, 31, 39, and 48, wherein said transistor is a bipolar transistor. 49. The method of any one of claims 28, 29, 39, and 48, further comprising forming another insulating film and another wiring material between the first insulating film and the semiconductor substrate. A semiconductor device manufacturing method. 49. The method of manufacturing a semiconductor device according to any one of claims 27, 29, and 48, wherein said heating is performed at a temperature of 400 deg. The semiconductor device manufacturing method according to any one of claims 26 to 29, 31, 39, and 48, wherein the heating is performed at a temperature of 350 ° C or lower. The semiconductor device manufacturing method according to any one of claims 26 to 29, 31, 39, and 48, wherein the heating is performed in an atmosphere containing hydrogen. 32. The method of manufacturing a semiconductor device according to any one of claims 26, 27, and 31, further comprising forming another film containing titanium between the insulating film and the wiring material. 49. The method of any one of claims 28, 29, 39, and 48, further comprising forming another film containing titanium between the second insulating film and the wiring material. A semiconductor device manufacturing method. The semiconductor device manufacturing method according to any one of claims 26 to 29, 31, 39, and 48, wherein an oxygen concentration in the wiring material is 5 x 10 ¹⁹ atoms / cm ³ or less. . A method according to claim 48, wherein said semiconductor device is an EL display device. 49. The method of claim 48, wherein the semiconductor device is at least one electronic device selected from the group consisting of a mobile computer, a head mounted display, a car navigation system, a mobile phone, a video camera, and a projector. . 49. The method of claim 48, wherein said semiconductor substrate comprises single crystal silicon. 49. The method of claim 48, wherein said Group 12-15 elements comprise at least one selected from the group consisting of Ge, Sn, Ga, Pb, Zn, In, Sb.