JP2005038994A - Thin film transistor, manufacturing method therefor, display device equipped therewith and manufacturing method of display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that a large substrate has much flatness and removal/discard amounts of wiring materials due to polishing and it is not suitable although a damascene method is used in wiring using copper and in formation of an electrode. <P>SOLUTION: A non-electrolytic plating method (or electroplating) is used on a metal diffusion prevention base layer 6 arranged on a semiconductor layer 3, and a gate electrode formed of a metal layer (or lamination of a metal seed layer 31 and a metal layer 8) 8 is selectively formed. Impurity of low concentration is doped with the metal layer 8 as a mask. A first metal diffusion prevention cover layer 9 by the non-electrolytic plating method is selectively formed so that it covers the metal layer 8. Impurity of high concentration is doped with the first metal diffusion prevention cover layer 9 as the mask. In a thin film transistor, source/drain regions 3b having low concentration and high concentration are arranged. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a thin film transistor having a lightly doped drain (LDD) region used in a display device typified by a liquid crystal display device or an electroluminescence (EL) device, a manufacturing method thereof, a display device including the thin film transistor, and The present invention relates to a method for manufacturing the display device.
[0002]
[Prior art]
In general, a thin film transistor (TFT) can be provided over a transparent glass substrate, and thus is used in a display device such as an active matrix liquid crystal display device or an active matrix EL display device. When this TFT is applied to an n-type TFT which is a pixel switching element of an active matrix liquid crystal display device, a gate voltage of about 15 to 20 V is applied, and it is particularly necessary to reduce the leakage current in the off region. ing. On the other hand, the peripheral drive circuit provided for driving the pixel switching element is basically composed of a CMOS circuit, and the on-region characteristics are mainly important.
[0003]
However, TFTs using polycrystalline silicon have a large off-region leakage current in the initial characteristics, and therefore, when driven for a long time, the on-current decreases and a deterioration phenomenon occurs in which the off-current increases. One of the causes is considered to be a hot carrier injection phenomenon caused by a high electric field near the drain.
[0004]
In the technical field of semiconductor integrated circuits, a lightly doped drain (LDD) structure is known as a method for reducing the off-current of a MOS transistor and further mitigating a high electric field near the drain. In the prior art, a low concentration impurity region to be an LDD region is formed by a first impurity element implantation process using a gate electrode as a mask, and then a second impurity element implantation process is performed using a resist mask. A method of forming a high concentration impurity region to be a source region and a drain region is used.
[0005]
However, although this LDD structure can reduce the off-current compared to a TFT having a normal structure, the series resistance component is structurally increased, resulting in a decrease in the on-current of the TFT. In addition, a structure in which the LDD region overlaps with the gate electrode is known as a structure that suppresses deterioration of on-current and compensates for the above-described drawbacks.
[0006]
There are several methods for forming this structure. For example, GOLD (Gate-drain Overlapped LDD) and LATID (Large-tilt-angle implanted drain) are known. By adopting such a structure, it is known that the high electric field in the vicinity of the drain is relaxed, the hot carrier resistance is enhanced, and at the same time, the decrease in the on-current is prevented.
[0007]
In addition, as a metal material such as wiring and electrodes in the field of semiconductors represented by ULSI, due to the progress of miniaturization due to the improvement of the degree of integration and the improvement of the operation speed, the conventional aluminum (Al) is used. However, studies are being made on wiring using copper (Cu), which has low wiring resistance and high resistance to electromigration and stress migration.
[0008]
Also in the field of display devices such as liquid crystal display devices, monolithic peripheral circuit parts by increasing the wiring length due to the expansion of the display area and incorporating various additional functions such as driver circuits for drivers and in-pixel memories. The demand for low resistance wiring, like the semiconductor field, has been increasing due to demands such as downsizing. As described above, copper as a metal material is excellent in low resistance and migration resistance as compared to Al, which is a conventional metal material. Has been.
[0009]
However, conventionally, when trying to form a fine wiring using copper by a combination of photolithography technique masking and reactive ion etching (Reactive Ion Etching) method as used for forming fine wiring, Since the copper halide has a low vapor pressure (that is, it is difficult to evaporate), in order to volatilize and remove the halide formed by the etching, an etching process at 200 to 300 ° C. is required as a process temperature. For this reason, it is difficult to finely process the copper wiring by etching.
[0010]
For this reason, in the field of semiconductor technology, a so-called damascene method disclosed in, for example, Patent Document 1 and Patent Document 2 is used as a method for forming fine wiring using copper. In this damascene method, first, a wiring groove having a desired wiring pattern shape is formed in advance on an insulating layer on a substrate, and PVD (Physical Vapor Deposition) such as sputtering, plating method or A thin copper layer is embedded in the groove and formed over the entire surface of the insulating layer by various methods such as CVD using an organometallic material. Thereafter, the copper thin layer is removed by using a polishing method such as chemical mechanical polishing (CMP) or etch back to the upper end face of the groove in which the copper thin layer is embedded. A buried copper wiring pattern is formed only in the groove.
[0011]
[Patent Document 1]
JP 2001-189295 A
[0012]
[Patent Document 2]
Japanese Patent Laid-Open No. 11-135504
[0013]
[Problems to be solved by the invention]
The various forming methods conventionally used in Patent Documents 1 and 2 described above have the following problems.
LATID is achieved by ion implantation with oblique incidence, but is difficult with a non-mass-separated ion shower implanter for large substrates.
[0014]
In the GOLD structure, a first gate electrode layer is usually formed, and low-concentration impurity implantation is performed using the first gate electrode layer as a mask. After that, a second gate electrode layer is formed so as to cover the first gate electrode layer. The second gate electrode layer is formed as wide as desired on both sides of the gate length of the first gate electrode layer. Then, the second gate electrode layer is used as a mask to form a high concentration impurity. Although this formation method is easy in terms of process, the LDD length on the source side and the drain side is caused by the alignment accuracy of the exposure apparatus, the processing accuracy such as etching, etc. There are problems that the periphery is not uniform and the number of manufacturing processes is large compared to the center. As a method of forming a GOLD structure by self-alignment, a gate electrode having a two-layer structure of a polysilicon gate electrode film and an oxide film is formed on the gate insulating film, and low-concentration impurity implantation is performed, and then the gate electrode is formed. A polysilicon film is formed on the gate electrode and anisotropically etched to form sidewalls on both sides of the gate electrode. When a high concentration impurity is implanted into the source and drain portions, a high concentration impurity is also implanted into the sidewall portion. A method has been proposed. (“A Novel Self-aligned Gate-overlapped LDD Poly-Si TFT with High Reliability and Performance” Requires activation at a high temperature and it is difficult to reduce the resistance of the sidewall. Furthermore, it is difficult to apply to a gate electrode wiring made of copper.
[0015]
Therefore, the present invention uses a low-resistance metal made of copper or the like on a large-area substrate to reduce variation in LDD length and realize a reduction in manufacturing cost by reducing the number of manufacturing steps and a manufacturing method thereof Another object of the present invention is to provide a display device including the thin film transistor and a method for manufacturing the display device.
[0016]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a step of providing a semiconductor layer, a step of providing a gate insulating layer on the semiconductor layer, a step of providing a metal diffusion preventing underlayer on the gate insulating layer, and the metal diffusion. A step of providing a gate electrode made of a metal layer on the prevention underlayer; a step of etching the metal diffusion prevention underlayer using the metal layer as a mask; and a low-concentration impurity implantation into the semiconductor layer using the metal layer as a mask A step of providing a first metal diffusion prevention cover layer so as to cover the surface of the metal layer, and the semiconductor into which the low-concentration impurities are implanted using the first metal diffusion prevention cover layer as a mask Including a step of implanting a high concentration of impurities into the layer with a width corresponding to the thickness of the first metal diffusion prevention cover layer and a step of activating the semiconductor layer into which the impurities have been implanted. To provide a manufacturing method of a thin film transistor.
[0017]
The present invention further includes a step of providing a semiconductor layer, a step of providing a gate insulating layer on the semiconductor layer, a step of providing a metal diffusion preventing underlayer on the gate insulating layer, and a metal on the metal diffusion preventing underlayer. A step of providing a gate electrode comprising a layer, a step of providing a second metal diffusion prevention cover layer so as to cover the surface of the metal layer, and the metal diffusion prevention underlayer using the second metal diffusion prevention cover layer as a mask A step of performing low-concentration impurity implantation using the second metal diffusion prevention cover layer as a mask, and further providing a first metal diffusion prevention cover layer on the second metal diffusion prevention cover layer And using the first metal diffusion prevention cover layer as a mask, the semiconductor layer into which the low-concentration impurity is implanted has a width that is approximately the thickness of the first metal diffusion prevention cover layer and has a high concentration. Providing and performing impurity implantation, a method of manufacturing a thin film transistor comprising the step of activating a semiconductor layer in which the impurity is injected. Here, by forming the second metal diffusion prevention cover layer before the low-concentration impurity implantation step, it is possible to provide a method for manufacturing a thin film transistor capable of suppressing the surface oxidation of the metal layer and damage during ion implantation. .
[0018]
The present invention further includes a step of providing a semiconductor layer, a step of providing a gate insulating layer on the semiconductor layer, a step of providing a metal diffusion preventing underlayer on the gate insulating layer, and a metal on the metal diffusion preventing underlayer. A step of providing a gate electrode comprising a layer, a step of providing a second metal diffusion prevention cover layer so as to cover the surface of the metal layer, and the metal diffusion prevention underlayer using the second metal diffusion prevention cover layer as a mask A step of performing low-concentration impurity implantation using the second metal diffusion prevention cover layer as a mask, and further providing a first metal diffusion prevention cover layer on the second metal diffusion prevention cover layer And using the first metal diffusion prevention cover layer as a mask, the semiconductor layer into which the low-concentration impurity is implanted has a width that is approximately the thickness of the first metal diffusion prevention cover layer and has a high concentration. And a step of activating the semiconductor layer into which the impurity is implanted, and a step of etching the metal diffusion prevention base layer using the first metal diffusion prevention cover layer as a mask. A manufacturing method is provided. Here, by performing etching of the metal diffusion prevention underlayer after the high concentration impurity implantation, damage suppression of the gate insulating layer at the time of ion implantation, and good thermal uniformity and annealing treatment in the impurity activation process by the metal diffusion prevention underlayer In addition, it is possible to provide a method of manufacturing a thin film transistor that can be easily formed and can have a good gate electrode end face shape.
[0019]
The present invention further provides a method for manufacturing a thin film transistor, which includes a step of implanting the impurities before or after etching the metal diffusion prevention underlayer.
[0020]
The present invention further provides a method of manufacturing a thin film transistor including the step of performing the impurity implantation through the metal diffusion prevention underlayer.
[0021]
The present invention further provides a method of manufacturing a thin film transistor including a step of etching the metal diffusion prevention underlayer after the step of activating.
[0022]
According to the method of manufacturing a thin film transistor of the present invention having the above-described structure, a gate electrode made of a metal layer is selectively provided on the metal diffusion prevention base layer provided on the semiconductor layer by using an electroless plating method. A low concentration impurity is doped using the metal layer or the second metal diffusion prevention cover layer formed on the surface of the metal layer as a mask. Further, a first metal diffusion prevention cover layer is selectively provided by an electroless plating method so as to cover the metal layer, and a high concentration impurity is doped using the first metal diffusion prevention cover layer as a mask to reduce the concentration of the first metal diffusion prevention cover layer. A thin film transistor provided with a source / drain region having a high concentration impurity region is provided.
[0023]
In addition, according to the thin film transistor manufacturing method of the present invention, a gate electrode made of a metal layer is selectively provided on the metal diffusion prevention base layer provided on the semiconductor layer by using an electroless plating method, and further covers the metal layer. A second metal diffusion prevention cover layer is selectively provided by electroless plating. The metal diffusion prevention base layer is etched using the second metal diffusion prevention cover layer as a mask, and further, a low concentration impurity is doped using the second metal diffusion prevention layer as a mask, and the second metal diffusion prevention layer is formed. A first metal diffusion prevention cover layer is formed by electroless plating so as to cover. Using this first metal diffusion prevention cover layer as a mask, a high-concentration impurity is doped to provide a thin film transistor provided with source / drain regions having low-concentration and high-concentration impurity regions.
[0024]
In addition, according to the thin film transistor manufacturing method of the present invention, a gate electrode made of a metal layer is selectively provided on the metal diffusion prevention base layer provided on the semiconductor layer by using an electroless plating method, and further covers the metal layer. A second metal diffusion prevention cover layer is selectively provided by electroless plating. Further, a low concentration impurity is doped using the second metal diffusion prevention layer as a mask, and a first metal diffusion prevention cover layer is provided by an electroless plating method so as to cover the second metal diffusion prevention layer. After doping a high concentration impurity using the first metal diffusion prevention cover layer as a mask, the metal diffusion prevention base layer is etched using the first metal diffusion prevention cover layer as a mask to form low concentration and high concentration impurity regions. A thin film transistor provided with a source / drain region is provided.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1, FIG. 2 and FIG. 3 show a MOS structure n-channel TFT having a gate electrode using a copper layer and an LDD (Lightly Doped Drain) region as a first embodiment of the thin film transistor manufacturing method of the present invention. It is process drawing for demonstrating the formation method of a thin-film transistor.
[0026]
In the process shown in FIG. 1A, for example, silicon nitride (SiN) is used to prevent diffusion of impurities in a region where a TFT is formed on an insulating substrate 1 made of a transparent material such as glass, by using PE-CVD. A base insulating layer 2 having a layer thickness of about 300 nm is deposited. On the underlying insulating layer 2, a semiconductor layer that becomes an active layer, for example, an amorphous silicon layer 3 ′ having a thickness of, for example, 50 nm is deposited. Thereafter, the substrate 1 is annealed in an atmosphere at a temperature of, for example, 500 ° C. to desorb hydrogen from the amorphous silicon layer 3 ′. Further, the amorphous silicon layer 3 ′ is crystallized into the polysilicon layer 3 by an ELA (Excimer Laser Anneal) method. In this crystallization step, excimer laser light is diffracted and interfered by a phase shifter by a phase shifter to emit laser light having a reverse peak pattern, and the amorphous silicon layer 3 ′ is irradiated to crystallize the polysilicon layer 3. It is desirable.
[0027]
In the step shown in FIG. 1B, after forming a mask pattern made of a photosensitive resin, that is, a photoresist layer 4 by PEP (Photo Engraving Process), island-like polysilicon is formed by using CDE (Chemical Dry Etching) method. Layer 3 is formed.
In the step shown in FIG. 1C, a gate insulating layer 5 having a layer thickness of, for example, 50 nm is deposited on the substrate 1 including the polysilicon layer 3 by PE-CVD.
[0028]
In the step shown in FIG. 1D, after a copper diffusion preventing underlayer, for example, a copper diffusion preventing underlayer 6 having a layer thickness of, for example, about 50 nm made of titanium nitride (TiN) is formed on the gate insulating layer 5, A mask pattern of the photoresist layer 7 is formed on the copper diffusion preventing underlayer 6 using PEP. The groove 7a opened in the photoresist layer 7 selectively forms a wiring pattern, an electrode pattern, or the like. The formation of a wiring pattern, an electrode pattern, or the like is a process for saving resources of wiring and electrodes.
[0029]
In the step shown in FIG. 2A, a copper layer 8 having a layer thickness of 0.5 μm, for example, is selectively formed in the groove 7a by using an electroless plating method. As a pretreatment for electroless plating, it is desirable to form Pd nuclei or Cu nuclei having catalytic ability by a displacement plating method.
[0030]
In the step shown in FIG. 2B, after the copper layer 8 is formed, the photoresist layer 7 is removed, and then the copper diffusion preventing underlayer 6 is etched in a self-aligning manner using the copper layer 8 as a mask. Remove.
[0031]
In the step shown in FIG. 2C, an impurity such as arsenic for forming a source region and a drain region in the polysilicon layer 3 is formed using the copper layer 8 formed on the first copper diffusion preventing layer 6 as a mask. , Doping amount, eg 1 × 10 ¹³ atoms / cm ² Is implanted, for example, by ion doping to form a low concentration region (n ⁻ ) LDD region 3a.
[0032]
In the step shown in FIG. 3A, a copper diffusion prevention layer is formed on the copper layer 8, for example, by using an electroless plating method so that the surfaces of the copper layer 8 and the first copper diffusion prevention layer 6 are covered. A first copper diffusion prevention cover layer 9 is formed by depositing a layer thickness corresponding to the LDD length, for example, 0.5 μm.
[0033]
In the step shown in FIG. 3B, an impurity such as arsenic for forming the source region and the drain region at a high concentration is used, and a doping amount such as 4 × 10 is used with the second copper diffusion prevention layer 9 as a mask. ¹⁴ atoms / cm ² Is ion-doped into the copper layer 8 so that a high concentration region (n ⁺ ) Source / drain regions 3b.
In the step shown in FIG. 3C, the interlayer insulating layer 10 made of, for example, silicon oxide and having a layer thickness of, for example, 400 nm is formed using the PE-CVD method. Next, after the ion doping step, a step of activating the implanted impurities, for example, a heat treatment step by laser annealing, flash lamp annealing, rapid thermal annealing (RTA) or the like is performed. Further, a mask pattern is formed by the photoresist layer 11 on the interlayer insulating layer 10 and the interlayer insulating layer 10 is etched to contact holes so that the surface of the polysilicon layer 3 (source / drain region 3b) is exposed. 11a is formed.
In the step shown in FIG. 3D, the source / drain electrode 12 connected to the source / drain region 3b is formed by filling the contact hole 11a with a metal such as aluminum (Al).
[0034]
According to the first embodiment described above, the length of the low-concentration region 3a on the source side and the drain side is substantially equal to the layer thickness of the first copper diffusion prevention layer cover 9 by using the manufacturing process described above. A method of manufacturing a thin film transistor having a GOLD structure that can be configured equally, has a low-concentration region 3a having excellent uniformity in length, does not require PEP, and can be selectively formed. Can be provided.
[0035]
The copper diffusion preventing underlayer may be not only TiN described above but also TaN, TaSiN, TiSiN, WSiN, Ti, Ta, etc. having the ability to prevent copper diffusion, and may be a laminate of the above materials. Good. The copper diffusion prevention layer cover layer is preferably formed of a metal that can be formed on the surface of copper when selected by an electroless plating method. Examples of such a copper diffusion prevention layer cover layer include cobalt (Co) -tungsten (W) -boron (B) alloy, cobalt (Co) -boron (B) alloy, and cobalt (Co) -phosphorus (P) alloy. And nickel (Ni) -tungsten (W) -phosphorus (P) alloy. Here, cobalt-based alloys and nickel-based alloys are refractory metals, and in the wavelength region of excimer laser light used for impurity activation, the reflectance is lower than the silicon region into which impurities are implanted. Since it covers the surface including the copper wiring side surface, it has a high light absorption effect and also has an effect of suppressing junction defects that tend to occur at the end of the gate electrode.
[0036]
Next, a second embodiment will be described.
In the first embodiment described above, the copper diffusion prevention base layer 6 is etched using the formed copper wiring layer 8 as a mask. However, in this embodiment, after the copper wiring layer is formed, an electroless plating method is used. Then, a second copper diffusion prevention cover layer is formed, and then the copper diffusion prevention base layer is etched. Here, in the steps of the second embodiment, the steps equivalent to those of the first embodiment described with reference to FIGS. 1 to 3 will be described in a simplified manner. The layer thickness of each layer constituting the thin film transistor may be equal to the layer thickness of each layer in the first embodiment.
[0037]
In the step shown in FIG. 4A, the base insulating layer 12 made of silicon nitride (SiNx) is deposited on the substrate 11 made of glass or the like, similar to the steps in FIGS. 1A to 1C described above. Further, an amorphous silicon layer 13 ′ is deposited, hydrogen is desorbed by annealing, and then crystallized using an ELA method to form a polysilicon layer 13. Then, a polysilicon layer 13 is formed in an island shape by PEP and etching, and a gate insulating layer 14 is deposited on the substrate 11 including the polysilicon layer 13.
[0038]
The process shown in FIG. 4B is the same as the process shown in FIGS. 1D and 2A, and a copper diffusion prevention base layer 15 made of titanium nitride (TiN) or the like is formed on the gate insulating layer 14. After the layer formation, the copper wiring layer 17 is selectively formed in the groove 15a opened by the resist mask 16 made of PEP by using an electroless plating method. As a pretreatment for electroless plating, it is desirable to form Pd nuclei or Cu nuclei having catalytic ability by a displacement plating method.
[0039]
The process shown in FIG. 4C is the same as the process shown in FIG. 2B, and after removing the photoresist layer 16, an electroless plating method is used to cover the copper wiring layer 17. Two copper diffusion prevention cover layers 18 are formed.
[0040]
In the step shown in FIG. 4D, the copper diffusion prevention base layer 15 is etched and removed in a self-aligning manner using the second copper diffusion prevention cover layer as a mask.
In the step shown in FIG. 5A, the gate electrode covered with the second copper diffusion prevention cover layer 18 is formed.
As a mask, the polysilicon layer 13 is ion-doped with arsenic to form a low concentration impurity region (n ⁻ ) LDD portion 13a.
[0041]
In the step shown in FIG. 5B, an electroless plating method is used to further deposit a layer thickness corresponding to the LDD length on the second copper diffusion prevention layer 19 to form the first copper diffusion prevention layer 19. Form. Thereafter, arsenic is ion-doped again to form a high concentration impurity region (n ⁺ ) Source / drain electrodes 13b.
[0042]
In the step shown in FIG. 5C, after the interlayer insulating layer 20 made of silicon oxide or the like is formed by PE-CVD, an impurity activation step is performed, and a mask pattern is formed by a photoresist layer (not shown). Then, the interlayer insulating layer 20 is etched to form a contact hole so that the surface of the polysilicon layer 13 (source / drain region 13b) is exposed. The contact hole is filled with a metal such as aluminum (Al), for example, and a source / drain electrode 21 connected to the source / drain region 13b is formed.
[0043]
According to the second embodiment described above, the length of the low-concentration region 13a on the source side and the drain side is substantially equal to the layer thickness of the first copper diffusion prevention layer 19 as in the first embodiment described above. A method of manufacturing a thin film transistor having a GOLD structure that can be configured equally, has a low-concentration region 13a having excellent uniformity in length, does not require PEP, and can be selectively formed. Can be provided. In this case, the second copper diffusion prevention layer 19 is effective as a low-concentration impurity implantation step, an oxidation protection layer for the copper wiring layer, and an etching protection layer for the copper diffusion prevention base layer 15.
[0044]
Next, a third embodiment will be described.
In the second embodiment described above, the copper diffusion prevention base layer 15 is etched using the formed second copper diffusion prevention cover layer 18 as a mask. However, in this embodiment, the second copper diffusion prevention cover layer 18 A first copper diffusion prevention cover layer is formed later, ion doping is performed in a high concentration region, an annealing process for activation is performed, and then copper diffusion prevention is performed using the first copper diffusion prevention cover layer as a mask. Etching the underlayer. Here, in the steps of the third embodiment, the steps equivalent to those of the second embodiment described with reference to FIGS. 4 to 6 are simplified and described. The layer thickness of each layer constituting the thin film transistor may be equal to the layer thickness of each layer in the second embodiment.
[0045]
In the step shown in FIG. 10A, the base insulating layer 62 made of silicon nitride (SiNx) is deposited on the substrate 61 made of glass or the like, similar to the steps in FIGS. 4A to 4C described above. Further, an amorphous silicon layer 63 ′ is deposited, hydrogen is desorbed by annealing, and then crystallized using an ELA method to form a polysilicon layer 63. Then, the polysilicon layer 13 is formed in an island shape by PEP and etching, and a gate insulating layer 64 is deposited on the substrate 61 including the polysilicon layer 63.
[0046]
The process shown in FIG. 10B is the same as the process shown in FIGS. 4D and 2A, and a copper diffusion prevention base layer 65 made of titanium nitride (TiN) or the like is formed on the gate insulating layer 64. After the layer formation, a copper wiring layer 67 is selectively formed in the groove 65a opened by the resist mask 66 made of PEP by using an electroless plating method. As a pretreatment for electroless plating, it is desirable to form Pd nuclei or Cu nuclei having catalytic ability by a displacement plating method.
The process shown in FIG. 10C is the same as the process shown in FIG. 5B, and after removing the photoresist layer 66, an electroless plating method is used to cover the copper wiring layer 67. Two copper diffusion prevention cover layers 68 are formed.
[0047]
In the step shown in FIG. 10D, the polysilicon layer 63 is ion-doped with the gate electrode covered with the second copper diffusion prevention cover layer 68 as a mask to form a low concentration impurity region (n ⁻ ) LDD portion 63a.
[0048]
In the step shown in FIG. 11A, a layer thickness corresponding to the LDD length is further deposited on the second copper diffusion prevention cover layer 69 by using an electroless plating method. 69 is formed. Thereafter, arsenic is ion-doped again to form a high concentration impurity region (n ⁺ ) Source / drain electrodes 13b.
[0049]
In the step shown in FIG. 11B, after performing a heat treatment step such as laser annealing, flash lamp annealing, rapid thermal annealing (RTA), etc., the gate electrode covered with the first copper diffusion prevention cover layer 69 is used as a mask. Then, the copper diffusion preventing underlayer 65 is etched and removed in a self-aligning manner.
[0050]
In the step shown in FIG. 11C, an interlayer insulating layer 70 made of silicon oxide or the like is formed by PE-CVD, and then a mask pattern is formed by a photoresist layer (not shown), and the interlayer insulating layer 70 is etched. Then, a contact hole is formed so that the surface of the polysilicon layer 63 (source / drain region 63b) is exposed. The contact hole is filled with a metal such as aluminum (Al), for example, and a source / drain electrode 71 connected to the source / drain region 63b is formed.
[0051]
According to the above third embodiment, the length of the low-concentration region 63a on the source side and the drain side is equal to the layer thickness of the first copper diffusion prevention cover layer 69, as in the second embodiment described above. A method of manufacturing a thin film transistor having a GOLD structure that can be configured substantially equally, has a low-concentration region 63a having excellent length uniformity, does not require PEP, and can be selectively formed. Can be provided. In this case, since the copper diffusion preventing underlayer 65 is formed on the entire surface up to the annealing step for activating the impurities, temperature unevenness due to the annealing treatment is suppressed, temperature control is facilitated, and uniformity is achieved. Furthermore, damage to the gate insulating layer 64 in the ion doping process, which is a previous process, can be suppressed. In addition, since there is no decrease in film thickness due to the etching of the gate insulating film 64 in the etching process of the copper diffusion preventing underlayer 65, it is easy to set conditions for the ion doping process.
[0052]
Next, a first modification of the method for forming the copper wiring layer 8, 17 or 67 of the first, second and third embodiments described above will be described. In this modification, a metal seed layer 31 is provided under the copper wiring layer 8 (or 17). Here, the same reference numerals are used for the same layers as those described in FIGS. 1 to 3.
In the step shown in FIG. 6A, as in the step shown in FIG. 1A, the base insulating layer 2 is deposited on the substrate 1, and the island-like polysilicon layer 3 is further provided. A gate insulating layer 5 is deposited. A first metal diffusion preventing layer 6 and a metal seed layer 31 are formed on the gate insulating layer 5.
[0053]
In the step shown in FIG. 6B, a mask pattern of the photoresist layer 7 is formed on the metal seed layer 31 using PEP, and a groove is opened so that a region for forming the gate electrode is exposed. . A copper wiring layer 8 is selectively formed in the groove using an electroless plating method.
[0054]
In the step shown in FIG. 6C, after removing the photoresist layer 7, the metal seed layer 31 is etched and removed in a self-aligning manner using the copper wiring layer 8 as a mask. The copper wiring layer 8 is formed so as to have a sufficient layer thickness with respect to the layer thickness of the metal seed layer 31 so that this etching does not affect. Subsequently, the copper diffusion preventing base layer 6 is etched. The etching process for the metal seed layer 31 and the copper diffusion prevention base layer 6 may be performed in separate steps, or may be performed continuously or in the same step. Although the copper wiring layer 8 is used as a mask here, the metal diffusion prevention cover layer 18 may be provided as a mask as in the second embodiment, or a photoresist layer (not shown) may be formed on the copper wiring layer 8. The metal seed layer 31 and the first copper diffusion prevention layer 6 may be etched by providing a mask made of
[0055]
The subsequent manufacturing process shifts to the process shown in FIG. 2B in the first embodiment, and shifts to the process shown in FIG. 5A in the second embodiment. According to this first modification, by providing the metal seed layer 31, not only the electroless plating method but also the electrolytic plating method can be used.
[0056]
A second modification will be described.
In the step shown in FIG. 7A, as in the step shown in FIG. 1A, a base insulating layer 2 is deposited on the substrate 1, and an island-like polysilicon layer 3 is further provided. Then, the gate insulating layer 5 and the metal diffusion preventing underlayer 6 are formed.
[0057]
As shown in FIG. 7B, a mask made of a PEP photoresist layer 7 is formed on the metal diffusion prevention base layer 6, and a groove is opened so that a region for forming a gate electrode is exposed. The A metal seed layer 22 is selectively formed in the groove using an electroless plating method. Further, the copper wiring layer 8 is selectively formed on the metal seed layer 22 by using an electroless plating method or an electrolytic plating method.
In the step shown in FIG. 7C, the metal diffusion preventing underlayer 6 is removed by etching in a self-aligning manner using the copper wiring layer 8 as a mask.
[0058]
Although different from the manufacturing process of each embodiment described above, the photoresist layer 7 is removed after the process shown in FIG. Then, the second copper diffusion preventing layer 9 is formed so as to cover the copper wiring layer 8. The metal seed layer 31 and the first copper diffusion preventing layer 6 may be etched using the second copper diffusion preventing layer 9 as a mask. After this etching is completed, a third copper diffusion prevention layer (corresponding to the third copper diffusion prevention layer 19) is formed so as to cover the second copper diffusion prevention layer 9, the metal seed layer 22, and the first copper diffusion prevention layer 6. ) May be formed.
[0059]
According to the first modification, when the metal seed layer 22 is formed, an etching process is not required, and not only the electroless plating method but also the electrolytic plating method is used as a method for forming the copper wiring layer 8. it can.
In the above-described embodiment, the step of performing low-concentration or high-concentration impurities after etching the copper diffusion prevention base layer 6 has been described. However, the copper diffusion prevention base layer 6 is used as a protective layer at the time of impurity implantation. Alternatively, after the low concentration or high concentration impurity is applied, the copper diffusion preventing underlayer 6 can be etched using the first copper diffusion preventing layer 19 as a mask.
[0060]
In addition, the thin film transistor manufacturing method in the first, second, and third embodiments described above can be easily applied to a thin film transistor manufacturing method used for a liquid crystal display device, an EL display device, or the like.
[0061]
Although specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. For example, in the first, second, and third embodiments, copper is taken as an example of the electrode material. However, the present invention is not limited to this, and alloys including copper and other metals may be applied.
[0062]
Therefore, according to the method for manufacturing a thin film transistor of the present invention, the method is a method for manufacturing a thin film transistor having a GOLD structure in which the number of steps is short and the uniformity on the source side and the drain side is low. Furthermore, a highly reliable gate electrode made of copper surrounded by a metal diffusion prevention layer can be formed, and a copper wiring layer and a copper diffusion prevention cover layer can be selectively formed. Removal and disposal are suppressed, and wiring materials can be saved.
[0063]
Next, as a fourth embodiment, FIGS. 8A and 8B illustrate an example in which the thin film transistor of the present invention is used for a driver circuit of a liquid crystal display device or a transistor connected to a pixel electrode.
The liquid crystal display device 31 is arranged such that a transparent substrate (base layer) 41 provided with a counter electrode 43 on the inner surface side and a transparent substrate (base layer) 32 provided with a pixel electrode 33 on the inner surface side face each other. The periphery of the pair of transparent substrates 41 and 32 is bonded to a frame-shaped sealing material 44, and a liquid crystal layer 42 filled with liquid crystal is provided therein. As these transparent substrates 41 and 32, a glass plate or a quartz glass plate can be used, for example.
[0064]
A plurality of pixel electrodes 33 provided on the inner surface side of the transparent substrate 32 are arranged in a matrix in the row direction and the outer direction, and each of these pixel electrodes 33 is provided with a plurality of TFTs 34 to be electrically connected. Connected. The gates of these TFTs 34 are provided with scanning wirings 36 along the row direction of the pixel electrodes 33, and the sources are provided with signal wirings 35 along the column direction, which are electrically connected to each other. One ends of these scanning wirings 36 are respectively connected to a plurality of scanning wiring terminals (not shown) provided at one side edge of the rear transparent substrate 32. These scanning wiring terminals are connected to the scanning line driving circuit 37.
In addition, one end of each of the signal wirings 35 is connected to a signal line driving circuit 38 via a terminal (not shown) of a plurality of signal wirings 35 provided at one end edge of the rear transparent substrate 32. Yes.
[0065]
The scanning line driving circuit 37 and the signal line driving circuit 38 are connected to the liquid crystal controller 39. The liquid crystal controller 39 receives, for example, an image signal and a synchronization signal supplied from the outside, and generates a pixel video signal Vpix, a vertical scanning control signal YCT, and a horizontal scanning control signal XCT.
[0066]
A single film-like transparent counter electrode 43 provided on the inner surface of the transparent substrate 41 faces the plurality of pixel electrodes 33. A color filter is provided on the inner surface of the transparent substrate 41 so as to correspond to the plurality of pixel portions where the plurality of pixel electrodes 33 and the facing electrode 43 face each other, and a light shielding film is provided corresponding to the region between the pixel portions. May be provided.
[0067]
A polarizing plate (not shown) is provided outside the pair of transparent substrates 41 and 32. In the transmissive liquid crystal display device 31, a surface light source (not shown) is provided on the rear side of the rear see-through substrate 32. The liquid crystal display device 30 may be a reflective type or a transflective type.
[0068]
FIG. 9 shows a specific structural example of a thin film transistor used in the pixel circuit of the liquid crystal display device described above. In this example, the thin film transistor shown in FIG. 3D in the first embodiment described above is used.
The thin film transistor is formed on the base insulating layer 2 on a transparent substrate (array substrate) 32 made of glass or the like, and the thin film transistor 51 is provided by the manufacturing process in the first embodiment described above. A source electrode 12a and a drain electrode 12b are formed so as to fill a contact hole provided in the interlayer insulating layer 10. Further, a passivation layer (SiNx) 52 and a planarization layer 53 are laminated so that the drain electrode portion is exposed in the upper layer. A pixel electrode (ITO) 54 connected to the drain electrode 12b is provided and covered with an alignment film 55 made of polyimide. On the other hand, a counter electrode 43 is provided on the opposing transparent substrate 41 (opposite surface side) and is covered with an alignment film 56 made of polyimide. A liquid crystal layer 42 is interposed between the alignment films 55 and 56.
[0069]
As described above, the thin film transistor of the present invention can be easily used for a driver circuit of a display device typified by a liquid crystal display device or an EL device or a transistor connected to a pixel electrode.
[0070]
In the above embodiment, the formation of the source region and the drain region has been described with respect to the step of implanting a high concentration of impurities using the metal diffusion prevention cover layer provided so as to cover the surface of the gate electrode as a mask. One of the drain regions may be formed by implanting a high concentration of impurities using the metal diffusion prevention cover layer as a mask.
[0071]
【The invention's effect】
As described above in detail, according to the present invention, by using a low resistance metal wiring made of copper or the like on a large area substrate, variation in LDD length is reduced, and the manufacturing cost is reduced by reducing the number of manufacturing steps. A thin film transistor to be realized and a manufacturing method thereof, a display device including the thin film transistor, and a manufacturing method of the display device can be provided.
[Brief description of the drawings]
FIG. 1 is a process diagram for explaining a thin film transistor manufacturing method according to a first embodiment of the thin film transistor manufacturing method of the present invention;
FIG. 2 is a process diagram for explaining the thin film transistor manufacturing method according to the first embodiment following FIG. 1;
FIG. 3 is a process diagram for describing the manufacturing method of the thin film transistor according to the first embodiment following FIG. 2;
FIG. 4 is a process diagram for explaining a thin film transistor manufacturing method according to a second embodiment of the thin film transistor manufacturing method of the present invention;
FIG. 5 is a process diagram for explaining the manufacturing method of the thin film transistor according to the second embodiment following FIG. 4;
FIG. 6 is a process diagram for describing a first modification.
FIG. 7 is a process diagram for describing a second modification.
FIG. 8 is a diagram for explaining an example in which a thin film transistor of the present invention is used in a driving circuit of a liquid crystal display device as a third embodiment.
FIG. 9 is a diagram illustrating a specific structural example of a thin film transistor used in a driving circuit of a liquid crystal display device according to a third embodiment.
FIG. 10 is a process diagram for explaining a thin film transistor manufacturing method according to a third embodiment of the thin film transistor manufacturing method of the present invention.
FIG. 11 is a process diagram for describing the manufacturing method of the thin film transistor according to the third embodiment following FIG. 10;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Base insulating layer, 3 '... Amorphous silicon layer, 3 ... Polysilicon layer, 3a ... LDD region, 3b ... Source / drain region, 4, 7, 11 ... Photoresist layer, 5 ... Gate insulating layer , 6 ... 1st copper diffusion prevention layer, 7a ... groove | channel, 8 ... Copper wiring layer, 9 ... 2nd copper diffusion prevention layer, 10 ... Interlayer insulation layer, 11a ... Contact hole, 12 ... Source-drain electrode.

Claims (15)

Providing a semiconductor layer;
Providing a gate insulating layer on the semiconductor layer;
Providing a metal diffusion preventing underlayer on the gate insulating layer;
Providing a gate electrode made of a metal layer on the metal diffusion prevention base layer;
A method of manufacturing a thin film transistor, wherein a source region and a drain region are formed separately from the semiconductor layer below the gate electrode,
The formation of at least one of the source region and the drain region is a step of implanting a high concentration of impurities using a metal diffusion prevention cover layer provided so as to cover the surface of the gate electrode as a mask;
A method for producing a thin film transistor, comprising: Providing a semiconductor layer;
Providing a gate insulating layer on the semiconductor layer;
Providing a metal diffusion preventing underlayer on the gate insulating layer;
Providing a gate electrode made of a metal layer on the metal diffusion prevention base layer;
Etching the metal diffusion prevention layer;
Using the metal layer as a mask, implanting low-concentration impurities into the semiconductor layer;
Providing a first metal diffusion prevention cover layer so as to cover the surface of the metal layer;
Using the first metal diffusion prevention cover layer as a mask, high-concentration impurity implantation is performed on the semiconductor layer into which the low-concentration impurity is implanted with a width corresponding to the thickness of the first metal diffusion prevention layer. A step of activating the implanted impurities;
A method for producing a thin film transistor, comprising: Providing a semiconductor layer;
Providing a gate insulating layer on the semiconductor layer;
Providing a metal diffusion preventing underlayer on the gate insulating layer;
Providing a gate electrode made of a metal layer on the metal diffusion prevention base layer;
Providing a second metal diffusion prevention cover layer so as to cover the surface of the metal layer;
Etching the metal diffusion preventing underlayer; and
Performing a low concentration impurity implantation into the semiconductor layer using the second metal diffusion prevention cover layer as a mask;
Further providing a first metal diffusion prevention cover layer on the second metal diffusion prevention cover layer;
Using the first metal diffusion prevention layer as a mask, performing a high concentration impurity implantation on the semiconductor layer into which the low concentration impurity is implanted with a width corresponding to the thickness of the first metal diffusion prevention layer And activating the implanted impurities;
A method for producing a thin film transistor, comprising: The step of providing the gate electrode made of the metal layer, the step of selectively providing the metal layer on the metal diffusion prevention base layer using a mask made of a photosensitive resin;
The method of manufacturing a thin film transistor according to claim 2 or 3, wherein Providing the metal seed layer on the metal diffusion prevention underlayer before the step of providing the gate electrode comprising the metal layer before the formation of the metal layer;
A step of selectively providing a metal layer using a mask made of a photosensitive resin;
Etching at least the metal seed layer;
The method for producing a thin film transistor according to claim 2 or 3, wherein: Providing the gate electrode made of the metal layer,
A step of selectively providing a metal seed layer on the metal diffusion prevention underlayer using a mask made of a photosensitive resin;
Providing a metal layer on the metal seed layer;
The method for producing a thin film transistor according to claim 2 or 3, wherein: 4. The thin film transistor according to claim 2, wherein the first and second metal diffusion prevention cover layers are provided so as to selectively surround the metal layer by an electroless plating method. Method. 4. The method of manufacturing a thin film transistor according to claim 2, wherein the step of providing the metal layer includes a step of selectively providing a copper layer or a metal layer containing copper. Etching the first metal diffusion prevention layer includes etching using the metal layer, the first metal diffusion prevention cover layer or the second metal diffusion prevention cover layer as a mask. The method for producing a thin film transistor according to claim 2 or 3, characterized in that: 4. The method of manufacturing a thin film transistor according to claim 2, wherein the impurity implantation is performed after etching the metal diffusion preventing base layer. 4. The method of manufacturing a thin film transistor according to claim 2, wherein the impurity implantation is performed through the metal diffusion prevention base layer. 4. The method of manufacturing a thin film transistor according to claim 2, wherein the step of etching the metal diffusion prevention base layer is performed after the step of activating the semiconductor layer into which the impurity has been implanted. A semiconductor layer;
A gate insulating layer provided on the semiconductor layer;
A metal diffusion prevention base layer provided on the gate insulating layer;
A gate electrode made of a metal layer provided on the metal diffusion prevention base layer;
A metal diffusion prevention cover layer provided on the surface of the gate electrode;
A thin film transistor having a source region and a drain region provided separately from the semiconductor layer under the gate electrode,
A thin film transistor, wherein at least one of the source region and the drain region is a high concentration impurity implantation formed using the metal diffusion prevention cover layer as a mask. A semiconductor layer provided on a substrate;
A gate insulating layer provided on the semiconductor layer;
A metal diffusion prevention base layer provided on the gate insulating layer;
A gate electrode made of a metal layer provided on the metal diffusion prevention base layer;
A metal diffusion prevention cover layer provided on the surface of the gate electrode;
A source region and a drain region provided separately from the semiconductor layer below the gate electrode;
At least one of the source region and the drain region includes a thin film transistor into which a high-concentration impurity is implanted using the metal diffusion prevention cover layer as a mask. A semiconductor layer is provided on the substrate,
A gate insulating layer is provided on this semiconductor layer,
A metal diffusion prevention base layer is provided on the gate insulating layer,
A gate electrode made of a metal layer is provided on the metal diffusion prevention base layer,
A metal diffusion prevention cover layer is provided on the surface of the gate electrode,
A method of manufacturing a liquid crystal display device in which a source region and a drain region are provided separately from the semiconductor layer below the gate electrode,
At least one of the source region and the drain region is formed by implanting impurities at a high concentration using the metal diffusion prevention cover layer as a mask.

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